cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

stm32f2xx_timer.h (2928B)

      1/*
      2 * STM32F2XX Timer
      3 *
      4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
      5 *
      6 * Permission is hereby granted, free of charge, to any person obtaining a copy
      7 * of this software and associated documentation files (the "Software"), to deal
      8 * in the Software without restriction, including without limitation the rights
      9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     10 * copies of the Software, and to permit persons to whom the Software is
     11 * furnished to do so, subject to the following conditions:
     12 *
     13 * The above copyright notice and this permission notice shall be included in
     14 * all copies or substantial portions of the Software.
     15 *
     16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
     19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     22 * THE SOFTWARE.
     23 */
     24
     25#ifndef HW_STM32F2XX_TIMER_H
     26#define HW_STM32F2XX_TIMER_H
     27
     28#include "hw/sysbus.h"
     29#include "qemu/timer.h"
     30#include "qom/object.h"
     31
     32#define TIM_CR1      0x00
     33#define TIM_CR2      0x04
     34#define TIM_SMCR     0x08
     35#define TIM_DIER     0x0C
     36#define TIM_SR       0x10
     37#define TIM_EGR      0x14
     38#define TIM_CCMR1    0x18
     39#define TIM_CCMR2    0x1C
     40#define TIM_CCER     0x20
     41#define TIM_CNT      0x24
     42#define TIM_PSC      0x28
     43#define TIM_ARR      0x2C
     44#define TIM_CCR1     0x34
     45#define TIM_CCR2     0x38
     46#define TIM_CCR3     0x3C
     47#define TIM_CCR4     0x40
     48#define TIM_DCR      0x48
     49#define TIM_DMAR     0x4C
     50#define TIM_OR       0x50
     51
     52#define TIM_CR1_CEN   1
     53
     54#define TIM_EGR_UG 1
     55
     56#define TIM_CCER_CC2E   (1 << 4)
     57#define TIM_CCMR1_OC2M2 (1 << 14)
     58#define TIM_CCMR1_OC2M1 (1 << 13)
     59#define TIM_CCMR1_OC2M0 (1 << 12)
     60#define TIM_CCMR1_OC2PE (1 << 11)
     61
     62#define TIM_DIER_UIE  1
     63
     64#define TYPE_STM32F2XX_TIMER "stm32f2xx-timer"
     65typedef struct STM32F2XXTimerState STM32F2XXTimerState;
     66DECLARE_INSTANCE_CHECKER(STM32F2XXTimerState, STM32F2XXTIMER,
     67                         TYPE_STM32F2XX_TIMER)
     68
     69struct STM32F2XXTimerState {
     70    /* <private> */
     71    SysBusDevice parent_obj;
     72
     73    /* <public> */
     74    MemoryRegion iomem;
     75    QEMUTimer *timer;
     76    qemu_irq irq;
     77
     78    int64_t tick_offset;
     79    uint64_t hit_time;
     80    uint64_t freq_hz;
     81
     82    uint32_t tim_cr1;
     83    uint32_t tim_cr2;
     84    uint32_t tim_smcr;
     85    uint32_t tim_dier;
     86    uint32_t tim_sr;
     87    uint32_t tim_egr;
     88    uint32_t tim_ccmr1;
     89    uint32_t tim_ccmr2;
     90    uint32_t tim_ccer;
     91    uint32_t tim_psc;
     92    uint32_t tim_arr;
     93    uint32_t tim_ccr1;
     94    uint32_t tim_ccr2;
     95    uint32_t tim_ccr3;
     96    uint32_t tim_ccr4;
     97    uint32_t tim_dcr;
     98    uint32_t tim_dmar;
     99    uint32_t tim_or;
    100};
    101
    102#endif /* HW_STM32F2XX_TIMER_H */