cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

tc27x_soc.h (2935B)

      1/*
      2 * Infineon tc27x SoC System emulation.
      3 *
      4 * Copyright (c) 2020 Andreas Konopik <andreas.konopik@efs-auto.de>
      5 * Copyright (c) 2020 David Brenken <david.brenken@efs-auto.de>
      6 *
      7 * This library is free software; you can redistribute it and/or
      8 * modify it under the terms of the GNU Lesser General Public
      9 * License as published by the Free Software Foundation; either
     10 * version 2 of the License, or (at your option) any later version.
     11 *
     12 * This library is distributed in the hope that it will be useful,
     13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     15 * Lesser General Public License for more details.
     16 *
     17 * You should have received a copy of the GNU Lesser General Public
     18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
     19 */
     20
     21#ifndef TC27X_SoC_H
     22#define TC27X_SoC_H
     23
     24#include "hw/sysbus.h"
     25#include "target/tricore/cpu.h"
     26#include "qom/object.h"
     27
     28#define TYPE_TC27X_SOC ("tc27x-soc")
     29OBJECT_DECLARE_TYPE(TC27XSoCState, TC27XSoCClass, TC27X_SOC)
     30
     31typedef struct TC27XSoCCPUMemState {
     32
     33    MemoryRegion dspr;
     34    MemoryRegion pspr;
     35
     36    MemoryRegion dcache;
     37    MemoryRegion dtag;
     38    MemoryRegion pcache;
     39    MemoryRegion ptag;
     40
     41} TC27XSoCCPUMemState;
     42
     43typedef struct TC27XSoCFlashMemState {
     44
     45    MemoryRegion pflash0_c;
     46    MemoryRegion pflash1_c;
     47    MemoryRegion pflash0_u;
     48    MemoryRegion pflash1_u;
     49    MemoryRegion dflash0;
     50    MemoryRegion dflash1;
     51    MemoryRegion olda_c;
     52    MemoryRegion olda_u;
     53    MemoryRegion brom_c;
     54    MemoryRegion brom_u;
     55    MemoryRegion lmuram_c;
     56    MemoryRegion lmuram_u;
     57    MemoryRegion emem_c;
     58    MemoryRegion emem_u;
     59
     60} TC27XSoCFlashMemState;
     61
     62typedef struct TC27XSoCState {
     63    /*< private >*/
     64    SysBusDevice parent_obj;
     65
     66    /*< public >*/
     67    TriCoreCPU cpu;
     68
     69    MemoryRegion dsprX;
     70    MemoryRegion psprX;
     71
     72    TC27XSoCCPUMemState cpu0mem;
     73    TC27XSoCCPUMemState cpu1mem;
     74    TC27XSoCCPUMemState cpu2mem;
     75
     76    TC27XSoCFlashMemState flashmem;
     77
     78} TC27XSoCState;
     79
     80typedef struct MemmapEntry {
     81    hwaddr base;
     82    hwaddr size;
     83} MemmapEntry;
     84
     85typedef struct TC27XSoCClass {
     86    DeviceClass parent_class;
     87
     88    const char *name;
     89    const char *cpu_type;
     90    const MemmapEntry *memmap;
     91    uint32_t num_cpus;
     92} TC27XSoCClass;
     93
     94enum {
     95    TC27XD_DSPR2,
     96    TC27XD_DCACHE2,
     97    TC27XD_DTAG2,
     98    TC27XD_PSPR2,
     99    TC27XD_PCACHE2,
    100    TC27XD_PTAG2,
    101    TC27XD_DSPR1,
    102    TC27XD_DCACHE1,
    103    TC27XD_DTAG1,
    104    TC27XD_PSPR1,
    105    TC27XD_PCACHE1,
    106    TC27XD_PTAG1,
    107    TC27XD_DSPR0,
    108    TC27XD_PSPR0,
    109    TC27XD_PCACHE0,
    110    TC27XD_PTAG0,
    111    TC27XD_PFLASH0_C,
    112    TC27XD_PFLASH1_C,
    113    TC27XD_OLDA_C,
    114    TC27XD_BROM_C,
    115    TC27XD_LMURAM_C,
    116    TC27XD_EMEM_C,
    117    TC27XD_PFLASH0_U,
    118    TC27XD_PFLASH1_U,
    119    TC27XD_DFLASH0,
    120    TC27XD_DFLASH1,
    121    TC27XD_OLDA_U,
    122    TC27XD_BROM_U,
    123    TC27XD_LMURAM_U,
    124    TC27XD_EMEM_U,
    125    TC27XD_PSPRX,
    126    TC27XD_DSPRX,
    127};
    128
    129#endif