cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

hcd-musb.h (1374B)

      1/*
      2 * "Inventra" High-speed Dual-Role Controller (MUSB-HDRC), Mentor Graphics,
      3 * USB2.0 OTG compliant core used in various chips.
      4 *
      5 * Only host-mode and non-DMA accesses are currently supported.
      6 *
      7 * Copyright (C) 2008 Nokia Corporation
      8 * Written by Andrzej Zaborowski <balrog@zabor.org>
      9 *
     10 * SPDX-License-Identifier: GPL-2.0-or-later
     11 */
     12
     13#ifndef HW_USB_MUSB_H
     14#define HW_USB_MUSB_H
     15
     16enum musb_irq_source_e {
     17    musb_irq_suspend = 0,
     18    musb_irq_resume,
     19    musb_irq_rst_babble,
     20    musb_irq_sof,
     21    musb_irq_connect,
     22    musb_irq_disconnect,
     23    musb_irq_vbus_request,
     24    musb_irq_vbus_error,
     25    musb_irq_rx,
     26    musb_irq_tx,
     27    musb_set_vbus,
     28    musb_set_session,
     29    /* Add new interrupts here */
     30    musb_irq_max /* total number of interrupts defined */
     31};
     32
     33/* TODO convert hcd-musb to QOM/qdev and remove MUSBReadFunc/MUSBWriteFunc */
     34typedef void MUSBWriteFunc(void *opaque, hwaddr addr, uint32_t value);
     35typedef uint32_t MUSBReadFunc(void *opaque, hwaddr addr);
     36extern MUSBReadFunc * const musb_read[];
     37extern MUSBWriteFunc * const musb_write[];
     38
     39typedef struct MUSBState MUSBState;
     40
     41MUSBState *musb_init(DeviceState *parent_device, int gpio_base);
     42void musb_reset(MUSBState *s);
     43uint32_t musb_core_intr_get(MUSBState *s);
     44void musb_core_intr_clear(MUSBState *s, uint32_t mask);
     45void musb_set_size(MUSBState *s, int epnum, int size, int is_tx);
     46
     47#endif