cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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sbsa_gwdt.h (1968B)

      1/*
      2 * Copyright (c) 2020 Linaro Limited
      3 *
      4 * Authors:
      5 *  Shashi Mallela <shashi.mallela@linaro.org>
      6 *
      7 * This work is licensed under the terms of the GNU GPL, version 2 or (at your
      8 * option) any later version.  See the COPYING file in the top-level directory.
      9 *
     10 */
     11
     12#ifndef WDT_SBSA_GWDT_H
     13#define WDT_SBSA_GWDT_H
     14
     15#include "qemu/bitops.h"
     16#include "hw/sysbus.h"
     17#include "hw/irq.h"
     18
     19#define TYPE_WDT_SBSA "sbsa_gwdt"
     20#define SBSA_GWDT(obj) \
     21    OBJECT_CHECK(SBSA_GWDTState, (obj), TYPE_WDT_SBSA)
     22#define SBSA_GWDT_CLASS(klass) \
     23    OBJECT_CLASS_CHECK(SBSA_GWDTClass, (klass), TYPE_WDT_SBSA)
     24#define SBSA_GWDT_GET_CLASS(obj) \
     25    OBJECT_GET_CLASS(SBSA_GWDTClass, (obj), TYPE_WDT_SBSA)
     26
     27/* SBSA Generic Watchdog register definitions */
     28/* refresh frame */
     29#define SBSA_GWDT_WRR       0x000
     30
     31/* control frame */
     32#define SBSA_GWDT_WCS       0x000
     33#define SBSA_GWDT_WOR       0x008
     34#define SBSA_GWDT_WORU      0x00C
     35#define SBSA_GWDT_WCV       0x010
     36#define SBSA_GWDT_WCVU      0x014
     37
     38/* Watchdog Interface Identification Register */
     39#define SBSA_GWDT_W_IIDR    0xFCC
     40
     41/* Watchdog Control and Status Register Bits */
     42#define SBSA_GWDT_WCS_EN    BIT(0)
     43#define SBSA_GWDT_WCS_WS0   BIT(1)
     44#define SBSA_GWDT_WCS_WS1   BIT(2)
     45
     46#define SBSA_GWDT_WOR_MASK  0x0000FFFF
     47
     48/*
     49 * Watchdog Interface Identification Register definition
     50 * considering JEP106 code for ARM in Bits [11:0]
     51 */
     52#define SBSA_GWDT_ID        0x1043B
     53
     54/* 2 Separate memory regions for each of refresh & control register frames */
     55#define SBSA_GWDT_RMMIO_SIZE 0x1000
     56#define SBSA_GWDT_CMMIO_SIZE 0x1000
     57
     58#define SBSA_TIMER_FREQ      62500000 /* Hz */
     59
     60typedef struct SBSA_GWDTState {
     61    /* <private> */
     62    SysBusDevice parent_obj;
     63
     64    /*< public >*/
     65    MemoryRegion rmmio;
     66    MemoryRegion cmmio;
     67    qemu_irq irq;
     68
     69    QEMUTimer *timer;
     70
     71    uint32_t id;
     72    uint32_t wcs;
     73    uint32_t worl;
     74    uint32_t woru;
     75    uint32_t wcvl;
     76    uint32_t wcvu;
     77} SBSA_GWDTState;
     78
     79#endif /* WDT_SBSA_GWDT_H */