cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

wdt_aspeed.h (1194B)

      1/*
      2 * ASPEED Watchdog Controller
      3 *
      4 * Copyright (C) 2016-2017 IBM Corp.
      5 *
      6 * This code is licensed under the GPL version 2 or later. See the
      7 * COPYING file in the top-level directory.
      8 */
      9
     10#ifndef WDT_ASPEED_H
     11#define WDT_ASPEED_H
     12
     13#include "hw/misc/aspeed_scu.h"
     14#include "hw/sysbus.h"
     15#include "qom/object.h"
     16
     17#define TYPE_ASPEED_WDT "aspeed.wdt"
     18OBJECT_DECLARE_TYPE(AspeedWDTState, AspeedWDTClass, ASPEED_WDT)
     19#define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400"
     20#define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500"
     21#define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600"
     22
     23#define ASPEED_WDT_REGS_MAX        (0x20 / 4)
     24
     25struct AspeedWDTState {
     26    /*< private >*/
     27    SysBusDevice parent_obj;
     28    QEMUTimer *timer;
     29
     30    /*< public >*/
     31    MemoryRegion iomem;
     32    uint32_t regs[ASPEED_WDT_REGS_MAX];
     33
     34    AspeedSCUState *scu;
     35    uint32_t pclk_freq;
     36};
     37
     38
     39struct AspeedWDTClass {
     40    SysBusDeviceClass parent_class;
     41
     42    uint32_t offset;
     43    uint32_t ext_pulse_width_mask;
     44    uint32_t reset_ctrl_reg;
     45    void (*reset_pulse)(AspeedWDTState *s, uint32_t property);
     46    void (*wdt_reload)(AspeedWDTState *s);
     47    uint64_t (*sanitize_ctrl)(uint64_t data);
     48};
     49
     50#endif /* WDT_ASPEED_H */