cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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target_cpu.h (1502B)

      1/*
      2 * ARM AArch64 specific CPU ABI and functions for linux-user
      3 *
      4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
      5 *
      6 * This library is free software; you can redistribute it and/or
      7 * modify it under the terms of the GNU Lesser General Public
      8 * License as published by the Free Software Foundation; either
      9 * version 2.1 of the License, or (at your option) any later version.
     10 *
     11 * This library is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     14 * Lesser General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU Lesser General Public
     17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
     18 */
     19#ifndef AARCH64_TARGET_CPU_H
     20#define AARCH64_TARGET_CPU_H
     21
     22static inline void cpu_clone_regs_child(CPUARMState *env, target_ulong newsp,
     23                                        unsigned flags)
     24{
     25    if (newsp) {
     26        env->xregs[31] = newsp;
     27    }
     28    env->xregs[0] = 0;
     29}
     30
     31static inline void cpu_clone_regs_parent(CPUARMState *env, unsigned flags)
     32{
     33}
     34
     35static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
     36{
     37    /* Note that AArch64 Linux keeps the TLS pointer in TPIDR; this is
     38     * different from AArch32 Linux, which uses TPIDRRO.
     39     */
     40    env->cp15.tpidr_el[0] = newtls;
     41}
     42
     43static inline abi_ulong get_sp_from_cpustate(CPUARMState *state)
     44{
     45   return state->xregs[31];
     46}
     47#endif