cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

fpopcode.c (3016B)

      1/*
      2    NetWinder Floating Point Emulator
      3    (c) Rebel.COM, 1998,1999
      4
      5    Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
      6
      7    This program is free software; you can redistribute it and/or modify
      8    it under the terms of the GNU General Public License as published by
      9    the Free Software Foundation; either version 2 of the License, or
     10    (at your option) any later version.
     11
     12    This program is distributed in the hope that it will be useful,
     13    but WITHOUT ANY WARRANTY; without even the implied warranty of
     14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     15    GNU General Public License for more details.
     16
     17    You should have received a copy of the GNU General Public License
     18    along with this program; if not, see <http://www.gnu.org/licenses/>.
     19*/
     20
     21#include "qemu/osdep.h"
     22#include "fpa11.h"
     23#include "fpu/softfloat.h"
     24#include "fpopcode.h"
     25#include "fpsr.h"
     26//#include "fpmodule.h"
     27//#include "fpmodule.inl"
     28
     29const floatx80 floatx80Constant[] = {
     30  { 0x0000000000000000ULL, 0x0000},	/* extended 0.0 */
     31  { 0x8000000000000000ULL, 0x3fff},	/* extended 1.0 */
     32  { 0x8000000000000000ULL, 0x4000},	/* extended 2.0 */
     33  { 0xc000000000000000ULL, 0x4000},	/* extended 3.0 */
     34  { 0x8000000000000000ULL, 0x4001},	/* extended 4.0 */
     35  { 0xa000000000000000ULL, 0x4001},	/* extended 5.0 */
     36  { 0x8000000000000000ULL, 0x3ffe},	/* extended 0.5 */
     37  { 0xa000000000000000ULL, 0x4002}	/* extended 10.0 */
     38};
     39
     40const float64 float64Constant[] = {
     41  const_float64(0x0000000000000000ULL),		/* double 0.0 */
     42  const_float64(0x3ff0000000000000ULL),		/* double 1.0 */
     43  const_float64(0x4000000000000000ULL),		/* double 2.0 */
     44  const_float64(0x4008000000000000ULL),		/* double 3.0 */
     45  const_float64(0x4010000000000000ULL),		/* double 4.0 */
     46  const_float64(0x4014000000000000ULL),		/* double 5.0 */
     47  const_float64(0x3fe0000000000000ULL),		/* double 0.5 */
     48  const_float64(0x4024000000000000ULL)			/* double 10.0 */
     49};
     50
     51const float32 float32Constant[] = {
     52  const_float32(0x00000000),				/* single 0.0 */
     53  const_float32(0x3f800000),				/* single 1.0 */
     54  const_float32(0x40000000),				/* single 2.0 */
     55  const_float32(0x40400000),				/* single 3.0 */
     56  const_float32(0x40800000),				/* single 4.0 */
     57  const_float32(0x40a00000),				/* single 5.0 */
     58  const_float32(0x3f000000),				/* single 0.5 */
     59  const_float32(0x41200000)				/* single 10.0 */
     60};
     61
     62unsigned int getRegisterCount(const unsigned int opcode)
     63{
     64  unsigned int nRc;
     65
     66  switch (opcode & MASK_REGISTER_COUNT)
     67  {
     68    case 0x00000000: nRc = 4; break;
     69    case 0x00008000: nRc = 1; break;
     70    case 0x00400000: nRc = 2; break;
     71    case 0x00408000: nRc = 3; break;
     72    default: nRc = 0;
     73  }
     74
     75  return(nRc);
     76}
     77
     78unsigned int getDestinationSize(const unsigned int opcode)
     79{
     80  unsigned int nRc;
     81
     82  switch (opcode & MASK_DESTINATION_SIZE)
     83  {
     84    case 0x00000000: nRc = typeSingle; break;
     85    case 0x00000080: nRc = typeDouble; break;
     86    case 0x00080000: nRc = typeExtended; break;
     87    default: nRc = typeNone;
     88  }
     89
     90  return(nRc);
     91}