cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

optrom.h (2602B)

      1/*
      2 * Common Option ROM Functions for C code
      3 *
      4 * This program is free software; you can redistribute it and/or modify
      5 * it under the terms of the GNU General Public License as published by
      6 * the Free Software Foundation; either version 2 of the License, or
      7 * (at your option) any later version.
      8 *
      9 * This program is distributed in the hope that it will be useful,
     10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
     12 * GNU General Public License for more details.
     13 *
     14 * You should have received a copy of the GNU General Public License
     15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
     16 *
     17 * Copyright (c) 2015-2019 Red Hat Inc.
     18 *   Authors:
     19 *     Marc Marí <marc.mari.barcelo@gmail.com>
     20 *     Richard W.M. Jones <rjones@redhat.com>
     21 *     Stefano Garzarella <sgarzare@redhat.com>
     22 */
     23
     24#ifndef OPTROM_H
     25#define OPTROM_H
     26
     27#include <stdint.h>
     28#include "../../include/standard-headers/linux/qemu_fw_cfg.h"
     29
     30#define barrier() asm("" : : : "memory")
     31
     32#ifdef __clang__
     33#define ADDR32
     34#else
     35#define ADDR32 "addr32 "
     36#endif
     37
     38static inline void outb(uint8_t value, uint16_t port)
     39{
     40    asm volatile("outb %0, %w1" : : "a"(value), "Nd"(port));
     41}
     42
     43static inline void outw(uint16_t value, uint16_t port)
     44{
     45    asm volatile("outw %0, %w1" : : "a"(value), "Nd"(port));
     46}
     47
     48static inline void outl(uint32_t value, uint16_t port)
     49{
     50    asm volatile("outl %0, %w1" : : "a"(value), "Nd"(port));
     51}
     52
     53static inline uint8_t inb(uint16_t port)
     54{
     55    uint8_t value;
     56
     57    asm volatile("inb %w1, %0" : "=a"(value) : "Nd"(port));
     58    return value;
     59}
     60
     61static inline uint16_t inw(uint16_t port)
     62{
     63    uint16_t value;
     64
     65    asm volatile("inw %w1, %0" : "=a"(value) : "Nd"(port));
     66    return value;
     67}
     68
     69static inline uint32_t inl(uint16_t port)
     70{
     71    uint32_t value;
     72
     73    asm volatile("inl %w1, %0" : "=a"(value) : "Nd"(port));
     74    return value;
     75}
     76
     77static inline void insb(uint16_t port, uint8_t *buf, uint32_t len)
     78{
     79    asm volatile("rep insb %%dx, %%es:(%%edi)"
     80                 : "+c"(len), "+D"(buf) : "d"(port) : "memory");
     81}
     82
     83static inline uint32_t bswap32(uint32_t x)
     84{
     85    asm("bswapl %0" : "=r" (x) : "0" (x));
     86    return x;
     87}
     88
     89static inline uint64_t bswap64(uint64_t x)
     90{
     91    asm("bswapl %%eax; bswapl %%edx; xchg %%eax, %%edx" : "=A" (x) : "0" (x));
     92    return x;
     93}
     94
     95static inline uint64_t cpu_to_be64(uint64_t x)
     96{
     97    return bswap64(x);
     98}
     99
    100static inline uint32_t cpu_to_be32(uint32_t x)
    101{
    102    return bswap32(x);
    103}
    104
    105static inline uint32_t be32_to_cpu(uint32_t x)
    106{
    107    return bswap32(x);
    108}
    109
    110#endif /* OPTROM_H */