cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

cpu-qom.h (2782B)

      1/*
      2 * QEMU ARM CPU
      3 *
      4 * Copyright (c) 2012 SUSE LINUX Products GmbH
      5 *
      6 * This program is free software; you can redistribute it and/or
      7 * modify it under the terms of the GNU General Public License
      8 * as published by the Free Software Foundation; either version 2
      9 * of the License, or (at your option) any later version.
     10 *
     11 * This program is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     14 * GNU General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU General Public License
     17 * along with this program; if not, see
     18 * <http://www.gnu.org/licenses/gpl-2.0.html>
     19 */
     20#ifndef QEMU_ARM_CPU_QOM_H
     21#define QEMU_ARM_CPU_QOM_H
     22
     23#include "hw/core/cpu.h"
     24#include "qom/object.h"
     25
     26struct arm_boot_info;
     27
     28#define TYPE_ARM_CPU "arm-cpu"
     29
     30OBJECT_DECLARE_TYPE(ARMCPU, ARMCPUClass,
     31                    ARM_CPU)
     32
     33#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
     34
     35typedef struct ARMCPUInfo {
     36    const char *name;
     37    void (*initfn)(Object *obj);
     38    void (*class_init)(ObjectClass *oc, void *data);
     39} ARMCPUInfo;
     40
     41void arm_cpu_register(const ARMCPUInfo *info);
     42void aarch64_cpu_register(const ARMCPUInfo *info);
     43
     44/**
     45 * ARMCPUClass:
     46 * @parent_realize: The parent class' realize handler.
     47 * @parent_reset: The parent class' reset handler.
     48 *
     49 * An ARM CPU model.
     50 */
     51struct ARMCPUClass {
     52    /*< private >*/
     53    CPUClass parent_class;
     54    /*< public >*/
     55
     56    const ARMCPUInfo *info;
     57    DeviceRealize parent_realize;
     58    DeviceReset parent_reset;
     59};
     60
     61
     62#define TYPE_AARCH64_CPU "aarch64-cpu"
     63typedef struct AArch64CPUClass AArch64CPUClass;
     64DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
     65                       TYPE_AARCH64_CPU)
     66
     67struct AArch64CPUClass {
     68    /*< private >*/
     69    ARMCPUClass parent_class;
     70    /*< public >*/
     71};
     72
     73void register_cp_regs_for_features(ARMCPU *cpu);
     74void init_cpreg_list(ARMCPU *cpu);
     75
     76/* Callback functions for the generic timer's timers. */
     77void arm_gt_ptimer_cb(void *opaque);
     78void arm_gt_vtimer_cb(void *opaque);
     79void arm_gt_htimer_cb(void *opaque);
     80void arm_gt_stimer_cb(void *opaque);
     81void arm_gt_hvtimer_cb(void *opaque);
     82
     83#define ARM_AFF0_SHIFT 0
     84#define ARM_AFF0_MASK  (0xFFULL << ARM_AFF0_SHIFT)
     85#define ARM_AFF1_SHIFT 8
     86#define ARM_AFF1_MASK  (0xFFULL << ARM_AFF1_SHIFT)
     87#define ARM_AFF2_SHIFT 16
     88#define ARM_AFF2_MASK  (0xFFULL << ARM_AFF2_SHIFT)
     89#define ARM_AFF3_SHIFT 32
     90#define ARM_AFF3_MASK  (0xFFULL << ARM_AFF3_SHIFT)
     91#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
     92
     93#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
     94#define ARM64_AFFINITY_MASK \
     95    (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
     96#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
     97
     98#endif