cpu.c (71356B)
1/* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21#include "qemu/osdep.h" 22#include "qemu/qemu-print.h" 23#include "qemu-common.h" 24#include "target/arm/idau.h" 25#include "qemu/module.h" 26#include "qapi/error.h" 27#include "qapi/visitor.h" 28#include "cpu.h" 29#ifdef CONFIG_TCG 30#include "hw/core/tcg-cpu-ops.h" 31#endif /* CONFIG_TCG */ 32#include "internals.h" 33#include "exec/exec-all.h" 34#include "hw/qdev-properties.h" 35#if !defined(CONFIG_USER_ONLY) 36#include "hw/loader.h" 37#include "hw/boards.h" 38#endif 39#include "sysemu/tcg.h" 40#include "sysemu/hw_accel.h" 41#include "kvm_arm.h" 42#include "hvf_arm.h" 43#include "disas/capstone.h" 44#include "fpu/softfloat.h" 45 46static void arm_cpu_set_pc(CPUState *cs, vaddr value) 47{ 48 ARMCPU *cpu = ARM_CPU(cs); 49 CPUARMState *env = &cpu->env; 50 51 if (is_a64(env)) { 52 env->pc = value; 53 env->thumb = 0; 54 } else { 55 env->regs[15] = value & ~1; 56 env->thumb = value & 1; 57 } 58} 59 60#ifdef CONFIG_TCG 61void arm_cpu_synchronize_from_tb(CPUState *cs, 62 const TranslationBlock *tb) 63{ 64 ARMCPU *cpu = ARM_CPU(cs); 65 CPUARMState *env = &cpu->env; 66 67 /* 68 * It's OK to look at env for the current mode here, because it's 69 * never possible for an AArch64 TB to chain to an AArch32 TB. 70 */ 71 if (is_a64(env)) { 72 env->pc = tb->pc; 73 } else { 74 env->regs[15] = tb->pc; 75 } 76} 77#endif /* CONFIG_TCG */ 78 79static bool arm_cpu_has_work(CPUState *cs) 80{ 81 ARMCPU *cpu = ARM_CPU(cs); 82 83 return (cpu->power_state != PSCI_OFF) 84 && cs->interrupt_request & 85 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 86 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 87 | CPU_INTERRUPT_EXITTB); 88} 89 90void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 91 void *opaque) 92{ 93 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 94 95 entry->hook = hook; 96 entry->opaque = opaque; 97 98 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 99} 100 101void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 102 void *opaque) 103{ 104 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 105 106 entry->hook = hook; 107 entry->opaque = opaque; 108 109 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 110} 111 112static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 113{ 114 /* Reset a single ARMCPRegInfo register */ 115 ARMCPRegInfo *ri = value; 116 ARMCPU *cpu = opaque; 117 118 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 119 return; 120 } 121 122 if (ri->resetfn) { 123 ri->resetfn(&cpu->env, ri); 124 return; 125 } 126 127 /* A zero offset is never possible as it would be regs[0] 128 * so we use it to indicate that reset is being handled elsewhere. 129 * This is basically only used for fields in non-core coprocessors 130 * (like the pxa2xx ones). 131 */ 132 if (!ri->fieldoffset) { 133 return; 134 } 135 136 if (cpreg_field_is_64bit(ri)) { 137 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 138 } else { 139 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 140 } 141} 142 143static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 144{ 145 /* Purely an assertion check: we've already done reset once, 146 * so now check that running the reset for the cpreg doesn't 147 * change its value. This traps bugs where two different cpregs 148 * both try to reset the same state field but to different values. 149 */ 150 ARMCPRegInfo *ri = value; 151 ARMCPU *cpu = opaque; 152 uint64_t oldvalue, newvalue; 153 154 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 155 return; 156 } 157 158 oldvalue = read_raw_cp_reg(&cpu->env, ri); 159 cp_reg_reset(key, value, opaque); 160 newvalue = read_raw_cp_reg(&cpu->env, ri); 161 assert(oldvalue == newvalue); 162} 163 164static void arm_cpu_reset(DeviceState *dev) 165{ 166 CPUState *s = CPU(dev); 167 ARMCPU *cpu = ARM_CPU(s); 168 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 169 CPUARMState *env = &cpu->env; 170 171 acc->parent_reset(dev); 172 173 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 174 175 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 176 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 177 178 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 179 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 180 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 181 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 182 183 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 184 185 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 186 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 187 } 188 189 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 190 /* 64 bit CPUs always start in 64 bit mode */ 191 env->aarch64 = 1; 192#if defined(CONFIG_USER_ONLY) 193 env->pstate = PSTATE_MODE_EL0t; 194 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 195 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 196 /* Enable all PAC keys. */ 197 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 198 SCTLR_EnDA | SCTLR_EnDB); 199 /* and to the FP/Neon instructions */ 200 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 201 /* and to the SVE instructions */ 202 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 203 /* with reasonable vector length */ 204 if (cpu_isar_feature(aa64_sve, cpu)) { 205 env->vfp.zcr_el[1] = 206 aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1); 207 } 208 /* 209 * Enable TBI0 but not TBI1. 210 * Note that this must match useronly_clean_ptr. 211 */ 212 env->cp15.tcr_el[1].raw_tcr = (1ULL << 37); 213 214 /* Enable MTE */ 215 if (cpu_isar_feature(aa64_mte, cpu)) { 216 /* Enable tag access, but leave TCF0 as No Effect (0). */ 217 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 218 /* 219 * Exclude all tags, so that tag 0 is always used. 220 * This corresponds to Linux current->thread.gcr_incl = 0. 221 * 222 * Set RRND, so that helper_irg() will generate a seed later. 223 * Here in cpu_reset(), the crypto subsystem has not yet been 224 * initialized. 225 */ 226 env->cp15.gcr_el1 = 0x1ffff; 227 } 228#else 229 /* Reset into the highest available EL */ 230 if (arm_feature(env, ARM_FEATURE_EL3)) { 231 env->pstate = PSTATE_MODE_EL3h; 232 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 233 env->pstate = PSTATE_MODE_EL2h; 234 } else { 235 env->pstate = PSTATE_MODE_EL1h; 236 } 237 env->pc = cpu->rvbar; 238#endif 239 } else { 240#if defined(CONFIG_USER_ONLY) 241 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 242 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 243#endif 244 } 245 246#if defined(CONFIG_USER_ONLY) 247 env->uncached_cpsr = ARM_CPU_MODE_USR; 248 /* For user mode we must enable access to coprocessors */ 249 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 250 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 251 env->cp15.c15_cpar = 3; 252 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 253 env->cp15.c15_cpar = 1; 254 } 255#else 256 257 /* 258 * If the highest available EL is EL2, AArch32 will start in Hyp 259 * mode; otherwise it starts in SVC. Note that if we start in 260 * AArch64 then these values in the uncached_cpsr will be ignored. 261 */ 262 if (arm_feature(env, ARM_FEATURE_EL2) && 263 !arm_feature(env, ARM_FEATURE_EL3)) { 264 env->uncached_cpsr = ARM_CPU_MODE_HYP; 265 } else { 266 env->uncached_cpsr = ARM_CPU_MODE_SVC; 267 } 268 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 269 270 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 271 * executing as AArch32 then check if highvecs are enabled and 272 * adjust the PC accordingly. 273 */ 274 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 275 env->regs[15] = 0xFFFF0000; 276 } 277 278 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 279#endif 280 281 if (arm_feature(env, ARM_FEATURE_M)) { 282#ifndef CONFIG_USER_ONLY 283 uint32_t initial_msp; /* Loaded from 0x0 */ 284 uint32_t initial_pc; /* Loaded from 0x4 */ 285 uint8_t *rom; 286 uint32_t vecbase; 287#endif 288 289 if (cpu_isar_feature(aa32_lob, cpu)) { 290 /* 291 * LTPSIZE is constant 4 if MVE not implemented, and resets 292 * to an UNKNOWN value if MVE is implemented. We choose to 293 * always reset to 4. 294 */ 295 env->v7m.ltpsize = 4; 296 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 297 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 298 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 299 } 300 301 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 302 env->v7m.secure = true; 303 } else { 304 /* This bit resets to 0 if security is supported, but 1 if 305 * it is not. The bit is not present in v7M, but we set it 306 * here so we can avoid having to make checks on it conditional 307 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 308 */ 309 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 310 /* 311 * Set NSACR to indicate "NS access permitted to everything"; 312 * this avoids having to have all the tests of it being 313 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 314 * v8.1M the guest-visible value of NSACR in a CPU without the 315 * Security Extension is 0xcff. 316 */ 317 env->v7m.nsacr = 0xcff; 318 } 319 320 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 321 * that it resets to 1, so QEMU always does that rather than making 322 * it dependent on CPU model. In v8M it is RES1. 323 */ 324 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 325 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 326 if (arm_feature(env, ARM_FEATURE_V8)) { 327 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 328 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 329 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 330 } 331 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 332 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 333 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 334 } 335 336 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 337 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 338 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 339 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 340 } 341 342#ifndef CONFIG_USER_ONLY 343 /* Unlike A/R profile, M profile defines the reset LR value */ 344 env->regs[14] = 0xffffffff; 345 346 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 347 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 348 349 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 350 vecbase = env->v7m.vecbase[env->v7m.secure]; 351 rom = rom_ptr_for_as(s->as, vecbase, 8); 352 if (rom) { 353 /* Address zero is covered by ROM which hasn't yet been 354 * copied into physical memory. 355 */ 356 initial_msp = ldl_p(rom); 357 initial_pc = ldl_p(rom + 4); 358 } else { 359 /* Address zero not covered by a ROM blob, or the ROM blob 360 * is in non-modifiable memory and this is a second reset after 361 * it got copied into memory. In the latter case, rom_ptr 362 * will return a NULL pointer and we should use ldl_phys instead. 363 */ 364 initial_msp = ldl_phys(s->as, vecbase); 365 initial_pc = ldl_phys(s->as, vecbase + 4); 366 } 367 368 env->regs[13] = initial_msp & 0xFFFFFFFC; 369 env->regs[15] = initial_pc & ~1; 370 env->thumb = initial_pc & 1; 371#else 372 /* 373 * For user mode we run non-secure and with access to the FPU. 374 * The FPU context is active (ie does not need further setup) 375 * and is owned by non-secure. 376 */ 377 env->v7m.secure = false; 378 env->v7m.nsacr = 0xcff; 379 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 380 env->v7m.fpccr[M_REG_S] &= 381 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 382 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 383#endif 384 } 385 386 /* M profile requires that reset clears the exclusive monitor; 387 * A profile does not, but clearing it makes more sense than having it 388 * set with an exclusive access on address zero. 389 */ 390 arm_clear_exclusive(env); 391 392 if (arm_feature(env, ARM_FEATURE_PMSA)) { 393 if (cpu->pmsav7_dregion > 0) { 394 if (arm_feature(env, ARM_FEATURE_V8)) { 395 memset(env->pmsav8.rbar[M_REG_NS], 0, 396 sizeof(*env->pmsav8.rbar[M_REG_NS]) 397 * cpu->pmsav7_dregion); 398 memset(env->pmsav8.rlar[M_REG_NS], 0, 399 sizeof(*env->pmsav8.rlar[M_REG_NS]) 400 * cpu->pmsav7_dregion); 401 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 402 memset(env->pmsav8.rbar[M_REG_S], 0, 403 sizeof(*env->pmsav8.rbar[M_REG_S]) 404 * cpu->pmsav7_dregion); 405 memset(env->pmsav8.rlar[M_REG_S], 0, 406 sizeof(*env->pmsav8.rlar[M_REG_S]) 407 * cpu->pmsav7_dregion); 408 } 409 } else if (arm_feature(env, ARM_FEATURE_V7)) { 410 memset(env->pmsav7.drbar, 0, 411 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 412 memset(env->pmsav7.drsr, 0, 413 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 414 memset(env->pmsav7.dracr, 0, 415 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 416 } 417 } 418 env->pmsav7.rnr[M_REG_NS] = 0; 419 env->pmsav7.rnr[M_REG_S] = 0; 420 env->pmsav8.mair0[M_REG_NS] = 0; 421 env->pmsav8.mair0[M_REG_S] = 0; 422 env->pmsav8.mair1[M_REG_NS] = 0; 423 env->pmsav8.mair1[M_REG_S] = 0; 424 } 425 426 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 427 if (cpu->sau_sregion > 0) { 428 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 429 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 430 } 431 env->sau.rnr = 0; 432 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 433 * the Cortex-M33 does. 434 */ 435 env->sau.ctrl = 0; 436 } 437 438 set_flush_to_zero(1, &env->vfp.standard_fp_status); 439 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 440 set_default_nan_mode(1, &env->vfp.standard_fp_status); 441 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 442 set_float_detect_tininess(float_tininess_before_rounding, 443 &env->vfp.fp_status); 444 set_float_detect_tininess(float_tininess_before_rounding, 445 &env->vfp.standard_fp_status); 446 set_float_detect_tininess(float_tininess_before_rounding, 447 &env->vfp.fp_status_f16); 448 set_float_detect_tininess(float_tininess_before_rounding, 449 &env->vfp.standard_fp_status_f16); 450#ifndef CONFIG_USER_ONLY 451 if (kvm_enabled()) { 452 kvm_arm_reset_vcpu(cpu); 453 } 454#endif 455 456 hw_breakpoint_update_all(cpu); 457 hw_watchpoint_update_all(cpu); 458 arm_rebuild_hflags(env); 459} 460 461#ifndef CONFIG_USER_ONLY 462 463static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 464 unsigned int target_el, 465 unsigned int cur_el, bool secure, 466 uint64_t hcr_el2) 467{ 468 CPUARMState *env = cs->env_ptr; 469 bool pstate_unmasked; 470 bool unmasked = false; 471 472 /* 473 * Don't take exceptions if they target a lower EL. 474 * This check should catch any exceptions that would not be taken 475 * but left pending. 476 */ 477 if (cur_el > target_el) { 478 return false; 479 } 480 481 switch (excp_idx) { 482 case EXCP_FIQ: 483 pstate_unmasked = !(env->daif & PSTATE_F); 484 break; 485 486 case EXCP_IRQ: 487 pstate_unmasked = !(env->daif & PSTATE_I); 488 break; 489 490 case EXCP_VFIQ: 491 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 492 /* VFIQs are only taken when hypervized. */ 493 return false; 494 } 495 return !(env->daif & PSTATE_F); 496 case EXCP_VIRQ: 497 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 498 /* VIRQs are only taken when hypervized. */ 499 return false; 500 } 501 return !(env->daif & PSTATE_I); 502 default: 503 g_assert_not_reached(); 504 } 505 506 /* 507 * Use the target EL, current execution state and SCR/HCR settings to 508 * determine whether the corresponding CPSR bit is used to mask the 509 * interrupt. 510 */ 511 if ((target_el > cur_el) && (target_el != 1)) { 512 /* Exceptions targeting a higher EL may not be maskable */ 513 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 514 /* 515 * 64-bit masking rules are simple: exceptions to EL3 516 * can't be masked, and exceptions to EL2 can only be 517 * masked from Secure state. The HCR and SCR settings 518 * don't affect the masking logic, only the interrupt routing. 519 */ 520 if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) { 521 unmasked = true; 522 } 523 } else { 524 /* 525 * The old 32-bit-only environment has a more complicated 526 * masking setup. HCR and SCR bits not only affect interrupt 527 * routing but also change the behaviour of masking. 528 */ 529 bool hcr, scr; 530 531 switch (excp_idx) { 532 case EXCP_FIQ: 533 /* 534 * If FIQs are routed to EL3 or EL2 then there are cases where 535 * we override the CPSR.F in determining if the exception is 536 * masked or not. If neither of these are set then we fall back 537 * to the CPSR.F setting otherwise we further assess the state 538 * below. 539 */ 540 hcr = hcr_el2 & HCR_FMO; 541 scr = (env->cp15.scr_el3 & SCR_FIQ); 542 543 /* 544 * When EL3 is 32-bit, the SCR.FW bit controls whether the 545 * CPSR.F bit masks FIQ interrupts when taken in non-secure 546 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 547 * when non-secure but only when FIQs are only routed to EL3. 548 */ 549 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 550 break; 551 case EXCP_IRQ: 552 /* 553 * When EL3 execution state is 32-bit, if HCR.IMO is set then 554 * we may override the CPSR.I masking when in non-secure state. 555 * The SCR.IRQ setting has already been taken into consideration 556 * when setting the target EL, so it does not have a further 557 * affect here. 558 */ 559 hcr = hcr_el2 & HCR_IMO; 560 scr = false; 561 break; 562 default: 563 g_assert_not_reached(); 564 } 565 566 if ((scr || hcr) && !secure) { 567 unmasked = true; 568 } 569 } 570 } 571 572 /* 573 * The PSTATE bits only mask the interrupt if we have not overriden the 574 * ability above. 575 */ 576 return unmasked || pstate_unmasked; 577} 578 579static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 580{ 581 CPUClass *cc = CPU_GET_CLASS(cs); 582 CPUARMState *env = cs->env_ptr; 583 uint32_t cur_el = arm_current_el(env); 584 bool secure = arm_is_secure(env); 585 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 586 uint32_t target_el; 587 uint32_t excp_idx; 588 589 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 590 591 if (interrupt_request & CPU_INTERRUPT_FIQ) { 592 excp_idx = EXCP_FIQ; 593 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 594 if (arm_excp_unmasked(cs, excp_idx, target_el, 595 cur_el, secure, hcr_el2)) { 596 goto found; 597 } 598 } 599 if (interrupt_request & CPU_INTERRUPT_HARD) { 600 excp_idx = EXCP_IRQ; 601 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 602 if (arm_excp_unmasked(cs, excp_idx, target_el, 603 cur_el, secure, hcr_el2)) { 604 goto found; 605 } 606 } 607 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 608 excp_idx = EXCP_VIRQ; 609 target_el = 1; 610 if (arm_excp_unmasked(cs, excp_idx, target_el, 611 cur_el, secure, hcr_el2)) { 612 goto found; 613 } 614 } 615 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 616 excp_idx = EXCP_VFIQ; 617 target_el = 1; 618 if (arm_excp_unmasked(cs, excp_idx, target_el, 619 cur_el, secure, hcr_el2)) { 620 goto found; 621 } 622 } 623 return false; 624 625 found: 626 cs->exception_index = excp_idx; 627 env->exception.target_el = target_el; 628 cc->tcg_ops->do_interrupt(cs); 629 return true; 630} 631#endif /* !CONFIG_USER_ONLY */ 632 633void arm_cpu_update_virq(ARMCPU *cpu) 634{ 635 /* 636 * Update the interrupt level for VIRQ, which is the logical OR of 637 * the HCR_EL2.VI bit and the input line level from the GIC. 638 */ 639 CPUARMState *env = &cpu->env; 640 CPUState *cs = CPU(cpu); 641 642 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 643 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 644 645 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 646 if (new_state) { 647 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 648 } else { 649 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 650 } 651 } 652} 653 654void arm_cpu_update_vfiq(ARMCPU *cpu) 655{ 656 /* 657 * Update the interrupt level for VFIQ, which is the logical OR of 658 * the HCR_EL2.VF bit and the input line level from the GIC. 659 */ 660 CPUARMState *env = &cpu->env; 661 CPUState *cs = CPU(cpu); 662 663 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 664 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 665 666 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 667 if (new_state) { 668 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 669 } else { 670 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 671 } 672 } 673} 674 675#ifndef CONFIG_USER_ONLY 676static void arm_cpu_set_irq(void *opaque, int irq, int level) 677{ 678 ARMCPU *cpu = opaque; 679 CPUARMState *env = &cpu->env; 680 CPUState *cs = CPU(cpu); 681 static const int mask[] = { 682 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 683 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 684 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 685 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 686 }; 687 688 if (level) { 689 env->irq_line_state |= mask[irq]; 690 } else { 691 env->irq_line_state &= ~mask[irq]; 692 } 693 694 switch (irq) { 695 case ARM_CPU_VIRQ: 696 assert(arm_feature(env, ARM_FEATURE_EL2)); 697 arm_cpu_update_virq(cpu); 698 break; 699 case ARM_CPU_VFIQ: 700 assert(arm_feature(env, ARM_FEATURE_EL2)); 701 arm_cpu_update_vfiq(cpu); 702 break; 703 case ARM_CPU_IRQ: 704 case ARM_CPU_FIQ: 705 if (level) { 706 cpu_interrupt(cs, mask[irq]); 707 } else { 708 cpu_reset_interrupt(cs, mask[irq]); 709 } 710 break; 711 default: 712 g_assert_not_reached(); 713 } 714} 715 716static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 717{ 718#ifdef CONFIG_KVM 719 ARMCPU *cpu = opaque; 720 CPUARMState *env = &cpu->env; 721 CPUState *cs = CPU(cpu); 722 uint32_t linestate_bit; 723 int irq_id; 724 725 switch (irq) { 726 case ARM_CPU_IRQ: 727 irq_id = KVM_ARM_IRQ_CPU_IRQ; 728 linestate_bit = CPU_INTERRUPT_HARD; 729 break; 730 case ARM_CPU_FIQ: 731 irq_id = KVM_ARM_IRQ_CPU_FIQ; 732 linestate_bit = CPU_INTERRUPT_FIQ; 733 break; 734 default: 735 g_assert_not_reached(); 736 } 737 738 if (level) { 739 env->irq_line_state |= linestate_bit; 740 } else { 741 env->irq_line_state &= ~linestate_bit; 742 } 743 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 744#endif 745} 746 747static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 748{ 749 ARMCPU *cpu = ARM_CPU(cs); 750 CPUARMState *env = &cpu->env; 751 752 cpu_synchronize_state(cs); 753 return arm_cpu_data_is_big_endian(env); 754} 755 756#endif 757 758static int 759print_insn_thumb1(bfd_vma pc, disassemble_info *info) 760{ 761 return print_insn_arm(pc | 1, info); 762} 763 764static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 765{ 766 ARMCPU *ac = ARM_CPU(cpu); 767 CPUARMState *env = &ac->env; 768 bool sctlr_b; 769 770 if (is_a64(env)) { 771 /* We might not be compiled with the A64 disassembler 772 * because it needs a C++ compiler. Leave print_insn 773 * unset in this case to use the caller default behaviour. 774 */ 775#if defined(CONFIG_ARM_A64_DIS) 776 info->print_insn = print_insn_arm_a64; 777#endif 778 info->cap_arch = CS_ARCH_ARM64; 779 info->cap_insn_unit = 4; 780 info->cap_insn_split = 4; 781 } else { 782 int cap_mode; 783 if (env->thumb) { 784 info->print_insn = print_insn_thumb1; 785 info->cap_insn_unit = 2; 786 info->cap_insn_split = 4; 787 cap_mode = CS_MODE_THUMB; 788 } else { 789 info->print_insn = print_insn_arm; 790 info->cap_insn_unit = 4; 791 info->cap_insn_split = 4; 792 cap_mode = CS_MODE_ARM; 793 } 794 if (arm_feature(env, ARM_FEATURE_V8)) { 795 cap_mode |= CS_MODE_V8; 796 } 797 if (arm_feature(env, ARM_FEATURE_M)) { 798 cap_mode |= CS_MODE_MCLASS; 799 } 800 info->cap_arch = CS_ARCH_ARM; 801 info->cap_mode = cap_mode; 802 } 803 804 sctlr_b = arm_sctlr_b(env); 805 if (bswap_code(sctlr_b)) { 806#ifdef TARGET_WORDS_BIGENDIAN 807 info->endian = BFD_ENDIAN_LITTLE; 808#else 809 info->endian = BFD_ENDIAN_BIG; 810#endif 811 } 812 info->flags &= ~INSN_ARM_BE32; 813#ifndef CONFIG_USER_ONLY 814 if (sctlr_b) { 815 info->flags |= INSN_ARM_BE32; 816 } 817#endif 818} 819 820#ifdef TARGET_AARCH64 821 822static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 823{ 824 ARMCPU *cpu = ARM_CPU(cs); 825 CPUARMState *env = &cpu->env; 826 uint32_t psr = pstate_read(env); 827 int i; 828 int el = arm_current_el(env); 829 const char *ns_status; 830 831 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 832 for (i = 0; i < 32; i++) { 833 if (i == 31) { 834 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 835 } else { 836 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 837 (i + 2) % 3 ? " " : "\n"); 838 } 839 } 840 841 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 842 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 843 } else { 844 ns_status = ""; 845 } 846 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 847 psr, 848 psr & PSTATE_N ? 'N' : '-', 849 psr & PSTATE_Z ? 'Z' : '-', 850 psr & PSTATE_C ? 'C' : '-', 851 psr & PSTATE_V ? 'V' : '-', 852 ns_status, 853 el, 854 psr & PSTATE_SP ? 'h' : 't'); 855 856 if (cpu_isar_feature(aa64_bti, cpu)) { 857 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 858 } 859 if (!(flags & CPU_DUMP_FPU)) { 860 qemu_fprintf(f, "\n"); 861 return; 862 } 863 if (fp_exception_el(env, el) != 0) { 864 qemu_fprintf(f, " FPU disabled\n"); 865 return; 866 } 867 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 868 vfp_get_fpcr(env), vfp_get_fpsr(env)); 869 870 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { 871 int j, zcr_len = sve_zcr_len_for_el(env, el); 872 873 for (i = 0; i <= FFR_PRED_NUM; i++) { 874 bool eol; 875 if (i == FFR_PRED_NUM) { 876 qemu_fprintf(f, "FFR="); 877 /* It's last, so end the line. */ 878 eol = true; 879 } else { 880 qemu_fprintf(f, "P%02d=", i); 881 switch (zcr_len) { 882 case 0: 883 eol = i % 8 == 7; 884 break; 885 case 1: 886 eol = i % 6 == 5; 887 break; 888 case 2: 889 case 3: 890 eol = i % 3 == 2; 891 break; 892 default: 893 /* More than one quadword per predicate. */ 894 eol = true; 895 break; 896 } 897 } 898 for (j = zcr_len / 4; j >= 0; j--) { 899 int digits; 900 if (j * 4 + 4 <= zcr_len + 1) { 901 digits = 16; 902 } else { 903 digits = (zcr_len % 4 + 1) * 4; 904 } 905 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 906 env->vfp.pregs[i].p[j], 907 j ? ":" : eol ? "\n" : " "); 908 } 909 } 910 911 for (i = 0; i < 32; i++) { 912 if (zcr_len == 0) { 913 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 914 i, env->vfp.zregs[i].d[1], 915 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 916 } else if (zcr_len == 1) { 917 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 918 ":%016" PRIx64 ":%016" PRIx64 "\n", 919 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 920 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 921 } else { 922 for (j = zcr_len; j >= 0; j--) { 923 bool odd = (zcr_len - j) % 2 != 0; 924 if (j == zcr_len) { 925 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 926 } else if (!odd) { 927 if (j > 0) { 928 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 929 } else { 930 qemu_fprintf(f, " [%x]=", j); 931 } 932 } 933 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 934 env->vfp.zregs[i].d[j * 2 + 1], 935 env->vfp.zregs[i].d[j * 2], 936 odd || j == 0 ? "\n" : ":"); 937 } 938 } 939 } 940 } else { 941 for (i = 0; i < 32; i++) { 942 uint64_t *q = aa64_vfp_qreg(env, i); 943 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 944 i, q[1], q[0], (i & 1 ? "\n" : " ")); 945 } 946 } 947} 948 949#else 950 951static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 952{ 953 g_assert_not_reached(); 954} 955 956#endif 957 958static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 959{ 960 ARMCPU *cpu = ARM_CPU(cs); 961 CPUARMState *env = &cpu->env; 962 int i; 963 964 if (is_a64(env)) { 965 aarch64_cpu_dump_state(cs, f, flags); 966 return; 967 } 968 969 for (i = 0; i < 16; i++) { 970 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 971 if ((i % 4) == 3) { 972 qemu_fprintf(f, "\n"); 973 } else { 974 qemu_fprintf(f, " "); 975 } 976 } 977 978 if (arm_feature(env, ARM_FEATURE_M)) { 979 uint32_t xpsr = xpsr_read(env); 980 const char *mode; 981 const char *ns_status = ""; 982 983 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 984 ns_status = env->v7m.secure ? "S " : "NS "; 985 } 986 987 if (xpsr & XPSR_EXCP) { 988 mode = "handler"; 989 } else { 990 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 991 mode = "unpriv-thread"; 992 } else { 993 mode = "priv-thread"; 994 } 995 } 996 997 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 998 xpsr, 999 xpsr & XPSR_N ? 'N' : '-', 1000 xpsr & XPSR_Z ? 'Z' : '-', 1001 xpsr & XPSR_C ? 'C' : '-', 1002 xpsr & XPSR_V ? 'V' : '-', 1003 xpsr & XPSR_T ? 'T' : 'A', 1004 ns_status, 1005 mode); 1006 } else { 1007 uint32_t psr = cpsr_read(env); 1008 const char *ns_status = ""; 1009 1010 if (arm_feature(env, ARM_FEATURE_EL3) && 1011 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1012 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1013 } 1014 1015 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1016 psr, 1017 psr & CPSR_N ? 'N' : '-', 1018 psr & CPSR_Z ? 'Z' : '-', 1019 psr & CPSR_C ? 'C' : '-', 1020 psr & CPSR_V ? 'V' : '-', 1021 psr & CPSR_T ? 'T' : 'A', 1022 ns_status, 1023 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1024 } 1025 1026 if (flags & CPU_DUMP_FPU) { 1027 int numvfpregs = 0; 1028 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1029 numvfpregs = 32; 1030 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1031 numvfpregs = 16; 1032 } 1033 for (i = 0; i < numvfpregs; i++) { 1034 uint64_t v = *aa32_vfp_dreg(env, i); 1035 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1036 i * 2, (uint32_t)v, 1037 i * 2 + 1, (uint32_t)(v >> 32), 1038 i, v); 1039 } 1040 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1041 if (cpu_isar_feature(aa32_mve, cpu)) { 1042 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1043 } 1044 } 1045} 1046 1047uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1048{ 1049 uint32_t Aff1 = idx / clustersz; 1050 uint32_t Aff0 = idx % clustersz; 1051 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1052} 1053 1054static void cpreg_hashtable_data_destroy(gpointer data) 1055{ 1056 /* 1057 * Destroy function for cpu->cp_regs hashtable data entries. 1058 * We must free the name string because it was g_strdup()ed in 1059 * add_cpreg_to_hashtable(). It's OK to cast away the 'const' 1060 * from r->name because we know we definitely allocated it. 1061 */ 1062 ARMCPRegInfo *r = data; 1063 1064 g_free((void *)r->name); 1065 g_free(r); 1066} 1067 1068static void arm_cpu_initfn(Object *obj) 1069{ 1070 ARMCPU *cpu = ARM_CPU(obj); 1071 1072 cpu_set_cpustate_pointers(cpu); 1073 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 1074 g_free, cpreg_hashtable_data_destroy); 1075 1076 QLIST_INIT(&cpu->pre_el_change_hooks); 1077 QLIST_INIT(&cpu->el_change_hooks); 1078 1079#ifdef CONFIG_USER_ONLY 1080# ifdef TARGET_AARCH64 1081 /* 1082 * The linux kernel defaults to 512-bit vectors, when sve is supported. 1083 * See documentation for /proc/sys/abi/sve_default_vector_length, and 1084 * our corresponding sve-default-vector-length cpu property. 1085 */ 1086 cpu->sve_default_vq = 4; 1087# endif 1088#else 1089 /* Our inbound IRQ and FIQ lines */ 1090 if (kvm_enabled()) { 1091 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1092 * the same interface as non-KVM CPUs. 1093 */ 1094 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1095 } else { 1096 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1097 } 1098 1099 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1100 ARRAY_SIZE(cpu->gt_timer_outputs)); 1101 1102 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1103 "gicv3-maintenance-interrupt", 1); 1104 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1105 "pmu-interrupt", 1); 1106#endif 1107 1108 /* DTB consumers generally don't in fact care what the 'compatible' 1109 * string is, so always provide some string and trust that a hypothetical 1110 * picky DTB consumer will also provide a helpful error message. 1111 */ 1112 cpu->dtb_compatible = "qemu,unknown"; 1113 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 1114 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1115 1116 if (tcg_enabled() || hvf_enabled()) { 1117 cpu->psci_version = 2; /* TCG and HVF implement PSCI 0.2 */ 1118 } 1119} 1120 1121static Property arm_cpu_gt_cntfrq_property = 1122 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1123 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1124 1125static Property arm_cpu_reset_cbar_property = 1126 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1127 1128static Property arm_cpu_reset_hivecs_property = 1129 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1130 1131static Property arm_cpu_rvbar_property = 1132 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 1133 1134#ifndef CONFIG_USER_ONLY 1135static Property arm_cpu_has_el2_property = 1136 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1137 1138static Property arm_cpu_has_el3_property = 1139 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1140#endif 1141 1142static Property arm_cpu_cfgend_property = 1143 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1144 1145static Property arm_cpu_has_vfp_property = 1146 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1147 1148static Property arm_cpu_has_neon_property = 1149 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1150 1151static Property arm_cpu_has_dsp_property = 1152 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1153 1154static Property arm_cpu_has_mpu_property = 1155 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1156 1157/* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1158 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1159 * the right value for that particular CPU type, and we don't want 1160 * to override that with an incorrect constant value. 1161 */ 1162static Property arm_cpu_pmsav7_dregion_property = 1163 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1164 pmsav7_dregion, 1165 qdev_prop_uint32, uint32_t); 1166 1167static bool arm_get_pmu(Object *obj, Error **errp) 1168{ 1169 ARMCPU *cpu = ARM_CPU(obj); 1170 1171 return cpu->has_pmu; 1172} 1173 1174static void arm_set_pmu(Object *obj, bool value, Error **errp) 1175{ 1176 ARMCPU *cpu = ARM_CPU(obj); 1177 1178 if (value) { 1179 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1180 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1181 return; 1182 } 1183 set_feature(&cpu->env, ARM_FEATURE_PMU); 1184 } else { 1185 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1186 } 1187 cpu->has_pmu = value; 1188} 1189 1190unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1191{ 1192 /* 1193 * The exact approach to calculating guest ticks is: 1194 * 1195 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1196 * NANOSECONDS_PER_SECOND); 1197 * 1198 * We don't do that. Rather we intentionally use integer division 1199 * truncation below and in the caller for the conversion of host monotonic 1200 * time to guest ticks to provide the exact inverse for the semantics of 1201 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1202 * it loses precision when representing frequencies where 1203 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1204 * provide an exact inverse leads to scheduling timers with negative 1205 * periods, which in turn leads to sticky behaviour in the guest. 1206 * 1207 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1208 * cannot become zero. 1209 */ 1210 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1211 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1212} 1213 1214void arm_cpu_post_init(Object *obj) 1215{ 1216 ARMCPU *cpu = ARM_CPU(obj); 1217 1218 /* M profile implies PMSA. We have to do this here rather than 1219 * in realize with the other feature-implication checks because 1220 * we look at the PMSA bit to see if we should add some properties. 1221 */ 1222 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1223 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1224 } 1225 1226 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1227 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1228 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1229 } 1230 1231 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1232 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1233 } 1234 1235 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1236 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); 1237 } 1238 1239#ifndef CONFIG_USER_ONLY 1240 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1241 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1242 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1243 */ 1244 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1245 1246 object_property_add_link(obj, "secure-memory", 1247 TYPE_MEMORY_REGION, 1248 (Object **)&cpu->secure_memory, 1249 qdev_prop_allow_set_link_before_realize, 1250 OBJ_PROP_LINK_STRONG); 1251 } 1252 1253 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1254 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1255 } 1256#endif 1257 1258 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1259 cpu->has_pmu = true; 1260 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1261 } 1262 1263 /* 1264 * Allow user to turn off VFP and Neon support, but only for TCG -- 1265 * KVM does not currently allow us to lie to the guest about its 1266 * ID/feature registers, so the guest always sees what the host has. 1267 */ 1268 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1269 ? cpu_isar_feature(aa64_fp_simd, cpu) 1270 : cpu_isar_feature(aa32_vfp, cpu)) { 1271 cpu->has_vfp = true; 1272 if (!kvm_enabled()) { 1273 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1274 } 1275 } 1276 1277 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1278 cpu->has_neon = true; 1279 if (!kvm_enabled()) { 1280 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1281 } 1282 } 1283 1284 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1285 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1286 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1287 } 1288 1289 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1290 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1291 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1292 qdev_property_add_static(DEVICE(obj), 1293 &arm_cpu_pmsav7_dregion_property); 1294 } 1295 } 1296 1297 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1298 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1299 qdev_prop_allow_set_link_before_realize, 1300 OBJ_PROP_LINK_STRONG); 1301 /* 1302 * M profile: initial value of the Secure VTOR. We can't just use 1303 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1304 * the property to be set after realize. 1305 */ 1306 object_property_add_uint32_ptr(obj, "init-svtor", 1307 &cpu->init_svtor, 1308 OBJ_PROP_FLAG_READWRITE); 1309 } 1310 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1311 /* 1312 * Initial value of the NS VTOR (for cores without the Security 1313 * extension, this is the only VTOR) 1314 */ 1315 object_property_add_uint32_ptr(obj, "init-nsvtor", 1316 &cpu->init_nsvtor, 1317 OBJ_PROP_FLAG_READWRITE); 1318 } 1319 1320 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1321 1322 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1323 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1324 } 1325 1326 if (kvm_enabled()) { 1327 kvm_arm_add_vcpu_properties(obj); 1328 } 1329 1330#ifndef CONFIG_USER_ONLY 1331 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1332 cpu_isar_feature(aa64_mte, cpu)) { 1333 object_property_add_link(obj, "tag-memory", 1334 TYPE_MEMORY_REGION, 1335 (Object **)&cpu->tag_memory, 1336 qdev_prop_allow_set_link_before_realize, 1337 OBJ_PROP_LINK_STRONG); 1338 1339 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1340 object_property_add_link(obj, "secure-tag-memory", 1341 TYPE_MEMORY_REGION, 1342 (Object **)&cpu->secure_tag_memory, 1343 qdev_prop_allow_set_link_before_realize, 1344 OBJ_PROP_LINK_STRONG); 1345 } 1346 } 1347#endif 1348} 1349 1350static void arm_cpu_finalizefn(Object *obj) 1351{ 1352 ARMCPU *cpu = ARM_CPU(obj); 1353 ARMELChangeHook *hook, *next; 1354 1355 g_hash_table_destroy(cpu->cp_regs); 1356 1357 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1358 QLIST_REMOVE(hook, node); 1359 g_free(hook); 1360 } 1361 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1362 QLIST_REMOVE(hook, node); 1363 g_free(hook); 1364 } 1365#ifndef CONFIG_USER_ONLY 1366 if (cpu->pmu_timer) { 1367 timer_free(cpu->pmu_timer); 1368 } 1369#endif 1370} 1371 1372void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1373{ 1374 Error *local_err = NULL; 1375 1376 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1377 arm_cpu_sve_finalize(cpu, &local_err); 1378 if (local_err != NULL) { 1379 error_propagate(errp, local_err); 1380 return; 1381 } 1382 1383 /* 1384 * KVM does not support modifications to this feature. 1385 * We have not registered the cpu properties when KVM 1386 * is in use, so the user will not be able to set them. 1387 */ 1388 if (!kvm_enabled()) { 1389 arm_cpu_pauth_finalize(cpu, &local_err); 1390 if (local_err != NULL) { 1391 error_propagate(errp, local_err); 1392 return; 1393 } 1394 } 1395 } 1396 1397 if (kvm_enabled()) { 1398 kvm_arm_steal_time_finalize(cpu, &local_err); 1399 if (local_err != NULL) { 1400 error_propagate(errp, local_err); 1401 return; 1402 } 1403 } 1404} 1405 1406static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1407{ 1408 CPUState *cs = CPU(dev); 1409 ARMCPU *cpu = ARM_CPU(dev); 1410 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1411 CPUARMState *env = &cpu->env; 1412 int pagebits; 1413 Error *local_err = NULL; 1414 bool no_aa32 = false; 1415 1416 /* If we needed to query the host kernel for the CPU features 1417 * then it's possible that might have failed in the initfn, but 1418 * this is the first point where we can report it. 1419 */ 1420 if (cpu->host_cpu_probe_failed) { 1421 if (!kvm_enabled() && !hvf_enabled()) { 1422 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1423 } else { 1424 error_setg(errp, "Failed to retrieve host CPU features"); 1425 } 1426 return; 1427 } 1428 1429#ifndef CONFIG_USER_ONLY 1430 /* The NVIC and M-profile CPU are two halves of a single piece of 1431 * hardware; trying to use one without the other is a command line 1432 * error and will result in segfaults if not caught here. 1433 */ 1434 if (arm_feature(env, ARM_FEATURE_M)) { 1435 if (!env->nvic) { 1436 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1437 return; 1438 } 1439 } else { 1440 if (env->nvic) { 1441 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1442 return; 1443 } 1444 } 1445 1446 if (kvm_enabled()) { 1447 /* 1448 * Catch all the cases which might cause us to create more than one 1449 * address space for the CPU (otherwise we will assert() later in 1450 * cpu_address_space_init()). 1451 */ 1452 if (arm_feature(env, ARM_FEATURE_M)) { 1453 error_setg(errp, 1454 "Cannot enable KVM when using an M-profile guest CPU"); 1455 return; 1456 } 1457 if (cpu->has_el3) { 1458 error_setg(errp, 1459 "Cannot enable KVM when guest CPU has EL3 enabled"); 1460 return; 1461 } 1462 if (cpu->tag_memory) { 1463 error_setg(errp, 1464 "Cannot enable KVM when guest CPUs has MTE enabled"); 1465 return; 1466 } 1467 } 1468 1469 { 1470 uint64_t scale; 1471 1472 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1473 if (!cpu->gt_cntfrq_hz) { 1474 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1475 cpu->gt_cntfrq_hz); 1476 return; 1477 } 1478 scale = gt_cntfrq_period_ns(cpu); 1479 } else { 1480 scale = GTIMER_SCALE; 1481 } 1482 1483 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1484 arm_gt_ptimer_cb, cpu); 1485 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1486 arm_gt_vtimer_cb, cpu); 1487 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1488 arm_gt_htimer_cb, cpu); 1489 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1490 arm_gt_stimer_cb, cpu); 1491 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1492 arm_gt_hvtimer_cb, cpu); 1493 } 1494#endif 1495 1496 cpu_exec_realizefn(cs, &local_err); 1497 if (local_err != NULL) { 1498 error_propagate(errp, local_err); 1499 return; 1500 } 1501 1502 arm_cpu_finalize_features(cpu, &local_err); 1503 if (local_err != NULL) { 1504 error_propagate(errp, local_err); 1505 return; 1506 } 1507 1508 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1509 cpu->has_vfp != cpu->has_neon) { 1510 /* 1511 * This is an architectural requirement for AArch64; AArch32 is 1512 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1513 */ 1514 error_setg(errp, 1515 "AArch64 CPUs must have both VFP and Neon or neither"); 1516 return; 1517 } 1518 1519 if (!cpu->has_vfp) { 1520 uint64_t t; 1521 uint32_t u; 1522 1523 t = cpu->isar.id_aa64isar1; 1524 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1525 cpu->isar.id_aa64isar1 = t; 1526 1527 t = cpu->isar.id_aa64pfr0; 1528 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1529 cpu->isar.id_aa64pfr0 = t; 1530 1531 u = cpu->isar.id_isar6; 1532 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1533 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1534 cpu->isar.id_isar6 = u; 1535 1536 u = cpu->isar.mvfr0; 1537 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1538 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1539 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1540 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1541 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1542 if (!arm_feature(env, ARM_FEATURE_M)) { 1543 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1544 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1545 } 1546 cpu->isar.mvfr0 = u; 1547 1548 u = cpu->isar.mvfr1; 1549 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1550 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1551 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1552 if (arm_feature(env, ARM_FEATURE_M)) { 1553 u = FIELD_DP32(u, MVFR1, FP16, 0); 1554 } 1555 cpu->isar.mvfr1 = u; 1556 1557 u = cpu->isar.mvfr2; 1558 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1559 cpu->isar.mvfr2 = u; 1560 } 1561 1562 if (!cpu->has_neon) { 1563 uint64_t t; 1564 uint32_t u; 1565 1566 unset_feature(env, ARM_FEATURE_NEON); 1567 1568 t = cpu->isar.id_aa64isar0; 1569 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1570 cpu->isar.id_aa64isar0 = t; 1571 1572 t = cpu->isar.id_aa64isar1; 1573 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1574 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 1575 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 1576 cpu->isar.id_aa64isar1 = t; 1577 1578 t = cpu->isar.id_aa64pfr0; 1579 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1580 cpu->isar.id_aa64pfr0 = t; 1581 1582 u = cpu->isar.id_isar5; 1583 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1584 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1585 cpu->isar.id_isar5 = u; 1586 1587 u = cpu->isar.id_isar6; 1588 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1589 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1590 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1591 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 1592 cpu->isar.id_isar6 = u; 1593 1594 if (!arm_feature(env, ARM_FEATURE_M)) { 1595 u = cpu->isar.mvfr1; 1596 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1597 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1598 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1599 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1600 cpu->isar.mvfr1 = u; 1601 1602 u = cpu->isar.mvfr2; 1603 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1604 cpu->isar.mvfr2 = u; 1605 } 1606 } 1607 1608 if (!cpu->has_neon && !cpu->has_vfp) { 1609 uint64_t t; 1610 uint32_t u; 1611 1612 t = cpu->isar.id_aa64isar0; 1613 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1614 cpu->isar.id_aa64isar0 = t; 1615 1616 t = cpu->isar.id_aa64isar1; 1617 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1618 cpu->isar.id_aa64isar1 = t; 1619 1620 u = cpu->isar.mvfr0; 1621 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1622 cpu->isar.mvfr0 = u; 1623 1624 /* Despite the name, this field covers both VFP and Neon */ 1625 u = cpu->isar.mvfr1; 1626 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1627 cpu->isar.mvfr1 = u; 1628 } 1629 1630 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1631 uint32_t u; 1632 1633 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1634 1635 u = cpu->isar.id_isar1; 1636 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1637 cpu->isar.id_isar1 = u; 1638 1639 u = cpu->isar.id_isar2; 1640 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1641 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1642 cpu->isar.id_isar2 = u; 1643 1644 u = cpu->isar.id_isar3; 1645 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1646 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1647 cpu->isar.id_isar3 = u; 1648 } 1649 1650 /* Some features automatically imply others: */ 1651 if (arm_feature(env, ARM_FEATURE_V8)) { 1652 if (arm_feature(env, ARM_FEATURE_M)) { 1653 set_feature(env, ARM_FEATURE_V7); 1654 } else { 1655 set_feature(env, ARM_FEATURE_V7VE); 1656 } 1657 } 1658 1659 /* 1660 * There exist AArch64 cpus without AArch32 support. When KVM 1661 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1662 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1663 * As a general principle, we also do not make ID register 1664 * consistency checks anywhere unless using TCG, because only 1665 * for TCG would a consistency-check failure be a QEMU bug. 1666 */ 1667 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1668 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1669 } 1670 1671 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1672 /* v7 Virtualization Extensions. In real hardware this implies 1673 * EL2 and also the presence of the Security Extensions. 1674 * For QEMU, for backwards-compatibility we implement some 1675 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1676 * include the various other features that V7VE implies. 1677 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1678 * Security Extensions is ARM_FEATURE_EL3. 1679 */ 1680 assert(!tcg_enabled() || no_aa32 || 1681 cpu_isar_feature(aa32_arm_div, cpu)); 1682 set_feature(env, ARM_FEATURE_LPAE); 1683 set_feature(env, ARM_FEATURE_V7); 1684 } 1685 if (arm_feature(env, ARM_FEATURE_V7)) { 1686 set_feature(env, ARM_FEATURE_VAPA); 1687 set_feature(env, ARM_FEATURE_THUMB2); 1688 set_feature(env, ARM_FEATURE_MPIDR); 1689 if (!arm_feature(env, ARM_FEATURE_M)) { 1690 set_feature(env, ARM_FEATURE_V6K); 1691 } else { 1692 set_feature(env, ARM_FEATURE_V6); 1693 } 1694 1695 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1696 * non-EL3 configs. This is needed by some legacy boards. 1697 */ 1698 set_feature(env, ARM_FEATURE_VBAR); 1699 } 1700 if (arm_feature(env, ARM_FEATURE_V6K)) { 1701 set_feature(env, ARM_FEATURE_V6); 1702 set_feature(env, ARM_FEATURE_MVFR); 1703 } 1704 if (arm_feature(env, ARM_FEATURE_V6)) { 1705 set_feature(env, ARM_FEATURE_V5); 1706 if (!arm_feature(env, ARM_FEATURE_M)) { 1707 assert(!tcg_enabled() || no_aa32 || 1708 cpu_isar_feature(aa32_jazelle, cpu)); 1709 set_feature(env, ARM_FEATURE_AUXCR); 1710 } 1711 } 1712 if (arm_feature(env, ARM_FEATURE_V5)) { 1713 set_feature(env, ARM_FEATURE_V4T); 1714 } 1715 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1716 set_feature(env, ARM_FEATURE_V7MP); 1717 } 1718 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1719 set_feature(env, ARM_FEATURE_CBAR); 1720 } 1721 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1722 !arm_feature(env, ARM_FEATURE_M)) { 1723 set_feature(env, ARM_FEATURE_THUMB_DSP); 1724 } 1725 1726 /* 1727 * We rely on no XScale CPU having VFP so we can use the same bits in the 1728 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1729 */ 1730 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1731 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1732 !arm_feature(env, ARM_FEATURE_XSCALE)); 1733 1734 if (arm_feature(env, ARM_FEATURE_V7) && 1735 !arm_feature(env, ARM_FEATURE_M) && 1736 !arm_feature(env, ARM_FEATURE_PMSA)) { 1737 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1738 * can use 4K pages. 1739 */ 1740 pagebits = 12; 1741 } else { 1742 /* For CPUs which might have tiny 1K pages, or which have an 1743 * MPU and might have small region sizes, stick with 1K pages. 1744 */ 1745 pagebits = 10; 1746 } 1747 if (!set_preferred_target_page_bits(pagebits)) { 1748 /* This can only ever happen for hotplugging a CPU, or if 1749 * the board code incorrectly creates a CPU which it has 1750 * promised via minimum_page_size that it will not. 1751 */ 1752 error_setg(errp, "This CPU requires a smaller page size than the " 1753 "system is using"); 1754 return; 1755 } 1756 1757 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1758 * We don't support setting cluster ID ([16..23]) (known as Aff2 1759 * in later ARM ARM versions), or any of the higher affinity level fields, 1760 * so these bits always RAZ. 1761 */ 1762 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1763 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1764 ARM_DEFAULT_CPUS_PER_CLUSTER); 1765 } 1766 1767 if (cpu->reset_hivecs) { 1768 cpu->reset_sctlr |= (1 << 13); 1769 } 1770 1771 if (cpu->cfgend) { 1772 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1773 cpu->reset_sctlr |= SCTLR_EE; 1774 } else { 1775 cpu->reset_sctlr |= SCTLR_B; 1776 } 1777 } 1778 1779 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 1780 /* If the has_el3 CPU property is disabled then we need to disable the 1781 * feature. 1782 */ 1783 unset_feature(env, ARM_FEATURE_EL3); 1784 1785 /* Disable the security extension feature bits in the processor feature 1786 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 1787 */ 1788 cpu->isar.id_pfr1 &= ~0xf0; 1789 cpu->isar.id_aa64pfr0 &= ~0xf000; 1790 } 1791 1792 if (!cpu->has_el2) { 1793 unset_feature(env, ARM_FEATURE_EL2); 1794 } 1795 1796 if (!cpu->has_pmu) { 1797 unset_feature(env, ARM_FEATURE_PMU); 1798 } 1799 if (arm_feature(env, ARM_FEATURE_PMU)) { 1800 pmu_init(cpu); 1801 1802 if (!kvm_enabled()) { 1803 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1804 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1805 } 1806 1807#ifndef CONFIG_USER_ONLY 1808 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1809 cpu); 1810#endif 1811 } else { 1812 cpu->isar.id_aa64dfr0 = 1813 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1814 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1815 cpu->pmceid0 = 0; 1816 cpu->pmceid1 = 0; 1817 } 1818 1819 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1820 /* Disable the hypervisor feature bits in the processor feature 1821 * registers if we don't have EL2. These are id_pfr1[15:12] and 1822 * id_aa64pfr0_el1[11:8]. 1823 */ 1824 cpu->isar.id_aa64pfr0 &= ~0xf00; 1825 cpu->isar.id_pfr1 &= ~0xf000; 1826 } 1827 1828#ifndef CONFIG_USER_ONLY 1829 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { 1830 /* 1831 * Disable the MTE feature bits if we do not have tag-memory 1832 * provided by the machine. 1833 */ 1834 cpu->isar.id_aa64pfr1 = 1835 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 1836 } 1837#endif 1838 1839 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1840 * to false or by setting pmsav7-dregion to 0. 1841 */ 1842 if (!cpu->has_mpu) { 1843 cpu->pmsav7_dregion = 0; 1844 } 1845 if (cpu->pmsav7_dregion == 0) { 1846 cpu->has_mpu = false; 1847 } 1848 1849 if (arm_feature(env, ARM_FEATURE_PMSA) && 1850 arm_feature(env, ARM_FEATURE_V7)) { 1851 uint32_t nr = cpu->pmsav7_dregion; 1852 1853 if (nr > 0xff) { 1854 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1855 return; 1856 } 1857 1858 if (nr) { 1859 if (arm_feature(env, ARM_FEATURE_V8)) { 1860 /* PMSAv8 */ 1861 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1862 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1863 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1864 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1865 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1866 } 1867 } else { 1868 env->pmsav7.drbar = g_new0(uint32_t, nr); 1869 env->pmsav7.drsr = g_new0(uint32_t, nr); 1870 env->pmsav7.dracr = g_new0(uint32_t, nr); 1871 } 1872 } 1873 } 1874 1875 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1876 uint32_t nr = cpu->sau_sregion; 1877 1878 if (nr > 0xff) { 1879 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1880 return; 1881 } 1882 1883 if (nr) { 1884 env->sau.rbar = g_new0(uint32_t, nr); 1885 env->sau.rlar = g_new0(uint32_t, nr); 1886 } 1887 } 1888 1889 if (arm_feature(env, ARM_FEATURE_EL3)) { 1890 set_feature(env, ARM_FEATURE_VBAR); 1891 } 1892 1893 register_cp_regs_for_features(cpu); 1894 arm_cpu_register_gdb_regs_for_features(cpu); 1895 1896 init_cpreg_list(cpu); 1897 1898#ifndef CONFIG_USER_ONLY 1899 MachineState *ms = MACHINE(qdev_get_machine()); 1900 unsigned int smp_cpus = ms->smp.cpus; 1901 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 1902 1903 /* 1904 * We must set cs->num_ases to the final value before 1905 * the first call to cpu_address_space_init. 1906 */ 1907 if (cpu->tag_memory != NULL) { 1908 cs->num_ases = 3 + has_secure; 1909 } else { 1910 cs->num_ases = 1 + has_secure; 1911 } 1912 1913 if (has_secure) { 1914 if (!cpu->secure_memory) { 1915 cpu->secure_memory = cs->memory; 1916 } 1917 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1918 cpu->secure_memory); 1919 } 1920 1921 if (cpu->tag_memory != NULL) { 1922 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 1923 cpu->tag_memory); 1924 if (has_secure) { 1925 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 1926 cpu->secure_tag_memory); 1927 } 1928 } 1929 1930 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1931 1932 /* No core_count specified, default to smp_cpus. */ 1933 if (cpu->core_count == -1) { 1934 cpu->core_count = smp_cpus; 1935 } 1936#endif 1937 1938 if (tcg_enabled()) { 1939 int dcz_blocklen = 4 << cpu->dcz_blocksize; 1940 1941 /* 1942 * We only support DCZ blocklen that fits on one page. 1943 * 1944 * Architectually this is always true. However TARGET_PAGE_SIZE 1945 * is variable and, for compatibility with -machine virt-2.7, 1946 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 1947 * But even then, while the largest architectural DCZ blocklen 1948 * is 2KiB, no cpu actually uses such a large blocklen. 1949 */ 1950 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 1951 1952 /* 1953 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 1954 * both nibbles of each byte storing tag data may be written at once. 1955 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 1956 */ 1957 if (cpu_isar_feature(aa64_mte, cpu)) { 1958 assert(dcz_blocklen >= 2 * TAG_GRANULE); 1959 } 1960 } 1961 1962 qemu_init_vcpu(cs); 1963 cpu_reset(cs); 1964 1965 acc->parent_realize(dev, errp); 1966} 1967 1968static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1969{ 1970 ObjectClass *oc; 1971 char *typename; 1972 char **cpuname; 1973 const char *cpunamestr; 1974 1975 cpuname = g_strsplit(cpu_model, ",", 1); 1976 cpunamestr = cpuname[0]; 1977#ifdef CONFIG_USER_ONLY 1978 /* For backwards compatibility usermode emulation allows "-cpu any", 1979 * which has the same semantics as "-cpu max". 1980 */ 1981 if (!strcmp(cpunamestr, "any")) { 1982 cpunamestr = "max"; 1983 } 1984#endif 1985 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1986 oc = object_class_by_name(typename); 1987 g_strfreev(cpuname); 1988 g_free(typename); 1989 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1990 object_class_is_abstract(oc)) { 1991 return NULL; 1992 } 1993 return oc; 1994} 1995 1996static Property arm_cpu_properties[] = { 1997 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1998 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 1999 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2000 mp_affinity, ARM64_AFFINITY_INVALID), 2001 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2002 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2003 DEFINE_PROP_END_OF_LIST() 2004}; 2005 2006static gchar *arm_gdb_arch_name(CPUState *cs) 2007{ 2008 ARMCPU *cpu = ARM_CPU(cs); 2009 CPUARMState *env = &cpu->env; 2010 2011 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2012 return g_strdup("iwmmxt"); 2013 } 2014 return g_strdup("arm"); 2015} 2016 2017#ifndef CONFIG_USER_ONLY 2018#include "hw/core/sysemu-cpu-ops.h" 2019 2020static const struct SysemuCPUOps arm_sysemu_ops = { 2021 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2022 .asidx_from_attrs = arm_asidx_from_attrs, 2023 .write_elf32_note = arm_cpu_write_elf32_note, 2024 .write_elf64_note = arm_cpu_write_elf64_note, 2025 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2026 .legacy_vmsd = &vmstate_arm_cpu, 2027}; 2028#endif 2029 2030#ifdef CONFIG_TCG 2031static const struct TCGCPUOps arm_tcg_ops = { 2032 .initialize = arm_translate_init, 2033 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2034 .tlb_fill = arm_cpu_tlb_fill, 2035 .debug_excp_handler = arm_debug_excp_handler, 2036 2037#if !defined(CONFIG_USER_ONLY) 2038 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2039 .do_interrupt = arm_cpu_do_interrupt, 2040 .do_transaction_failed = arm_cpu_do_transaction_failed, 2041 .do_unaligned_access = arm_cpu_do_unaligned_access, 2042 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2043 .debug_check_watchpoint = arm_debug_check_watchpoint, 2044 .debug_check_breakpoint = arm_debug_check_breakpoint, 2045#endif /* !CONFIG_USER_ONLY */ 2046}; 2047#endif /* CONFIG_TCG */ 2048 2049static void arm_cpu_class_init(ObjectClass *oc, void *data) 2050{ 2051 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2052 CPUClass *cc = CPU_CLASS(acc); 2053 DeviceClass *dc = DEVICE_CLASS(oc); 2054 2055 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2056 &acc->parent_realize); 2057 2058 device_class_set_props(dc, arm_cpu_properties); 2059 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); 2060 2061 cc->class_by_name = arm_cpu_class_by_name; 2062 cc->has_work = arm_cpu_has_work; 2063 cc->dump_state = arm_cpu_dump_state; 2064 cc->set_pc = arm_cpu_set_pc; 2065 cc->gdb_read_register = arm_cpu_gdb_read_register; 2066 cc->gdb_write_register = arm_cpu_gdb_write_register; 2067#ifndef CONFIG_USER_ONLY 2068 cc->sysemu_ops = &arm_sysemu_ops; 2069#endif 2070 cc->gdb_num_core_regs = 26; 2071 cc->gdb_core_xml_file = "arm-core.xml"; 2072 cc->gdb_arch_name = arm_gdb_arch_name; 2073 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2074 cc->gdb_stop_before_watchpoint = true; 2075 cc->disas_set_info = arm_disas_set_info; 2076 2077#ifdef CONFIG_TCG 2078 cc->tcg_ops = &arm_tcg_ops; 2079#endif /* CONFIG_TCG */ 2080} 2081 2082#if defined(CONFIG_KVM) || defined(CONFIG_HVF) 2083static void arm_host_initfn(Object *obj) 2084{ 2085 ARMCPU *cpu = ARM_CPU(obj); 2086 2087#ifdef CONFIG_KVM 2088 kvm_arm_set_cpu_features_from_host(cpu); 2089 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 2090 aarch64_add_sve_properties(obj); 2091 } 2092#else 2093 hvf_arm_set_cpu_features_from_host(cpu); 2094#endif 2095 arm_cpu_post_init(obj); 2096} 2097 2098static const TypeInfo host_arm_cpu_type_info = { 2099 .name = TYPE_ARM_HOST_CPU, 2100 .parent = TYPE_AARCH64_CPU, 2101 .instance_init = arm_host_initfn, 2102}; 2103 2104#endif 2105 2106static void arm_cpu_instance_init(Object *obj) 2107{ 2108 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2109 2110 acc->info->initfn(obj); 2111 arm_cpu_post_init(obj); 2112} 2113 2114static void cpu_register_class_init(ObjectClass *oc, void *data) 2115{ 2116 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2117 2118 acc->info = data; 2119} 2120 2121void arm_cpu_register(const ARMCPUInfo *info) 2122{ 2123 TypeInfo type_info = { 2124 .parent = TYPE_ARM_CPU, 2125 .instance_size = sizeof(ARMCPU), 2126 .instance_align = __alignof__(ARMCPU), 2127 .instance_init = arm_cpu_instance_init, 2128 .class_size = sizeof(ARMCPUClass), 2129 .class_init = info->class_init ?: cpu_register_class_init, 2130 .class_data = (void *)info, 2131 }; 2132 2133 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2134 type_register(&type_info); 2135 g_free((void *)type_info.name); 2136} 2137 2138static const TypeInfo arm_cpu_type_info = { 2139 .name = TYPE_ARM_CPU, 2140 .parent = TYPE_CPU, 2141 .instance_size = sizeof(ARMCPU), 2142 .instance_align = __alignof__(ARMCPU), 2143 .instance_init = arm_cpu_initfn, 2144 .instance_finalize = arm_cpu_finalizefn, 2145 .abstract = true, 2146 .class_size = sizeof(ARMCPUClass), 2147 .class_init = arm_cpu_class_init, 2148}; 2149 2150static void arm_cpu_register_types(void) 2151{ 2152 type_register_static(&arm_cpu_type_info); 2153 2154#if defined(CONFIG_KVM) || defined(CONFIG_HVF) 2155 type_register_static(&host_arm_cpu_type_info); 2156#endif 2157} 2158 2159type_init(arm_cpu_register_types)