t16.decode (9606B)
1# Thumb1 instructions 2# 3# Copyright (c) 2019 Linaro, Ltd 4# 5# This library is free software; you can redistribute it and/or 6# modify it under the terms of the GNU Lesser General Public 7# License as published by the Free Software Foundation; either 8# version 2.1 of the License, or (at your option) any later version. 9# 10# This library is distributed in the hope that it will be useful, 11# but WITHOUT ANY WARRANTY; without even the implied warranty of 12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13# Lesser General Public License for more details. 14# 15# You should have received a copy of the GNU Lesser General Public 16# License along with this library; if not, see <http://www.gnu.org/licenses/>. 17 18# 19# This file is processed by scripts/decodetree.py 20# 21 22&empty !extern 23&s_rrr_shi !extern s rd rn rm shim shty 24&s_rrr_shr !extern s rn rd rm rs shty 25&s_rri_rot !extern s rn rd imm rot 26&s_rrrr !extern s rd rn rm ra 27&rrr_rot !extern rd rn rm rot 28&rr !extern rd rm 29&ri !extern rd imm 30&r !extern rm 31&i !extern imm 32&ldst_rr !extern p w u rn rt rm shimm shtype 33&ldst_ri !extern p w u rn rt imm 34&ldst_block !extern rn i b u w list 35&setend !extern E 36&cps !extern mode imod M A I F 37&ci !extern cond imm 38 39# Set S if the instruction is outside of an IT block. 40%s !function=t16_setflags 41 42# Data-processing (two low registers) 43 44%reg_0 0:3 45 46@lll_noshr ...... .... rm:3 rd:3 \ 47 &s_rrr_shi %s rn=%reg_0 shim=0 shty=0 48@xll_noshr ...... .... rm:3 rn:3 \ 49 &s_rrr_shi s=1 rd=0 shim=0 shty=0 50@lxl_shr ...... .... rs:3 rd:3 \ 51 &s_rrr_shr %s rm=%reg_0 rn=0 52 53AND_rrri 010000 0000 ... ... @lll_noshr 54EOR_rrri 010000 0001 ... ... @lll_noshr 55MOV_rxrr 010000 0010 ... ... @lxl_shr shty=0 # LSL 56MOV_rxrr 010000 0011 ... ... @lxl_shr shty=1 # LSR 57MOV_rxrr 010000 0100 ... ... @lxl_shr shty=2 # ASR 58ADC_rrri 010000 0101 ... ... @lll_noshr 59SBC_rrri 010000 0110 ... ... @lll_noshr 60MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3 # ROR 61TST_xrri 010000 1000 ... ... @xll_noshr 62RSB_rri 010000 1001 rn:3 rd:3 &s_rri_rot %s imm=0 rot=0 63CMP_xrri 010000 1010 ... ... @xll_noshr 64CMN_xrri 010000 1011 ... ... @xll_noshr 65ORR_rrri 010000 1100 ... ... @lll_noshr 66MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=%reg_0 ra=0 67BIC_rrri 010000 1110 ... ... @lll_noshr 68MVN_rxri 010000 1111 ... ... @lll_noshr 69 70# Load/store (register offset) 71 72@ldst_rr ....... rm:3 rn:3 rt:3 \ 73 &ldst_rr p=1 w=0 u=1 shimm=0 shtype=0 74 75STR_rr 0101 000 ... ... ... @ldst_rr 76STRH_rr 0101 001 ... ... ... @ldst_rr 77STRB_rr 0101 010 ... ... ... @ldst_rr 78LDRSB_rr 0101 011 ... ... ... @ldst_rr 79LDR_rr 0101 100 ... ... ... @ldst_rr 80LDRH_rr 0101 101 ... ... ... @ldst_rr 81LDRB_rr 0101 110 ... ... ... @ldst_rr 82LDRSH_rr 0101 111 ... ... ... @ldst_rr 83 84# Load/store word/byte (immediate offset) 85 86%imm5_6x4 6:5 !function=times_4 87 88@ldst_ri_1 ..... imm:5 rn:3 rt:3 \ 89 &ldst_ri p=1 w=0 u=1 90@ldst_ri_4 ..... ..... rn:3 rt:3 \ 91 &ldst_ri p=1 w=0 u=1 imm=%imm5_6x4 92 93STR_ri 01100 ..... ... ... @ldst_ri_4 94LDR_ri 01101 ..... ... ... @ldst_ri_4 95STRB_ri 01110 ..... ... ... @ldst_ri_1 96LDRB_ri 01111 ..... ... ... @ldst_ri_1 97 98# Load/store halfword (immediate offset) 99 100%imm5_6x2 6:5 !function=times_2 101@ldst_ri_2 ..... ..... rn:3 rt:3 \ 102 &ldst_ri p=1 w=0 u=1 imm=%imm5_6x2 103 104STRH_ri 10000 ..... ... ... @ldst_ri_2 105LDRH_ri 10001 ..... ... ... @ldst_ri_2 106 107# Load/store (SP-relative) 108 109%imm8_0x4 0:8 !function=times_4 110@ldst_spec_i ..... rt:3 ........ \ 111 &ldst_ri p=1 w=0 u=1 imm=%imm8_0x4 112 113STR_ri 10010 ... ........ @ldst_spec_i rn=13 114LDR_ri 10011 ... ........ @ldst_spec_i rn=13 115 116# Load (PC-relative) 117 118LDR_ri 01001 ... ........ @ldst_spec_i rn=15 119 120# Add PC/SP (immediate) 121 122ADR 10100 rd:3 ........ imm=%imm8_0x4 123ADD_rri 10101 rd:3 ........ \ 124 &s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4 # SP 125 126# Load/store multiple 127 128@ldstm ..... rn:3 list:8 &ldst_block i=1 b=0 u=0 w=1 129 130STM 11000 ... ........ @ldstm 131LDM_t16 11001 ... ........ @ldstm 132 133# Shift (immediate) 134 135@shift_i ..... shim:5 rm:3 rd:3 &s_rrr_shi %s rn=%reg_0 136 137MOV_rxri 000 00 ..... ... ... @shift_i shty=0 # LSL 138MOV_rxri 000 01 ..... ... ... @shift_i shty=1 # LSR 139MOV_rxri 000 10 ..... ... ... @shift_i shty=2 # ASR 140 141# Add/subtract (three low registers) 142 143@addsub_3 ....... rm:3 rn:3 rd:3 \ 144 &s_rrr_shi %s shim=0 shty=0 145 146ADD_rrri 0001100 ... ... ... @addsub_3 147SUB_rrri 0001101 ... ... ... @addsub_3 148 149# Add/subtract (two low registers and immediate) 150 151@addsub_2i ....... imm:3 rn:3 rd:3 \ 152 &s_rri_rot %s rot=0 153 154ADD_rri 0001 110 ... ... ... @addsub_2i 155SUB_rri 0001 111 ... ... ... @addsub_2i 156 157# Add, subtract, compare, move (one low register and immediate) 158 159%reg_8 8:3 160@arith_1i ..... rd:3 imm:8 \ 161 &s_rri_rot rot=0 rn=%reg_8 162 163MOV_rxi 00100 ... ........ @arith_1i %s 164CMP_xri 00101 ... ........ @arith_1i s=1 165ADD_rri 00110 ... ........ @arith_1i %s 166SUB_rri 00111 ... ........ @arith_1i %s 167 168# Add, compare, move (two high registers) 169 170%reg_0_7 7:1 0:3 171@addsub_2h .... .... . rm:4 ... \ 172 &s_rrr_shi rd=%reg_0_7 rn=%reg_0_7 shim=0 shty=0 173 174ADD_rrri 0100 0100 . .... ... @addsub_2h s=0 175CMP_xrri 0100 0101 . .... ... @addsub_2h s=1 176MOV_rxri 0100 0110 . .... ... @addsub_2h s=0 177 178# Adjust SP (immediate) 179 180%imm7_0x4 0:7 !function=times_4 181@addsub_sp_i .... .... . ....... \ 182 &s_rri_rot s=0 rd=13 rn=13 rot=0 imm=%imm7_0x4 183 184ADD_rri 1011 0000 0 ....... @addsub_sp_i 185SUB_rri 1011 0000 1 ....... @addsub_sp_i 186 187# Branch and exchange 188 189@branchr .... .... . rm:4 ... &r 190 191BX 0100 0111 0 .... 000 @branchr 192BLX_r 0100 0111 1 .... 000 @branchr 193BXNS 0100 0111 0 .... 100 @branchr 194BLXNS 0100 0111 1 .... 100 @branchr 195 196# Extend 197 198@extend .... .... .. rm:3 rd:3 &rrr_rot rn=15 rot=0 199 200SXTAH 1011 0010 00 ... ... @extend 201SXTAB 1011 0010 01 ... ... @extend 202UXTAH 1011 0010 10 ... ... @extend 203UXTAB 1011 0010 11 ... ... @extend 204 205# Change processor state 206 207%imod 4:1 !function=plus_2 208 209SETEND 1011 0110 010 1 E:1 000 &setend 210{ 211 CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=0 M=0 %imod 212 CPS_v7m 1011 0110 011 im:1 00 I:1 F:1 213} 214 215# Reverse bytes 216 217@rdm .... .... .. rm:3 rd:3 &rr 218 219REV 1011 1010 00 ... ... @rdm 220REV16 1011 1010 01 ... ... @rdm 221REVSH 1011 1010 11 ... ... @rdm 222 223# Hints 224 225{ 226 { 227 YIELD 1011 1111 0001 0000 228 WFE 1011 1111 0010 0000 229 WFI 1011 1111 0011 0000 230 231 # TODO: Implement SEV, SEVL; may help SMP performance. 232 # SEV 1011 1111 0100 0000 233 # SEVL 1011 1111 0101 0000 234 235 # The canonical nop has the second nibble as 0000, but the whole of the 236 # rest of the space is a reserved hint, behaves as nop. 237 NOP 1011 1111 ---- 0000 238 } 239 IT 1011 1111 cond_mask:8 240} 241 242# Miscellaneous 16-bit instructions 243 244%imm6_9_3 9:1 3:5 !function=times_2 245 246HLT 1011 1010 10 imm:6 &i 247BKPT 1011 1110 imm:8 &i 248CBZ 1011 nz:1 0.1 ..... rn:3 imm=%imm6_9_3 249 250# Push and Pop 251 252%push_list 0:9 !function=t16_push_list 253%pop_list 0:9 !function=t16_pop_list 254 255STM 1011 010 ......... \ 256 &ldst_block i=0 b=1 u=0 w=1 rn=13 list=%push_list 257LDM_t16 1011 110 ......... \ 258 &ldst_block i=1 b=0 u=0 w=1 rn=13 list=%pop_list 259 260# Conditional branches, Supervisor call 261 262%imm8_0x2 0:s8 !function=times_2 263 264{ 265 UDF 1101 1110 ---- ---- 266 SVC 1101 1111 imm:8 &i 267 B_cond_thumb 1101 cond:4 ........ &ci imm=%imm8_0x2 268} 269 270# Unconditional Branch 271 272%imm11_0x2 0:s11 !function=times_2 273 274B 11100 ........... &i imm=%imm11_0x2 275 276# thumb_insn_is_16bit() ensures we won't be decoding these as 277# T16 instructions for a Thumb2 CPU, so these patterns must be 278# a Thumb1 split BL/BLX. 279BLX_suffix 11101 imm:11 &i 280BL_BLX_prefix 11110 imm:s11 &i 281BL_suffix 11111 imm:11 &i