translate-a32.h (5717B)
1/* 2 * AArch32 translation, common definitions. 3 * 4 * Copyright (c) 2021 Linaro, Ltd. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20#ifndef TARGET_ARM_TRANSLATE_A64_H 21#define TARGET_ARM_TRANSLATE_A64_H 22 23/* Prototypes for autogenerated disassembler functions */ 24bool disas_m_nocp(DisasContext *dc, uint32_t insn); 25bool disas_mve(DisasContext *dc, uint32_t insn); 26bool disas_vfp(DisasContext *s, uint32_t insn); 27bool disas_vfp_uncond(DisasContext *s, uint32_t insn); 28bool disas_neon_dp(DisasContext *s, uint32_t insn); 29bool disas_neon_ls(DisasContext *s, uint32_t insn); 30bool disas_neon_shared(DisasContext *s, uint32_t insn); 31 32void load_reg_var(DisasContext *s, TCGv_i32 var, int reg); 33void arm_gen_condlabel(DisasContext *s); 34bool vfp_access_check(DisasContext *s); 35bool vfp_access_check_m(DisasContext *s, bool skip_context_update); 36void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop); 37void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop); 38void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop); 39void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop); 40TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs); 41void gen_set_cpsr(TCGv_i32 var, uint32_t mask); 42void gen_set_condexec(DisasContext *s); 43void gen_set_pc_im(DisasContext *s, target_ulong val); 44void gen_lookup_tb(DisasContext *s); 45long vfp_reg_offset(bool dp, unsigned reg); 46long neon_full_reg_offset(unsigned reg); 47long neon_element_offset(int reg, int element, MemOp memop); 48void gen_rev16(TCGv_i32 dest, TCGv_i32 var); 49void clear_eci_state(DisasContext *s); 50bool mve_eci_check(DisasContext *s); 51void mve_update_eci(DisasContext *s); 52void mve_update_and_store_eci(DisasContext *s); 53bool mve_skip_vmov(DisasContext *s, int vn, int index, int size); 54 55static inline TCGv_i32 load_cpu_offset(int offset) 56{ 57 TCGv_i32 tmp = tcg_temp_new_i32(); 58 tcg_gen_ld_i32(tmp, cpu_env, offset); 59 return tmp; 60} 61 62#define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name)) 63 64static inline void store_cpu_offset(TCGv_i32 var, int offset) 65{ 66 tcg_gen_st_i32(var, cpu_env, offset); 67 tcg_temp_free_i32(var); 68} 69 70#define store_cpu_field(var, name) \ 71 store_cpu_offset(var, offsetof(CPUARMState, name)) 72 73/* Create a new temporary and set it to the value of a CPU register. */ 74static inline TCGv_i32 load_reg(DisasContext *s, int reg) 75{ 76 TCGv_i32 tmp = tcg_temp_new_i32(); 77 load_reg_var(s, tmp, reg); 78 return tmp; 79} 80 81void store_reg(DisasContext *s, int reg, TCGv_i32 var); 82 83void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, 84 TCGv_i32 a32, int index, MemOp opc); 85void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, 86 TCGv_i32 a32, int index, MemOp opc); 87void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, 88 TCGv_i32 a32, int index, MemOp opc); 89void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, 90 TCGv_i32 a32, int index, MemOp opc); 91void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, 92 int index, MemOp opc); 93void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, 94 int index, MemOp opc); 95void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, 96 int index, MemOp opc); 97void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, 98 int index, MemOp opc); 99 100#define DO_GEN_LD(SUFF, OPC) \ 101 static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ 102 TCGv_i32 a32, int index) \ 103 { \ 104 gen_aa32_ld_i32(s, val, a32, index, OPC); \ 105 } 106 107#define DO_GEN_ST(SUFF, OPC) \ 108 static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ 109 TCGv_i32 a32, int index) \ 110 { \ 111 gen_aa32_st_i32(s, val, a32, index, OPC); \ 112 } 113 114static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, 115 TCGv_i32 a32, int index) 116{ 117 gen_aa32_ld_i64(s, val, a32, index, MO_Q); 118} 119 120static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, 121 TCGv_i32 a32, int index) 122{ 123 gen_aa32_st_i64(s, val, a32, index, MO_Q); 124} 125 126DO_GEN_LD(8u, MO_UB) 127DO_GEN_LD(16u, MO_UW) 128DO_GEN_LD(32u, MO_UL) 129DO_GEN_ST(8, MO_UB) 130DO_GEN_ST(16, MO_UW) 131DO_GEN_ST(32, MO_UL) 132 133#undef DO_GEN_LD 134#undef DO_GEN_ST 135 136#if defined(CONFIG_USER_ONLY) 137#define IS_USER(s) 1 138#else 139#define IS_USER(s) (s->user) 140#endif 141 142/* Set NZCV flags from the high 4 bits of var. */ 143#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV) 144 145/* Swap low and high halfwords. */ 146static inline void gen_swap_half(TCGv_i32 dest, TCGv_i32 var) 147{ 148 tcg_gen_rotri_i32(dest, var, 16); 149} 150 151#endif