insn.decode (6995B)
1# 2# AVR instruction decode definitions. 3# 4# Copyright (c) 2019-2020 Michael Rolnik <mrolnik@gmail.com> 5# 6# This library is free software; you can redistribute it and/or 7# modify it under the terms of the GNU Lesser General Public 8# License as published by the Free Software Foundation; either 9# version 2.1 of the License, or (at your option) any later version. 10# 11# This library is distributed in the hope that it will be useful, 12# but WITHOUT ANY WARRANTY; without even the implied warranty of 13# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14# Lesser General Public License for more details. 15# 16# You should have received a copy of the GNU Lesser General Public 17# License along with this library; if not, see <http://www.gnu.org/licenses/>. 18# 19 20# 21# regs_16_31_by_one = [16 .. 31] 22# regs_16_23_by_one = [16 .. 23] 23# regs_24_30_by_two = [24, 26, 28, 30] 24# regs_00_30_by_two = [0, 2, 4, 6, 8, .. 30] 25 26%rd 4:5 27%rr 9:1 0:4 28 29%rd_a 4:4 !function=to_regs_16_31_by_one 30%rd_b 4:3 !function=to_regs_16_23_by_one 31%rd_c 4:2 !function=to_regs_24_30_by_two 32%rr_a 0:4 !function=to_regs_16_31_by_one 33%rr_b 0:3 !function=to_regs_16_23_by_one 34 35%imm6 6:2 0:4 36%imm8 8:4 0:4 37 38%io_imm 9:2 0:4 39%ldst_d_imm 13:1 10:2 0:3 40 41 42&rd_rr rd rr 43&rd_imm rd imm 44 45@op_rd_rr .... .. . ..... .... &rd_rr rd=%rd rr=%rr 46@op_rd_imm6 .... .... .. .. .... &rd_imm rd=%rd_c imm=%imm6 47@op_rd_imm8 .... .... .... .... &rd_imm rd=%rd_a imm=%imm8 48@fmul .... .... . ... . ... &rd_rr rd=%rd_b rr=%rr_b 49 50# 51# Arithmetic Instructions 52# 53ADD 0000 11 . ..... .... @op_rd_rr 54ADC 0001 11 . ..... .... @op_rd_rr 55ADIW 1001 0110 .. .. .... @op_rd_imm6 56SUB 0001 10 . ..... .... @op_rd_rr 57SUBI 0101 .... .... .... @op_rd_imm8 58SBC 0000 10 . ..... .... @op_rd_rr 59SBCI 0100 .... .... .... @op_rd_imm8 60SBIW 1001 0111 .. .. .... @op_rd_imm6 61AND 0010 00 . ..... .... @op_rd_rr 62ANDI 0111 .... .... .... @op_rd_imm8 63OR 0010 10 . ..... .... @op_rd_rr 64ORI 0110 .... .... .... @op_rd_imm8 65EOR 0010 01 . ..... .... @op_rd_rr 66COM 1001 010 rd:5 0000 67NEG 1001 010 rd:5 0001 68INC 1001 010 rd:5 0011 69DEC 1001 010 rd:5 1010 70MUL 1001 11 . ..... .... @op_rd_rr 71MULS 0000 0010 .... .... &rd_rr rd=%rd_a rr=%rr_a 72MULSU 0000 0011 0 ... 0 ... @fmul 73FMUL 0000 0011 0 ... 1 ... @fmul 74FMULS 0000 0011 1 ... 0 ... @fmul 75FMULSU 0000 0011 1 ... 1 ... @fmul 76DES 1001 0100 imm:4 1011 77 78# 79# Branch Instructions 80# 81 82# The 22-bit immediate is partially in the opcode word, 83# and partially in the next. Use append_16 to build the 84# complete 22-bit value. 85%imm_call 4:5 0:1 !function=append_16 86 87@op_bit .... .... . bit:3 .... 88@op_bit_imm .... .. imm:s7 bit:3 89 90RJMP 1100 imm:s12 91IJMP 1001 0100 0000 1001 92EIJMP 1001 0100 0001 1001 93JMP 1001 010 ..... 110 . imm=%imm_call 94RCALL 1101 imm:s12 95ICALL 1001 0101 0000 1001 96EICALL 1001 0101 0001 1001 97CALL 1001 010 ..... 111 . imm=%imm_call 98RET 1001 0101 0000 1000 99RETI 1001 0101 0001 1000 100CPSE 0001 00 . ..... .... @op_rd_rr 101CP 0001 01 . ..... .... @op_rd_rr 102CPC 0000 01 . ..... .... @op_rd_rr 103CPI 0011 .... .... .... @op_rd_imm8 104SBRC 1111 110 rr:5 0 bit:3 105SBRS 1111 111 rr:5 0 bit:3 106SBIC 1001 1001 reg:5 bit:3 107SBIS 1001 1011 reg:5 bit:3 108BRBS 1111 00 ....... ... @op_bit_imm 109BRBC 1111 01 ....... ... @op_bit_imm 110 111# 112# Data Transfer Instructions 113# 114 115%rd_d 4:4 !function=to_regs_00_30_by_two 116%rr_d 0:4 !function=to_regs_00_30_by_two 117 118@io_rd_imm .... . .. ..... .... &rd_imm rd=%rd imm=%io_imm 119@ldst_d .. . . .. . rd:5 . ... &rd_imm imm=%ldst_d_imm 120 121# The 16-bit immediate is completely in the next word. 122# Fields cannot be defined with no bits, so we cannot play 123# the same trick and append to a zero-bit value. 124# Defer reading the immediate until trans_{LDS,STS}. 125@ldst_s .... ... rd:5 .... imm=0 126 127MOV 0010 11 . ..... .... @op_rd_rr 128MOVW 0000 0001 .... .... &rd_rr rd=%rd_d rr=%rr_d 129LDI 1110 .... .... .... @op_rd_imm8 130LDS 1001 000 ..... 0000 @ldst_s 131LDX1 1001 000 rd:5 1100 132LDX2 1001 000 rd:5 1101 133LDX3 1001 000 rd:5 1110 134LDY2 1001 000 rd:5 1001 135LDY3 1001 000 rd:5 1010 136LDZ2 1001 000 rd:5 0001 137LDZ3 1001 000 rd:5 0010 138LDDY 10 . 0 .. 0 ..... 1 ... @ldst_d 139LDDZ 10 . 0 .. 0 ..... 0 ... @ldst_d 140STS 1001 001 ..... 0000 @ldst_s 141STX1 1001 001 rr:5 1100 142STX2 1001 001 rr:5 1101 143STX3 1001 001 rr:5 1110 144STY2 1001 001 rd:5 1001 145STY3 1001 001 rd:5 1010 146STZ2 1001 001 rd:5 0001 147STZ3 1001 001 rd:5 0010 148STDY 10 . 0 .. 1 ..... 1 ... @ldst_d 149STDZ 10 . 0 .. 1 ..... 0 ... @ldst_d 150LPM1 1001 0101 1100 1000 151LPM2 1001 000 rd:5 0100 152LPMX 1001 000 rd:5 0101 153ELPM1 1001 0101 1101 1000 154ELPM2 1001 000 rd:5 0110 155ELPMX 1001 000 rd:5 0111 156SPM 1001 0101 1110 1000 157SPMX 1001 0101 1111 1000 158IN 1011 0 .. ..... .... @io_rd_imm 159OUT 1011 1 .. ..... .... @io_rd_imm 160PUSH 1001 001 rd:5 1111 161POP 1001 000 rd:5 1111 162XCH 1001 001 rd:5 0100 163LAC 1001 001 rd:5 0110 164LAS 1001 001 rd:5 0101 165LAT 1001 001 rd:5 0111 166 167# 168# Bit and Bit-test Instructions 169# 170LSR 1001 010 rd:5 0110 171ROR 1001 010 rd:5 0111 172ASR 1001 010 rd:5 0101 173SWAP 1001 010 rd:5 0010 174SBI 1001 1010 reg:5 bit:3 175CBI 1001 1000 reg:5 bit:3 176BST 1111 101 rd:5 0 bit:3 177BLD 1111 100 rd:5 0 bit:3 178BSET 1001 0100 0 bit:3 1000 179BCLR 1001 0100 1 bit:3 1000 180 181# 182# MCU Control Instructions 183# 184BREAK 1001 0101 1001 1000 185NOP 0000 0000 0000 0000 186SLEEP 1001 0101 1000 1000 187WDR 1001 0101 1010 1000