cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

gen_semantics.c (2883B)

      1/*
      2 *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
      3 *
      4 *  This program is free software; you can redistribute it and/or modify
      5 *  it under the terms of the GNU General Public License as published by
      6 *  the Free Software Foundation; either version 2 of the License, or
      7 *  (at your option) any later version.
      8 *
      9 *  This program is distributed in the hope that it will be useful,
     10 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
     11 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     12 *  GNU General Public License for more details.
     13 *
     14 *  You should have received a copy of the GNU General Public License
     15 *  along with this program; if not, see <http://www.gnu.org/licenses/>.
     16 */
     17
     18/*
     19 * This program generates the semantics file that is processed by
     20 * the do_qemu.py script.  We use the C preporcessor to manipulate the
     21 * files imported from the Hexagon architecture library.
     22 */
     23
     24#include <stdio.h>
     25#define STRINGIZE(X) #X
     26
     27int main(int argc, char *argv[])
     28{
     29    FILE *outfile;
     30
     31    if (argc != 2) {
     32        fprintf(stderr, "Usage: gen_semantics ouptputfile\n");
     33        return 1;
     34    }
     35    outfile = fopen(argv[1], "w");
     36    if (outfile == NULL) {
     37        fprintf(stderr, "Cannot open %s for writing\n", argv[1]);
     38        return 1;
     39    }
     40
     41/*
     42 * Process the instruction definitions
     43 *     Scalar core instructions have the following form
     44 *         Q6INSN(A2_add,"Rd32=add(Rs32,Rt32)",ATTRIBS(),
     45 *         "Add 32-bit registers",
     46 *         { RdV=RsV+RtV;})
     47 */
     48#define Q6INSN(TAG, BEH, ATTRIBS, DESCR, SEM) \
     49    do { \
     50        fprintf(outfile, "SEMANTICS( \\\n" \
     51                         "    \"%s\", \\\n" \
     52                         "    %s, \\\n" \
     53                         "    \"\"\"%s\"\"\" \\\n" \
     54                         ")\n", \
     55                #TAG, STRINGIZE(BEH), STRINGIZE(SEM)); \
     56        fprintf(outfile, "ATTRIBUTES( \\\n" \
     57                         "    \"%s\", \\\n" \
     58                         "    \"%s\" \\\n" \
     59                         ")\n", \
     60                #TAG, STRINGIZE(ATTRIBS)); \
     61    } while (0);
     62#include "imported/allidefs.def"
     63#undef Q6INSN
     64
     65/*
     66 * Process the macro definitions
     67 *     Macros definitions have the following form
     68 *         DEF_MACRO(
     69 *             fLSBNEW0,
     70 *             predlog_read(thread,0),
     71 *             ()
     72 *         )
     73 * The important part here is the attributes.  Whenever an instruction
     74 * invokes a macro, we add the macro's attributes to the instruction.
     75 */
     76#define DEF_MACRO(MNAME, BEH, ATTRS) \
     77    fprintf(outfile, "MACROATTRIB( \\\n" \
     78                     "    \"%s\", \\\n" \
     79                     "    \"\"\"%s\"\"\", \\\n" \
     80                     "    \"%s\" \\\n" \
     81                     ")\n", \
     82            #MNAME, STRINGIZE(BEH), STRINGIZE(ATTRS));
     83#include "imported/macros.def"
     84#undef DEF_MACRO
     85
     86    fclose(outfile);
     87    return 0;
     88}