cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

insn.h (2314B)

      1/*
      2 *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
      3 *
      4 *  This program is free software; you can redistribute it and/or modify
      5 *  it under the terms of the GNU General Public License as published by
      6 *  the Free Software Foundation; either version 2 of the License, or
      7 *  (at your option) any later version.
      8 *
      9 *  This program is distributed in the hope that it will be useful,
     10 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
     11 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     12 *  GNU General Public License for more details.
     13 *
     14 *  You should have received a copy of the GNU General Public License
     15 *  along with this program; if not, see <http://www.gnu.org/licenses/>.
     16 */
     17
     18#ifndef HEXAGON_INSN_H
     19#define HEXAGON_INSN_H
     20
     21#include "cpu.h"
     22
     23#define INSTRUCTIONS_MAX 7    /* 2 pairs + loopend */
     24#define REG_OPERANDS_MAX 5
     25#define IMMEDS_MAX 2
     26
     27struct Instruction;
     28struct Packet;
     29struct DisasContext;
     30
     31typedef void (*SemanticInsn)(CPUHexagonState *env,
     32                             struct DisasContext *ctx,
     33                             struct Instruction *insn,
     34                             struct Packet *pkt);
     35
     36struct Instruction {
     37    SemanticInsn generate;            /* pointer to genptr routine */
     38    uint8_t regno[REG_OPERANDS_MAX];    /* reg operands including predicates */
     39    uint16_t opcode;
     40
     41    uint32_t iclass:6;
     42    uint32_t slot:3;
     43    uint32_t which_extended:1;    /* If has an extender, which immediate */
     44    uint32_t new_value_producer_slot:4;
     45
     46    bool part1;              /*
     47                              * cmp-jumps are split into two insns.
     48                              * set for the compare and clear for the jump
     49                              */
     50    bool extension_valid;   /* Has a constant extender attached */
     51    bool is_endloop;   /* This is an end of loop */
     52    int32_t immed[IMMEDS_MAX];    /* immediate field */
     53};
     54
     55typedef struct Instruction Insn;
     56
     57struct Packet {
     58    uint16_t num_insns;
     59    uint16_t encod_pkt_size_in_bytes;
     60
     61    /* Pre-decodes about COF */
     62    bool pkt_has_cof;          /* Has any change-of-flow */
     63    bool pkt_has_endloop;
     64
     65    bool pkt_has_dczeroa;
     66
     67    bool pkt_has_store_s0;
     68    bool pkt_has_store_s1;
     69
     70    Insn insn[INSTRUCTIONS_MAX];
     71};
     72
     73typedef struct Packet Packet;
     74
     75#endif