cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

translate.h (2801B)

      1/*
      2 *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
      3 *
      4 *  This program is free software; you can redistribute it and/or modify
      5 *  it under the terms of the GNU General Public License as published by
      6 *  the Free Software Foundation; either version 2 of the License, or
      7 *  (at your option) any later version.
      8 *
      9 *  This program is distributed in the hope that it will be useful,
     10 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
     11 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     12 *  GNU General Public License for more details.
     13 *
     14 *  You should have received a copy of the GNU General Public License
     15 *  along with this program; if not, see <http://www.gnu.org/licenses/>.
     16 */
     17
     18#ifndef HEXAGON_TRANSLATE_H
     19#define HEXAGON_TRANSLATE_H
     20
     21#include "qemu/bitmap.h"
     22#include "cpu.h"
     23#include "exec/translator.h"
     24#include "tcg/tcg-op.h"
     25#include "internal.h"
     26
     27typedef struct DisasContext {
     28    DisasContextBase base;
     29    uint32_t mem_idx;
     30    uint32_t num_packets;
     31    uint32_t num_insns;
     32    int reg_log[REG_WRITES_MAX];
     33    int reg_log_idx;
     34    DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS);
     35    int preg_log[PRED_WRITES_MAX];
     36    int preg_log_idx;
     37    DECLARE_BITMAP(pregs_written, NUM_PREGS);
     38    uint8_t store_width[STORES_MAX];
     39    bool s1_store_processed;
     40} DisasContext;
     41
     42static inline void ctx_log_reg_write(DisasContext *ctx, int rnum)
     43{
     44    if (test_bit(rnum, ctx->regs_written)) {
     45        HEX_DEBUG_LOG("WARNING: Multiple writes to r%d\n", rnum);
     46    }
     47    ctx->reg_log[ctx->reg_log_idx] = rnum;
     48    ctx->reg_log_idx++;
     49    set_bit(rnum, ctx->regs_written);
     50}
     51
     52static inline void ctx_log_reg_write_pair(DisasContext *ctx, int rnum)
     53{
     54    ctx_log_reg_write(ctx, rnum);
     55    ctx_log_reg_write(ctx, rnum + 1);
     56}
     57
     58static inline void ctx_log_pred_write(DisasContext *ctx, int pnum)
     59{
     60    ctx->preg_log[ctx->preg_log_idx] = pnum;
     61    ctx->preg_log_idx++;
     62    set_bit(pnum, ctx->pregs_written);
     63}
     64
     65static inline bool is_preloaded(DisasContext *ctx, int num)
     66{
     67    return test_bit(num, ctx->regs_written);
     68}
     69
     70extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
     71extern TCGv hex_pred[NUM_PREGS];
     72extern TCGv hex_next_PC;
     73extern TCGv hex_this_PC;
     74extern TCGv hex_slot_cancelled;
     75extern TCGv hex_branch_taken;
     76extern TCGv hex_new_value[TOTAL_PER_THREAD_REGS];
     77extern TCGv hex_reg_written[TOTAL_PER_THREAD_REGS];
     78extern TCGv hex_new_pred_value[NUM_PREGS];
     79extern TCGv hex_pred_written;
     80extern TCGv hex_store_addr[STORES_MAX];
     81extern TCGv hex_store_width[STORES_MAX];
     82extern TCGv hex_store_val32[STORES_MAX];
     83extern TCGv_i64 hex_store_val64[STORES_MAX];
     84extern TCGv hex_dczero_addr;
     85extern TCGv hex_llsc_addr;
     86extern TCGv hex_llsc_val;
     87extern TCGv_i64 hex_llsc_val_i64;
     88
     89void process_store(DisasContext *ctx, Packet *pkt, int slot_num);
     90#endif