cpu.h (12176B)
1/* 2 * PA-RISC emulation cpu definitions for qemu. 3 * 4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20#ifndef HPPA_CPU_H 21#define HPPA_CPU_H 22 23#include "cpu-qom.h" 24#include "exec/cpu-defs.h" 25 26/* PA-RISC 1.x processors have a strong memory model. */ 27/* ??? While we do not yet implement PA-RISC 2.0, those processors have 28 a weak memory model, but with TLB bits that force ordering on a per-page 29 basis. It's probably easier to fall back to a strong memory model. */ 30#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL 31 32#define MMU_KERNEL_IDX 0 33#define MMU_USER_IDX 3 34#define MMU_PHYS_IDX 4 35#define TARGET_INSN_START_EXTRA_WORDS 1 36 37/* Hardware exceptions, interupts, faults, and traps. */ 38#define EXCP_HPMC 1 /* high priority machine check */ 39#define EXCP_POWER_FAIL 2 40#define EXCP_RC 3 /* recovery counter */ 41#define EXCP_EXT_INTERRUPT 4 /* external interrupt */ 42#define EXCP_LPMC 5 /* low priority machine check */ 43#define EXCP_ITLB_MISS 6 /* itlb miss / instruction page fault */ 44#define EXCP_IMP 7 /* instruction memory protection trap */ 45#define EXCP_ILL 8 /* illegal instruction trap */ 46#define EXCP_BREAK 9 /* break instruction */ 47#define EXCP_PRIV_OPR 10 /* privileged operation trap */ 48#define EXCP_PRIV_REG 11 /* privileged register trap */ 49#define EXCP_OVERFLOW 12 /* signed overflow trap */ 50#define EXCP_COND 13 /* trap-on-condition */ 51#define EXCP_ASSIST 14 /* assist exception trap */ 52#define EXCP_DTLB_MISS 15 /* dtlb miss / data page fault */ 53#define EXCP_NA_ITLB_MISS 16 /* non-access itlb miss */ 54#define EXCP_NA_DTLB_MISS 17 /* non-access dtlb miss */ 55#define EXCP_DMP 18 /* data memory protection trap */ 56#define EXCP_DMB 19 /* data memory break trap */ 57#define EXCP_TLB_DIRTY 20 /* tlb dirty bit trap */ 58#define EXCP_PAGE_REF 21 /* page reference trap */ 59#define EXCP_ASSIST_EMU 22 /* assist emulation trap */ 60#define EXCP_HPT 23 /* high-privilege transfer trap */ 61#define EXCP_LPT 24 /* low-privilege transfer trap */ 62#define EXCP_TB 25 /* taken branch trap */ 63#define EXCP_DMAR 26 /* data memory access rights trap */ 64#define EXCP_DMPI 27 /* data memory protection id trap */ 65#define EXCP_UNALIGN 28 /* unaligned data reference trap */ 66#define EXCP_PER_INTERRUPT 29 /* performance monitor interrupt */ 67 68/* Exceptions for linux-user emulation. */ 69#define EXCP_SYSCALL 30 70#define EXCP_SYSCALL_LWS 31 71 72/* Taken from Linux kernel: arch/parisc/include/asm/psw.h */ 73#define PSW_I 0x00000001 74#define PSW_D 0x00000002 75#define PSW_P 0x00000004 76#define PSW_Q 0x00000008 77#define PSW_R 0x00000010 78#define PSW_F 0x00000020 79#define PSW_G 0x00000040 /* PA1.x only */ 80#define PSW_O 0x00000080 /* PA2.0 only */ 81#define PSW_CB 0x0000ff00 82#define PSW_M 0x00010000 83#define PSW_V 0x00020000 84#define PSW_C 0x00040000 85#define PSW_B 0x00080000 86#define PSW_X 0x00100000 87#define PSW_N 0x00200000 88#define PSW_L 0x00400000 89#define PSW_H 0x00800000 90#define PSW_T 0x01000000 91#define PSW_S 0x02000000 92#define PSW_E 0x04000000 93#ifdef TARGET_HPPA64 94#define PSW_W 0x08000000 /* PA2.0 only */ 95#else 96#define PSW_W 0 97#endif 98#define PSW_Z 0x40000000 /* PA1.x only */ 99#define PSW_Y 0x80000000 /* PA1.x only */ 100 101#define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \ 102 | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I) 103 104/* ssm/rsm instructions number PSW_W and PSW_E differently */ 105#define PSW_SM_I PSW_I /* Enable External Interrupts */ 106#define PSW_SM_D PSW_D 107#define PSW_SM_P PSW_P 108#define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */ 109#define PSW_SM_R PSW_R /* Enable Recover Counter Trap */ 110#ifdef TARGET_HPPA64 111#define PSW_SM_E 0x100 112#define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ 113#else 114#define PSW_SM_E 0 115#define PSW_SM_W 0 116#endif 117 118#define CR_RC 0 119#define CR_PID1 8 120#define CR_PID2 9 121#define CR_PID3 12 122#define CR_PID4 13 123#define CR_SCRCCR 10 124#define CR_SAR 11 125#define CR_IVA 14 126#define CR_EIEM 15 127#define CR_IT 16 128#define CR_IIASQ 17 129#define CR_IIAOQ 18 130#define CR_IIR 19 131#define CR_ISR 20 132#define CR_IOR 21 133#define CR_IPSW 22 134#define CR_EIRR 23 135 136typedef struct CPUHPPAState CPUHPPAState; 137 138#if TARGET_REGISTER_BITS == 32 139typedef uint32_t target_ureg; 140typedef int32_t target_sreg; 141#define TREG_FMT_lx "%08"PRIx32 142#define TREG_FMT_ld "%"PRId32 143#else 144typedef uint64_t target_ureg; 145typedef int64_t target_sreg; 146#define TREG_FMT_lx "%016"PRIx64 147#define TREG_FMT_ld "%"PRId64 148#endif 149 150typedef struct { 151 uint64_t va_b; 152 uint64_t va_e; 153 target_ureg pa; 154 unsigned u : 1; 155 unsigned t : 1; 156 unsigned d : 1; 157 unsigned b : 1; 158 unsigned page_size : 4; 159 unsigned ar_type : 3; 160 unsigned ar_pl1 : 2; 161 unsigned ar_pl2 : 2; 162 unsigned entry_valid : 1; 163 unsigned access_id : 16; 164} hppa_tlb_entry; 165 166struct CPUHPPAState { 167 target_ureg gr[32]; 168 uint64_t fr[32]; 169 uint64_t sr[8]; /* stored shifted into place for gva */ 170 171 target_ureg psw; /* All psw bits except the following: */ 172 target_ureg psw_n; /* boolean */ 173 target_sreg psw_v; /* in most significant bit */ 174 175 /* Splitting the carry-borrow field into the MSB and "the rest", allows 176 * for "the rest" to be deleted when it is unused, but the MSB is in use. 177 * In addition, it's easier to compute carry-in for bit B+1 than it is to 178 * compute carry-out for bit B (3 vs 4 insns for addition, assuming the 179 * host has the appropriate add-with-carry insn to compute the msb). 180 * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110. 181 */ 182 target_ureg psw_cb; /* in least significant bit of next nibble */ 183 target_ureg psw_cb_msb; /* boolean */ 184 185 target_ureg iaoq_f; /* front */ 186 target_ureg iaoq_b; /* back, aka next instruction */ 187 uint64_t iasq_f; 188 uint64_t iasq_b; 189 190 uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ 191 float_status fp_status; 192 193 target_ureg cr[32]; /* control registers */ 194 target_ureg cr_back[2]; /* back of cr17/cr18 */ 195 target_ureg shadow[7]; /* shadow registers */ 196 197 /* ??? The number of entries isn't specified by the architecture. */ 198#define HPPA_TLB_ENTRIES 256 199#define HPPA_BTLB_ENTRIES 0 200 201 /* ??? Implement a unified itlb/dtlb for the moment. */ 202 /* ??? We should use a more intelligent data structure. */ 203 hppa_tlb_entry tlb[HPPA_TLB_ENTRIES]; 204 uint32_t tlb_last; 205}; 206 207/** 208 * HPPACPU: 209 * @env: #CPUHPPAState 210 * 211 * An HPPA CPU. 212 */ 213struct HPPACPU { 214 /*< private >*/ 215 CPUState parent_obj; 216 /*< public >*/ 217 218 CPUNegativeOffsetState neg; 219 CPUHPPAState env; 220 QEMUTimer *alarm_timer; 221}; 222 223 224typedef CPUHPPAState CPUArchState; 225typedef HPPACPU ArchCPU; 226 227#include "exec/cpu-all.h" 228 229static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) 230{ 231#ifdef CONFIG_USER_ONLY 232 return MMU_USER_IDX; 233#else 234 if (env->psw & (ifetch ? PSW_C : PSW_D)) { 235 return env->iaoq_f & 3; 236 } 237 return MMU_PHYS_IDX; /* mmu disabled */ 238#endif 239} 240 241void hppa_translate_init(void); 242 243#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU 244 245static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc, 246 target_ureg off) 247{ 248#ifdef CONFIG_USER_ONLY 249 return off; 250#else 251 off &= (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull); 252 return spc | off; 253#endif 254} 255 256static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, 257 target_ureg off) 258{ 259 return hppa_form_gva_psw(env->psw, spc, off); 260} 261 262/* Since PSW_{I,CB} will never need to be in tb->flags, reuse them. 263 * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the 264 * same value. 265 */ 266#define TB_FLAG_SR_SAME PSW_I 267#define TB_FLAG_PRIV_SHIFT 8 268 269static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, 270 target_ulong *cs_base, 271 uint32_t *pflags) 272{ 273 uint32_t flags = env->psw_n * PSW_N; 274 275 /* TB lookup assumes that PC contains the complete virtual address. 276 If we leave space+offset separate, we'll get ITLB misses to an 277 incomplete virtual address. This also means that we must separate 278 out current cpu priviledge from the low bits of IAOQ_F. */ 279#ifdef CONFIG_USER_ONLY 280 *pc = env->iaoq_f & -4; 281 *cs_base = env->iaoq_b & -4; 282#else 283 /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ 284 flags |= env->psw & (PSW_W | PSW_C | PSW_D); 285 flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; 286 287 *pc = (env->psw & PSW_C 288 ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4) 289 : env->iaoq_f & -4); 290 *cs_base = env->iasq_f; 291 292 /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero 293 low 32-bits of CS_BASE. This will succeed for all direct branches, 294 which is the primary case we care about -- using goto_tb within a page. 295 Failure is indicated by a zero difference. */ 296 if (env->iasq_f == env->iasq_b) { 297 target_sreg diff = env->iaoq_b - env->iaoq_f; 298 if (TARGET_REGISTER_BITS == 32 || diff == (int32_t)diff) { 299 *cs_base |= (uint32_t)diff; 300 } 301 } 302 if ((env->sr[4] == env->sr[5]) 303 & (env->sr[4] == env->sr[6]) 304 & (env->sr[4] == env->sr[7])) { 305 flags |= TB_FLAG_SR_SAME; 306 } 307#endif 308 309 *pflags = flags; 310} 311 312target_ureg cpu_hppa_get_psw(CPUHPPAState *env); 313void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg); 314void cpu_hppa_loaded_fr0(CPUHPPAState *env); 315 316#ifdef CONFIG_USER_ONLY 317static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { } 318#else 319void cpu_hppa_change_prot_id(CPUHPPAState *env); 320#endif 321 322hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); 323int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 324int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 325void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); 326bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 327 MMUAccessType access_type, int mmu_idx, 328 bool probe, uintptr_t retaddr); 329#ifndef CONFIG_USER_ONLY 330void hppa_cpu_do_interrupt(CPUState *cpu); 331bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); 332int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, 333 int type, hwaddr *pphys, int *pprot); 334extern const MemoryRegionOps hppa_io_eir_ops; 335extern const VMStateDescription vmstate_hppa_cpu; 336void hppa_cpu_alarm_timer(void *); 337int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr); 338#endif 339void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); 340 341#endif /* HPPA_CPU_H */