cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

helper.c (4134B)

      1/*
      2 *  HPPA emulation cpu helpers for qemu.
      3 *
      4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
      5 *
      6 * This library is free software; you can redistribute it and/or
      7 * modify it under the terms of the GNU Lesser General Public
      8 * License as published by the Free Software Foundation; either
      9 * version 2.1 of the License, or (at your option) any later version.
     10 *
     11 * This library is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     14 * Lesser General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU Lesser General Public
     17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
     18 */
     19
     20#include "qemu/osdep.h"
     21
     22#include "cpu.h"
     23#include "fpu/softfloat.h"
     24#include "exec/exec-all.h"
     25#include "exec/helper-proto.h"
     26#include "qemu/qemu-print.h"
     27
     28target_ureg cpu_hppa_get_psw(CPUHPPAState *env)
     29{
     30    target_ureg psw;
     31
     32    /* Fold carry bits down to 8 consecutive bits.  */
     33    /* ??? Needs tweaking for hppa64.  */
     34    /* .......b...c...d...e...f...g...h */
     35    psw = (env->psw_cb >> 4) & 0x01111111;
     36    /* .......b..bc..cd..de..ef..fg..gh */
     37    psw |= psw >> 3;
     38    /* .............bcd............efgh */
     39    psw |= (psw >> 6) & 0x000f000f;
     40    /* .........................bcdefgh */
     41    psw |= (psw >> 12) & 0xf;
     42    psw |= env->psw_cb_msb << 7;
     43    psw = (psw & 0xff) << 8;
     44
     45    psw |= env->psw_n * PSW_N;
     46    psw |= (env->psw_v < 0) * PSW_V;
     47    psw |= env->psw;
     48
     49    return psw;
     50}
     51
     52void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw)
     53{
     54    target_ureg old_psw = env->psw;
     55    target_ureg cb = 0;
     56
     57    env->psw = psw & ~(PSW_N | PSW_V | PSW_CB);
     58    env->psw_n = (psw / PSW_N) & 1;
     59    env->psw_v = -((psw / PSW_V) & 1);
     60    env->psw_cb_msb = (psw >> 15) & 1;
     61
     62    cb |= ((psw >> 14) & 1) << 28;
     63    cb |= ((psw >> 13) & 1) << 24;
     64    cb |= ((psw >> 12) & 1) << 20;
     65    cb |= ((psw >> 11) & 1) << 16;
     66    cb |= ((psw >> 10) & 1) << 12;
     67    cb |= ((psw >>  9) & 1) <<  8;
     68    cb |= ((psw >>  8) & 1) <<  4;
     69    env->psw_cb = cb;
     70
     71    /* If PSW_P changes, it affects how we translate addresses.  */
     72    if ((psw ^ old_psw) & PSW_P) {
     73#ifndef CONFIG_USER_ONLY
     74        tlb_flush_by_mmuidx(env_cpu(env), 0xf);
     75#endif
     76    }
     77}
     78
     79void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags)
     80{
     81    HPPACPU *cpu = HPPA_CPU(cs);
     82    CPUHPPAState *env = &cpu->env;
     83    target_ureg psw = cpu_hppa_get_psw(env);
     84    target_ureg psw_cb;
     85    char psw_c[20];
     86    int i;
     87
     88    qemu_fprintf(f, "IA_F " TARGET_FMT_lx " IA_B " TARGET_FMT_lx "\n",
     89                 hppa_form_gva_psw(psw, env->iasq_f, env->iaoq_f),
     90                 hppa_form_gva_psw(psw, env->iasq_b, env->iaoq_b));
     91
     92    psw_c[0]  = (psw & PSW_W ? 'W' : '-');
     93    psw_c[1]  = (psw & PSW_E ? 'E' : '-');
     94    psw_c[2]  = (psw & PSW_S ? 'S' : '-');
     95    psw_c[3]  = (psw & PSW_T ? 'T' : '-');
     96    psw_c[4]  = (psw & PSW_H ? 'H' : '-');
     97    psw_c[5]  = (psw & PSW_L ? 'L' : '-');
     98    psw_c[6]  = (psw & PSW_N ? 'N' : '-');
     99    psw_c[7]  = (psw & PSW_X ? 'X' : '-');
    100    psw_c[8]  = (psw & PSW_B ? 'B' : '-');
    101    psw_c[9]  = (psw & PSW_C ? 'C' : '-');
    102    psw_c[10] = (psw & PSW_V ? 'V' : '-');
    103    psw_c[11] = (psw & PSW_M ? 'M' : '-');
    104    psw_c[12] = (psw & PSW_F ? 'F' : '-');
    105    psw_c[13] = (psw & PSW_R ? 'R' : '-');
    106    psw_c[14] = (psw & PSW_Q ? 'Q' : '-');
    107    psw_c[15] = (psw & PSW_P ? 'P' : '-');
    108    psw_c[16] = (psw & PSW_D ? 'D' : '-');
    109    psw_c[17] = (psw & PSW_I ? 'I' : '-');
    110    psw_c[18] = '\0';
    111    psw_cb = ((env->psw_cb >> 4) & 0x01111111) | (env->psw_cb_msb << 28);
    112
    113    qemu_fprintf(f, "PSW  " TREG_FMT_lx " CB   " TREG_FMT_lx " %s\n",
    114                 psw, psw_cb, psw_c);
    115
    116    for (i = 0; i < 32; i++) {
    117        qemu_fprintf(f, "GR%02d " TREG_FMT_lx "%c", i, env->gr[i],
    118                     (i & 3) == 3 ? '\n' : ' ');
    119    }
    120#ifndef CONFIG_USER_ONLY
    121    for (i = 0; i < 8; i++) {
    122        qemu_fprintf(f, "SR%02d %08x%c", i, (uint32_t)(env->sr[i] >> 32),
    123                     (i & 3) == 3 ? '\n' : ' ');
    124    }
    125#endif
    126     qemu_fprintf(f, "\n");
    127
    128    /* ??? FR */
    129}