cpu.c (284147B)
1/* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20#include "qemu/osdep.h" 21#include "qemu/units.h" 22#include "qemu/cutils.h" 23#include "qemu/qemu-print.h" 24#include "cpu.h" 25#include "tcg/helper-tcg.h" 26#include "sysemu/reset.h" 27#include "sysemu/hvf.h" 28#include "kvm/kvm_i386.h" 29#include "sev_i386.h" 30#include "qapi/qapi-visit-machine.h" 31#include "qapi/qmp/qerror.h" 32#include "qapi/qapi-commands-machine-target.h" 33#include "standard-headers/asm-x86/kvm_para.h" 34#include "hw/qdev-properties.h" 35#include "hw/i386/topology.h" 36#ifndef CONFIG_USER_ONLY 37#include "exec/address-spaces.h" 38#include "hw/boards.h" 39#include "hw/i386/sgx-epc.h" 40#endif 41 42#include "disas/capstone.h" 43#include "cpu-internal.h" 44 45/* Helpers for building CPUID[2] descriptors: */ 46 47struct CPUID2CacheDescriptorInfo { 48 enum CacheType type; 49 int level; 50 int size; 51 int line_size; 52 int associativity; 53}; 54 55/* 56 * Known CPUID 2 cache descriptors. 57 * From Intel SDM Volume 2A, CPUID instruction 58 */ 59struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 60 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 61 .associativity = 4, .line_size = 32, }, 62 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 63 .associativity = 4, .line_size = 32, }, 64 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 65 .associativity = 4, .line_size = 64, }, 66 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 67 .associativity = 2, .line_size = 32, }, 68 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 69 .associativity = 4, .line_size = 32, }, 70 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 71 .associativity = 4, .line_size = 64, }, 72 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 73 .associativity = 6, .line_size = 64, }, 74 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 75 .associativity = 2, .line_size = 64, }, 76 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 77 .associativity = 8, .line_size = 64, }, 78 /* lines per sector is not supported cpuid2_cache_descriptor(), 79 * so descriptors 0x22, 0x23 are not included 80 */ 81 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 82 .associativity = 16, .line_size = 64, }, 83 /* lines per sector is not supported cpuid2_cache_descriptor(), 84 * so descriptors 0x25, 0x20 are not included 85 */ 86 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 87 .associativity = 8, .line_size = 64, }, 88 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 89 .associativity = 8, .line_size = 64, }, 90 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 91 .associativity = 4, .line_size = 32, }, 92 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 93 .associativity = 4, .line_size = 32, }, 94 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 95 .associativity = 4, .line_size = 32, }, 96 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 97 .associativity = 4, .line_size = 32, }, 98 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 99 .associativity = 4, .line_size = 32, }, 100 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 101 .associativity = 4, .line_size = 64, }, 102 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 103 .associativity = 8, .line_size = 64, }, 104 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 105 .associativity = 12, .line_size = 64, }, 106 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 107 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 108 .associativity = 12, .line_size = 64, }, 109 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 110 .associativity = 16, .line_size = 64, }, 111 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 112 .associativity = 12, .line_size = 64, }, 113 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 114 .associativity = 16, .line_size = 64, }, 115 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 116 .associativity = 24, .line_size = 64, }, 117 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 118 .associativity = 8, .line_size = 64, }, 119 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 120 .associativity = 4, .line_size = 64, }, 121 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 122 .associativity = 4, .line_size = 64, }, 123 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 124 .associativity = 4, .line_size = 64, }, 125 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 126 .associativity = 4, .line_size = 64, }, 127 /* lines per sector is not supported cpuid2_cache_descriptor(), 128 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 129 */ 130 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 131 .associativity = 8, .line_size = 64, }, 132 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 133 .associativity = 2, .line_size = 64, }, 134 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 135 .associativity = 8, .line_size = 64, }, 136 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 137 .associativity = 8, .line_size = 32, }, 138 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 139 .associativity = 8, .line_size = 32, }, 140 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 141 .associativity = 8, .line_size = 32, }, 142 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 143 .associativity = 8, .line_size = 32, }, 144 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 145 .associativity = 4, .line_size = 64, }, 146 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 147 .associativity = 8, .line_size = 64, }, 148 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 149 .associativity = 4, .line_size = 64, }, 150 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 151 .associativity = 4, .line_size = 64, }, 152 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 153 .associativity = 4, .line_size = 64, }, 154 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 155 .associativity = 8, .line_size = 64, }, 156 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 157 .associativity = 8, .line_size = 64, }, 158 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 159 .associativity = 8, .line_size = 64, }, 160 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 161 .associativity = 12, .line_size = 64, }, 162 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 163 .associativity = 12, .line_size = 64, }, 164 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 165 .associativity = 12, .line_size = 64, }, 166 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 167 .associativity = 16, .line_size = 64, }, 168 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 169 .associativity = 16, .line_size = 64, }, 170 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 171 .associativity = 16, .line_size = 64, }, 172 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 173 .associativity = 24, .line_size = 64, }, 174 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 175 .associativity = 24, .line_size = 64, }, 176 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 177 .associativity = 24, .line_size = 64, }, 178}; 179 180/* 181 * "CPUID leaf 2 does not report cache descriptor information, 182 * use CPUID leaf 4 to query cache parameters" 183 */ 184#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 185 186/* 187 * Return a CPUID 2 cache descriptor for a given cache. 188 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 189 */ 190static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 191{ 192 int i; 193 194 assert(cache->size > 0); 195 assert(cache->level > 0); 196 assert(cache->line_size > 0); 197 assert(cache->associativity > 0); 198 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 199 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 200 if (d->level == cache->level && d->type == cache->type && 201 d->size == cache->size && d->line_size == cache->line_size && 202 d->associativity == cache->associativity) { 203 return i; 204 } 205 } 206 207 return CACHE_DESCRIPTOR_UNAVAILABLE; 208} 209 210/* CPUID Leaf 4 constants: */ 211 212/* EAX: */ 213#define CACHE_TYPE_D 1 214#define CACHE_TYPE_I 2 215#define CACHE_TYPE_UNIFIED 3 216 217#define CACHE_LEVEL(l) (l << 5) 218 219#define CACHE_SELF_INIT_LEVEL (1 << 8) 220 221/* EDX: */ 222#define CACHE_NO_INVD_SHARING (1 << 0) 223#define CACHE_INCLUSIVE (1 << 1) 224#define CACHE_COMPLEX_IDX (1 << 2) 225 226/* Encode CacheType for CPUID[4].EAX */ 227#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 228 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 229 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 230 0 /* Invalid value */) 231 232 233/* Encode cache info for CPUID[4] */ 234static void encode_cache_cpuid4(CPUCacheInfo *cache, 235 int num_apic_ids, int num_cores, 236 uint32_t *eax, uint32_t *ebx, 237 uint32_t *ecx, uint32_t *edx) 238{ 239 assert(cache->size == cache->line_size * cache->associativity * 240 cache->partitions * cache->sets); 241 242 assert(num_apic_ids > 0); 243 *eax = CACHE_TYPE(cache->type) | 244 CACHE_LEVEL(cache->level) | 245 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 246 ((num_cores - 1) << 26) | 247 ((num_apic_ids - 1) << 14); 248 249 assert(cache->line_size > 0); 250 assert(cache->partitions > 0); 251 assert(cache->associativity > 0); 252 /* We don't implement fully-associative caches */ 253 assert(cache->associativity < cache->sets); 254 *ebx = (cache->line_size - 1) | 255 ((cache->partitions - 1) << 12) | 256 ((cache->associativity - 1) << 22); 257 258 assert(cache->sets > 0); 259 *ecx = cache->sets - 1; 260 261 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 262 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 263 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 264} 265 266/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 267static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 268{ 269 assert(cache->size % 1024 == 0); 270 assert(cache->lines_per_tag > 0); 271 assert(cache->associativity > 0); 272 assert(cache->line_size > 0); 273 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 274 (cache->lines_per_tag << 8) | (cache->line_size); 275} 276 277#define ASSOC_FULL 0xFF 278 279/* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 280#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 281 a == 2 ? 0x2 : \ 282 a == 4 ? 0x4 : \ 283 a == 8 ? 0x6 : \ 284 a == 16 ? 0x8 : \ 285 a == 32 ? 0xA : \ 286 a == 48 ? 0xB : \ 287 a == 64 ? 0xC : \ 288 a == 96 ? 0xD : \ 289 a == 128 ? 0xE : \ 290 a == ASSOC_FULL ? 0xF : \ 291 0 /* invalid value */) 292 293/* 294 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 295 * @l3 can be NULL. 296 */ 297static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 298 CPUCacheInfo *l3, 299 uint32_t *ecx, uint32_t *edx) 300{ 301 assert(l2->size % 1024 == 0); 302 assert(l2->associativity > 0); 303 assert(l2->lines_per_tag > 0); 304 assert(l2->line_size > 0); 305 *ecx = ((l2->size / 1024) << 16) | 306 (AMD_ENC_ASSOC(l2->associativity) << 12) | 307 (l2->lines_per_tag << 8) | (l2->line_size); 308 309 if (l3) { 310 assert(l3->size % (512 * 1024) == 0); 311 assert(l3->associativity > 0); 312 assert(l3->lines_per_tag > 0); 313 assert(l3->line_size > 0); 314 *edx = ((l3->size / (512 * 1024)) << 18) | 315 (AMD_ENC_ASSOC(l3->associativity) << 12) | 316 (l3->lines_per_tag << 8) | (l3->line_size); 317 } else { 318 *edx = 0; 319 } 320} 321 322/* Encode cache info for CPUID[8000001D] */ 323static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 324 X86CPUTopoInfo *topo_info, 325 uint32_t *eax, uint32_t *ebx, 326 uint32_t *ecx, uint32_t *edx) 327{ 328 uint32_t l3_threads; 329 assert(cache->size == cache->line_size * cache->associativity * 330 cache->partitions * cache->sets); 331 332 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 333 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 334 335 /* L3 is shared among multiple cores */ 336 if (cache->level == 3) { 337 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core; 338 *eax |= (l3_threads - 1) << 14; 339 } else { 340 *eax |= ((topo_info->threads_per_core - 1) << 14); 341 } 342 343 assert(cache->line_size > 0); 344 assert(cache->partitions > 0); 345 assert(cache->associativity > 0); 346 /* We don't implement fully-associative caches */ 347 assert(cache->associativity < cache->sets); 348 *ebx = (cache->line_size - 1) | 349 ((cache->partitions - 1) << 12) | 350 ((cache->associativity - 1) << 22); 351 352 assert(cache->sets > 0); 353 *ecx = cache->sets - 1; 354 355 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 356 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 357 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 358} 359 360/* Encode cache info for CPUID[8000001E] */ 361static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 362 uint32_t *eax, uint32_t *ebx, 363 uint32_t *ecx, uint32_t *edx) 364{ 365 X86CPUTopoIDs topo_ids; 366 367 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 368 369 *eax = cpu->apic_id; 370 371 /* 372 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 373 * Read-only. Reset: 0000_XXXXh. 374 * See Core::X86::Cpuid::ExtApicId. 375 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 376 * Bits Description 377 * 31:16 Reserved. 378 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 379 * The number of threads per core is ThreadsPerCore+1. 380 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 381 * 382 * NOTE: CoreId is already part of apic_id. Just use it. We can 383 * use all the 8 bits to represent the core_id here. 384 */ 385 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 386 387 /* 388 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 389 * Read-only. Reset: 0000_0XXXh. 390 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 391 * Bits Description 392 * 31:11 Reserved. 393 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 394 * ValidValues: 395 * Value Description 396 * 000b 1 node per processor. 397 * 001b 2 nodes per processor. 398 * 010b Reserved. 399 * 011b 4 nodes per processor. 400 * 111b-100b Reserved. 401 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 402 * 403 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 404 * But users can create more nodes than the actual hardware can 405 * support. To genaralize we can use all the upper 8 bits for nodes. 406 * NodeId is combination of node and socket_id which is already decoded 407 * in apic_id. Just use it by shifting. 408 */ 409 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 410 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 411 412 *edx = 0; 413} 414 415/* 416 * Definitions of the hardcoded cache entries we expose: 417 * These are legacy cache values. If there is a need to change any 418 * of these values please use builtin_x86_defs 419 */ 420 421/* L1 data cache: */ 422static CPUCacheInfo legacy_l1d_cache = { 423 .type = DATA_CACHE, 424 .level = 1, 425 .size = 32 * KiB, 426 .self_init = 1, 427 .line_size = 64, 428 .associativity = 8, 429 .sets = 64, 430 .partitions = 1, 431 .no_invd_sharing = true, 432}; 433 434/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 435static CPUCacheInfo legacy_l1d_cache_amd = { 436 .type = DATA_CACHE, 437 .level = 1, 438 .size = 64 * KiB, 439 .self_init = 1, 440 .line_size = 64, 441 .associativity = 2, 442 .sets = 512, 443 .partitions = 1, 444 .lines_per_tag = 1, 445 .no_invd_sharing = true, 446}; 447 448/* L1 instruction cache: */ 449static CPUCacheInfo legacy_l1i_cache = { 450 .type = INSTRUCTION_CACHE, 451 .level = 1, 452 .size = 32 * KiB, 453 .self_init = 1, 454 .line_size = 64, 455 .associativity = 8, 456 .sets = 64, 457 .partitions = 1, 458 .no_invd_sharing = true, 459}; 460 461/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 462static CPUCacheInfo legacy_l1i_cache_amd = { 463 .type = INSTRUCTION_CACHE, 464 .level = 1, 465 .size = 64 * KiB, 466 .self_init = 1, 467 .line_size = 64, 468 .associativity = 2, 469 .sets = 512, 470 .partitions = 1, 471 .lines_per_tag = 1, 472 .no_invd_sharing = true, 473}; 474 475/* Level 2 unified cache: */ 476static CPUCacheInfo legacy_l2_cache = { 477 .type = UNIFIED_CACHE, 478 .level = 2, 479 .size = 4 * MiB, 480 .self_init = 1, 481 .line_size = 64, 482 .associativity = 16, 483 .sets = 4096, 484 .partitions = 1, 485 .no_invd_sharing = true, 486}; 487 488/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 489static CPUCacheInfo legacy_l2_cache_cpuid2 = { 490 .type = UNIFIED_CACHE, 491 .level = 2, 492 .size = 2 * MiB, 493 .line_size = 64, 494 .associativity = 8, 495}; 496 497 498/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 499static CPUCacheInfo legacy_l2_cache_amd = { 500 .type = UNIFIED_CACHE, 501 .level = 2, 502 .size = 512 * KiB, 503 .line_size = 64, 504 .lines_per_tag = 1, 505 .associativity = 16, 506 .sets = 512, 507 .partitions = 1, 508}; 509 510/* Level 3 unified cache: */ 511static CPUCacheInfo legacy_l3_cache = { 512 .type = UNIFIED_CACHE, 513 .level = 3, 514 .size = 16 * MiB, 515 .line_size = 64, 516 .associativity = 16, 517 .sets = 16384, 518 .partitions = 1, 519 .lines_per_tag = 1, 520 .self_init = true, 521 .inclusive = true, 522 .complex_indexing = true, 523}; 524 525/* TLB definitions: */ 526 527#define L1_DTLB_2M_ASSOC 1 528#define L1_DTLB_2M_ENTRIES 255 529#define L1_DTLB_4K_ASSOC 1 530#define L1_DTLB_4K_ENTRIES 255 531 532#define L1_ITLB_2M_ASSOC 1 533#define L1_ITLB_2M_ENTRIES 255 534#define L1_ITLB_4K_ASSOC 1 535#define L1_ITLB_4K_ENTRIES 255 536 537#define L2_DTLB_2M_ASSOC 0 /* disabled */ 538#define L2_DTLB_2M_ENTRIES 0 /* disabled */ 539#define L2_DTLB_4K_ASSOC 4 540#define L2_DTLB_4K_ENTRIES 512 541 542#define L2_ITLB_2M_ASSOC 0 /* disabled */ 543#define L2_ITLB_2M_ENTRIES 0 /* disabled */ 544#define L2_ITLB_4K_ASSOC 4 545#define L2_ITLB_4K_ENTRIES 512 546 547/* CPUID Leaf 0x14 constants: */ 548#define INTEL_PT_MAX_SUBLEAF 0x1 549/* 550 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 551 * MSR can be accessed; 552 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 553 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 554 * of Intel PT MSRs across warm reset; 555 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 556 */ 557#define INTEL_PT_MINIMAL_EBX 0xf 558/* 559 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 560 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 561 * accessed; 562 * bit[01]: ToPA tables can hold any number of output entries, up to the 563 * maximum allowed by the MaskOrTableOffset field of 564 * IA32_RTIT_OUTPUT_MASK_PTRS; 565 * bit[02]: Support Single-Range Output scheme; 566 */ 567#define INTEL_PT_MINIMAL_ECX 0x7 568/* generated packets which contain IP payloads have LIP values */ 569#define INTEL_PT_IP_LIP (1 << 31) 570#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 571#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 572#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 573#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 574#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 575 576void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 577 uint32_t vendor2, uint32_t vendor3) 578{ 579 int i; 580 for (i = 0; i < 4; i++) { 581 dst[i] = vendor1 >> (8 * i); 582 dst[i + 4] = vendor2 >> (8 * i); 583 dst[i + 8] = vendor3 >> (8 * i); 584 } 585 dst[CPUID_VENDOR_SZ] = '\0'; 586} 587 588#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 589#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 590 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 591#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 592 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 593 CPUID_PSE36 | CPUID_FXSR) 594#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 595#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 596 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 597 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 598 CPUID_PAE | CPUID_SEP | CPUID_APIC) 599 600#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 601 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 602 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 603 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 604 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 605 /* partly implemented: 606 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 607 /* missing: 608 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 609#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 610 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 611 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 612 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 613 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 614 CPUID_EXT_RDRAND) 615 /* missing: 616 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 617 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA, 618 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 619 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX, 620 CPUID_EXT_F16C */ 621 622#ifdef TARGET_X86_64 623#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM) 624#else 625#define TCG_EXT2_X86_64_FEATURES 0 626#endif 627 628#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 629 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 630 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 631 TCG_EXT2_X86_64_FEATURES) 632#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 633 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) 634#define TCG_EXT4_FEATURES 0 635#define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 636 CPUID_SVM_SVME_ADDR_CHK) 637#define TCG_KVM_FEATURES 0 638#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 639 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 640 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \ 641 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 642 CPUID_7_0_EBX_ERMS) 643 /* missing: 644 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2, 645 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, 646 CPUID_7_0_EBX_RDSEED */ 647#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \ 648 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 649 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS) 650#define TCG_7_0_EDX_FEATURES 0 651#define TCG_7_1_EAX_FEATURES 0 652#define TCG_APM_FEATURES 0 653#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 654#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 655 /* missing: 656 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 657#define TCG_14_0_ECX_FEATURES 0 658#define TCG_SGX_12_0_EAX_FEATURES 0 659#define TCG_SGX_12_0_EBX_FEATURES 0 660#define TCG_SGX_12_1_EAX_FEATURES 0 661 662FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 663 [FEAT_1_EDX] = { 664 .type = CPUID_FEATURE_WORD, 665 .feat_names = { 666 "fpu", "vme", "de", "pse", 667 "tsc", "msr", "pae", "mce", 668 "cx8", "apic", NULL, "sep", 669 "mtrr", "pge", "mca", "cmov", 670 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 671 NULL, "ds" /* Intel dts */, "acpi", "mmx", 672 "fxsr", "sse", "sse2", "ss", 673 "ht" /* Intel htt */, "tm", "ia64", "pbe", 674 }, 675 .cpuid = {.eax = 1, .reg = R_EDX, }, 676 .tcg_features = TCG_FEATURES, 677 }, 678 [FEAT_1_ECX] = { 679 .type = CPUID_FEATURE_WORD, 680 .feat_names = { 681 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 682 "ds-cpl", "vmx", "smx", "est", 683 "tm2", "ssse3", "cid", NULL, 684 "fma", "cx16", "xtpr", "pdcm", 685 NULL, "pcid", "dca", "sse4.1", 686 "sse4.2", "x2apic", "movbe", "popcnt", 687 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 688 "avx", "f16c", "rdrand", "hypervisor", 689 }, 690 .cpuid = { .eax = 1, .reg = R_ECX, }, 691 .tcg_features = TCG_EXT_FEATURES, 692 }, 693 /* Feature names that are already defined on feature_name[] but 694 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 695 * names on feat_names below. They are copied automatically 696 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 697 */ 698 [FEAT_8000_0001_EDX] = { 699 .type = CPUID_FEATURE_WORD, 700 .feat_names = { 701 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 702 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 703 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 704 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 705 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 706 "nx", NULL, "mmxext", NULL /* mmx */, 707 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 708 NULL, "lm", "3dnowext", "3dnow", 709 }, 710 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 711 .tcg_features = TCG_EXT2_FEATURES, 712 }, 713 [FEAT_8000_0001_ECX] = { 714 .type = CPUID_FEATURE_WORD, 715 .feat_names = { 716 "lahf-lm", "cmp-legacy", "svm", "extapic", 717 "cr8legacy", "abm", "sse4a", "misalignsse", 718 "3dnowprefetch", "osvw", "ibs", "xop", 719 "skinit", "wdt", NULL, "lwp", 720 "fma4", "tce", NULL, "nodeid-msr", 721 NULL, "tbm", "topoext", "perfctr-core", 722 "perfctr-nb", NULL, NULL, NULL, 723 NULL, NULL, NULL, NULL, 724 }, 725 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 726 .tcg_features = TCG_EXT3_FEATURES, 727 /* 728 * TOPOEXT is always allowed but can't be enabled blindly by 729 * "-cpu host", as it requires consistent cache topology info 730 * to be provided so it doesn't confuse guests. 731 */ 732 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 733 }, 734 [FEAT_C000_0001_EDX] = { 735 .type = CPUID_FEATURE_WORD, 736 .feat_names = { 737 NULL, NULL, "xstore", "xstore-en", 738 NULL, NULL, "xcrypt", "xcrypt-en", 739 "ace2", "ace2-en", "phe", "phe-en", 740 "pmm", "pmm-en", NULL, NULL, 741 NULL, NULL, NULL, NULL, 742 NULL, NULL, NULL, NULL, 743 NULL, NULL, NULL, NULL, 744 NULL, NULL, NULL, NULL, 745 }, 746 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 747 .tcg_features = TCG_EXT4_FEATURES, 748 }, 749 [FEAT_KVM] = { 750 .type = CPUID_FEATURE_WORD, 751 .feat_names = { 752 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 753 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 754 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi", 755 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 756 NULL, NULL, NULL, NULL, 757 NULL, NULL, NULL, NULL, 758 "kvmclock-stable-bit", NULL, NULL, NULL, 759 NULL, NULL, NULL, NULL, 760 }, 761 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 762 .tcg_features = TCG_KVM_FEATURES, 763 }, 764 [FEAT_KVM_HINTS] = { 765 .type = CPUID_FEATURE_WORD, 766 .feat_names = { 767 "kvm-hint-dedicated", NULL, NULL, NULL, 768 NULL, NULL, NULL, NULL, 769 NULL, NULL, NULL, NULL, 770 NULL, NULL, NULL, NULL, 771 NULL, NULL, NULL, NULL, 772 NULL, NULL, NULL, NULL, 773 NULL, NULL, NULL, NULL, 774 NULL, NULL, NULL, NULL, 775 }, 776 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 777 .tcg_features = TCG_KVM_FEATURES, 778 /* 779 * KVM hints aren't auto-enabled by -cpu host, they need to be 780 * explicitly enabled in the command-line. 781 */ 782 .no_autoenable_flags = ~0U, 783 }, 784 [FEAT_SVM] = { 785 .type = CPUID_FEATURE_WORD, 786 .feat_names = { 787 "npt", "lbrv", "svm-lock", "nrip-save", 788 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 789 NULL, NULL, "pause-filter", NULL, 790 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 791 "vgif", NULL, NULL, NULL, 792 NULL, NULL, NULL, NULL, 793 NULL, NULL, NULL, NULL, 794 "svme-addr-chk", NULL, NULL, NULL, 795 }, 796 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 797 .tcg_features = TCG_SVM_FEATURES, 798 }, 799 [FEAT_7_0_EBX] = { 800 .type = CPUID_FEATURE_WORD, 801 .feat_names = { 802 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 803 "hle", "avx2", NULL, "smep", 804 "bmi2", "erms", "invpcid", "rtm", 805 NULL, NULL, "mpx", NULL, 806 "avx512f", "avx512dq", "rdseed", "adx", 807 "smap", "avx512ifma", "pcommit", "clflushopt", 808 "clwb", "intel-pt", "avx512pf", "avx512er", 809 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 810 }, 811 .cpuid = { 812 .eax = 7, 813 .needs_ecx = true, .ecx = 0, 814 .reg = R_EBX, 815 }, 816 .tcg_features = TCG_7_0_EBX_FEATURES, 817 }, 818 [FEAT_7_0_ECX] = { 819 .type = CPUID_FEATURE_WORD, 820 .feat_names = { 821 NULL, "avx512vbmi", "umip", "pku", 822 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 823 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 824 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 825 "la57", NULL, NULL, NULL, 826 NULL, NULL, "rdpid", NULL, 827 "bus-lock-detect", "cldemote", NULL, "movdiri", 828 "movdir64b", NULL, "sgxlc", "pks", 829 }, 830 .cpuid = { 831 .eax = 7, 832 .needs_ecx = true, .ecx = 0, 833 .reg = R_ECX, 834 }, 835 .tcg_features = TCG_7_0_ECX_FEATURES, 836 }, 837 [FEAT_7_0_EDX] = { 838 .type = CPUID_FEATURE_WORD, 839 .feat_names = { 840 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 841 "fsrm", NULL, NULL, NULL, 842 "avx512-vp2intersect", NULL, "md-clear", NULL, 843 NULL, NULL, "serialize", NULL, 844 "tsx-ldtrk", NULL, NULL /* pconfig */, NULL, 845 NULL, NULL, NULL, "avx512-fp16", 846 NULL, NULL, "spec-ctrl", "stibp", 847 NULL, "arch-capabilities", "core-capability", "ssbd", 848 }, 849 .cpuid = { 850 .eax = 7, 851 .needs_ecx = true, .ecx = 0, 852 .reg = R_EDX, 853 }, 854 .tcg_features = TCG_7_0_EDX_FEATURES, 855 }, 856 [FEAT_7_1_EAX] = { 857 .type = CPUID_FEATURE_WORD, 858 .feat_names = { 859 NULL, NULL, NULL, NULL, 860 "avx-vnni", "avx512-bf16", NULL, NULL, 861 NULL, NULL, NULL, NULL, 862 NULL, NULL, NULL, NULL, 863 NULL, NULL, NULL, NULL, 864 NULL, NULL, NULL, NULL, 865 NULL, NULL, NULL, NULL, 866 NULL, NULL, NULL, NULL, 867 }, 868 .cpuid = { 869 .eax = 7, 870 .needs_ecx = true, .ecx = 1, 871 .reg = R_EAX, 872 }, 873 .tcg_features = TCG_7_1_EAX_FEATURES, 874 }, 875 [FEAT_8000_0007_EDX] = { 876 .type = CPUID_FEATURE_WORD, 877 .feat_names = { 878 NULL, NULL, NULL, NULL, 879 NULL, NULL, NULL, NULL, 880 "invtsc", NULL, NULL, NULL, 881 NULL, NULL, NULL, NULL, 882 NULL, NULL, NULL, NULL, 883 NULL, NULL, NULL, NULL, 884 NULL, NULL, NULL, NULL, 885 NULL, NULL, NULL, NULL, 886 }, 887 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 888 .tcg_features = TCG_APM_FEATURES, 889 .unmigratable_flags = CPUID_APM_INVTSC, 890 }, 891 [FEAT_8000_0008_EBX] = { 892 .type = CPUID_FEATURE_WORD, 893 .feat_names = { 894 "clzero", NULL, "xsaveerptr", NULL, 895 NULL, NULL, NULL, NULL, 896 NULL, "wbnoinvd", NULL, NULL, 897 "ibpb", NULL, "ibrs", "amd-stibp", 898 NULL, NULL, NULL, NULL, 899 NULL, NULL, NULL, NULL, 900 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 901 NULL, NULL, NULL, NULL, 902 }, 903 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 904 .tcg_features = 0, 905 .unmigratable_flags = 0, 906 }, 907 [FEAT_XSAVE] = { 908 .type = CPUID_FEATURE_WORD, 909 .feat_names = { 910 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 911 NULL, NULL, NULL, NULL, 912 NULL, NULL, NULL, NULL, 913 NULL, NULL, NULL, NULL, 914 NULL, NULL, NULL, NULL, 915 NULL, NULL, NULL, NULL, 916 NULL, NULL, NULL, NULL, 917 NULL, NULL, NULL, NULL, 918 }, 919 .cpuid = { 920 .eax = 0xd, 921 .needs_ecx = true, .ecx = 1, 922 .reg = R_EAX, 923 }, 924 .tcg_features = TCG_XSAVE_FEATURES, 925 }, 926 [FEAT_6_EAX] = { 927 .type = CPUID_FEATURE_WORD, 928 .feat_names = { 929 NULL, NULL, "arat", NULL, 930 NULL, NULL, NULL, NULL, 931 NULL, NULL, NULL, NULL, 932 NULL, NULL, NULL, NULL, 933 NULL, NULL, NULL, NULL, 934 NULL, NULL, NULL, NULL, 935 NULL, NULL, NULL, NULL, 936 NULL, NULL, NULL, NULL, 937 }, 938 .cpuid = { .eax = 6, .reg = R_EAX, }, 939 .tcg_features = TCG_6_EAX_FEATURES, 940 }, 941 [FEAT_XSAVE_COMP_LO] = { 942 .type = CPUID_FEATURE_WORD, 943 .cpuid = { 944 .eax = 0xD, 945 .needs_ecx = true, .ecx = 0, 946 .reg = R_EAX, 947 }, 948 .tcg_features = ~0U, 949 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 950 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 951 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 952 XSTATE_PKRU_MASK, 953 }, 954 [FEAT_XSAVE_COMP_HI] = { 955 .type = CPUID_FEATURE_WORD, 956 .cpuid = { 957 .eax = 0xD, 958 .needs_ecx = true, .ecx = 0, 959 .reg = R_EDX, 960 }, 961 .tcg_features = ~0U, 962 }, 963 /*Below are MSR exposed features*/ 964 [FEAT_ARCH_CAPABILITIES] = { 965 .type = MSR_FEATURE_WORD, 966 .feat_names = { 967 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 968 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 969 "taa-no", NULL, NULL, NULL, 970 NULL, NULL, NULL, NULL, 971 NULL, NULL, NULL, NULL, 972 NULL, NULL, NULL, NULL, 973 NULL, NULL, NULL, NULL, 974 NULL, NULL, NULL, NULL, 975 }, 976 .msr = { 977 .index = MSR_IA32_ARCH_CAPABILITIES, 978 }, 979 }, 980 [FEAT_CORE_CAPABILITY] = { 981 .type = MSR_FEATURE_WORD, 982 .feat_names = { 983 NULL, NULL, NULL, NULL, 984 NULL, "split-lock-detect", NULL, NULL, 985 NULL, NULL, NULL, NULL, 986 NULL, NULL, NULL, NULL, 987 NULL, NULL, NULL, NULL, 988 NULL, NULL, NULL, NULL, 989 NULL, NULL, NULL, NULL, 990 NULL, NULL, NULL, NULL, 991 }, 992 .msr = { 993 .index = MSR_IA32_CORE_CAPABILITY, 994 }, 995 }, 996 [FEAT_PERF_CAPABILITIES] = { 997 .type = MSR_FEATURE_WORD, 998 .feat_names = { 999 NULL, NULL, NULL, NULL, 1000 NULL, NULL, NULL, NULL, 1001 NULL, NULL, NULL, NULL, 1002 NULL, "full-width-write", NULL, NULL, 1003 NULL, NULL, NULL, NULL, 1004 NULL, NULL, NULL, NULL, 1005 NULL, NULL, NULL, NULL, 1006 NULL, NULL, NULL, NULL, 1007 }, 1008 .msr = { 1009 .index = MSR_IA32_PERF_CAPABILITIES, 1010 }, 1011 }, 1012 1013 [FEAT_VMX_PROCBASED_CTLS] = { 1014 .type = MSR_FEATURE_WORD, 1015 .feat_names = { 1016 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1017 NULL, NULL, NULL, "vmx-hlt-exit", 1018 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1019 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1020 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1021 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1022 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1023 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1024 }, 1025 .msr = { 1026 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1027 } 1028 }, 1029 1030 [FEAT_VMX_SECONDARY_CTLS] = { 1031 .type = MSR_FEATURE_WORD, 1032 .feat_names = { 1033 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1034 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1035 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1036 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1037 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1038 "vmx-xsaves", NULL, NULL, NULL, 1039 NULL, "vmx-tsc-scaling", NULL, NULL, 1040 NULL, NULL, NULL, NULL, 1041 }, 1042 .msr = { 1043 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1044 } 1045 }, 1046 1047 [FEAT_VMX_PINBASED_CTLS] = { 1048 .type = MSR_FEATURE_WORD, 1049 .feat_names = { 1050 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1051 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1052 NULL, NULL, NULL, NULL, 1053 NULL, NULL, NULL, NULL, 1054 NULL, NULL, NULL, NULL, 1055 NULL, NULL, NULL, NULL, 1056 NULL, NULL, NULL, NULL, 1057 NULL, NULL, NULL, NULL, 1058 }, 1059 .msr = { 1060 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1061 } 1062 }, 1063 1064 [FEAT_VMX_EXIT_CTLS] = { 1065 .type = MSR_FEATURE_WORD, 1066 /* 1067 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1068 * the LM CPUID bit. 1069 */ 1070 .feat_names = { 1071 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1072 NULL, NULL, NULL, NULL, 1073 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1074 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1075 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1076 "vmx-exit-save-efer", "vmx-exit-load-efer", 1077 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1078 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1079 NULL, "vmx-exit-load-pkrs", NULL, NULL, 1080 }, 1081 .msr = { 1082 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1083 } 1084 }, 1085 1086 [FEAT_VMX_ENTRY_CTLS] = { 1087 .type = MSR_FEATURE_WORD, 1088 .feat_names = { 1089 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1090 NULL, NULL, NULL, NULL, 1091 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1092 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1093 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1094 NULL, NULL, "vmx-entry-load-pkrs", NULL, 1095 NULL, NULL, NULL, NULL, 1096 NULL, NULL, NULL, NULL, 1097 }, 1098 .msr = { 1099 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1100 } 1101 }, 1102 1103 [FEAT_VMX_MISC] = { 1104 .type = MSR_FEATURE_WORD, 1105 .feat_names = { 1106 NULL, NULL, NULL, NULL, 1107 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1108 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1109 NULL, NULL, NULL, NULL, 1110 NULL, NULL, NULL, NULL, 1111 NULL, NULL, NULL, NULL, 1112 NULL, NULL, NULL, NULL, 1113 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1114 }, 1115 .msr = { 1116 .index = MSR_IA32_VMX_MISC, 1117 } 1118 }, 1119 1120 [FEAT_VMX_EPT_VPID_CAPS] = { 1121 .type = MSR_FEATURE_WORD, 1122 .feat_names = { 1123 "vmx-ept-execonly", NULL, NULL, NULL, 1124 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1125 NULL, NULL, NULL, NULL, 1126 NULL, NULL, NULL, NULL, 1127 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1128 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1129 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1130 NULL, NULL, NULL, NULL, 1131 "vmx-invvpid", NULL, NULL, NULL, 1132 NULL, NULL, NULL, NULL, 1133 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1134 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1135 NULL, NULL, NULL, NULL, 1136 NULL, NULL, NULL, NULL, 1137 NULL, NULL, NULL, NULL, 1138 NULL, NULL, NULL, NULL, 1139 NULL, NULL, NULL, NULL, 1140 }, 1141 .msr = { 1142 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1143 } 1144 }, 1145 1146 [FEAT_VMX_BASIC] = { 1147 .type = MSR_FEATURE_WORD, 1148 .feat_names = { 1149 [54] = "vmx-ins-outs", 1150 [55] = "vmx-true-ctls", 1151 }, 1152 .msr = { 1153 .index = MSR_IA32_VMX_BASIC, 1154 }, 1155 /* Just to be safe - we don't support setting the MSEG version field. */ 1156 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1157 }, 1158 1159 [FEAT_VMX_VMFUNC] = { 1160 .type = MSR_FEATURE_WORD, 1161 .feat_names = { 1162 [0] = "vmx-eptp-switching", 1163 }, 1164 .msr = { 1165 .index = MSR_IA32_VMX_VMFUNC, 1166 } 1167 }, 1168 1169 [FEAT_14_0_ECX] = { 1170 .type = CPUID_FEATURE_WORD, 1171 .feat_names = { 1172 NULL, NULL, NULL, NULL, 1173 NULL, NULL, NULL, NULL, 1174 NULL, NULL, NULL, NULL, 1175 NULL, NULL, NULL, NULL, 1176 NULL, NULL, NULL, NULL, 1177 NULL, NULL, NULL, NULL, 1178 NULL, NULL, NULL, NULL, 1179 NULL, NULL, NULL, "intel-pt-lip", 1180 }, 1181 .cpuid = { 1182 .eax = 0x14, 1183 .needs_ecx = true, .ecx = 0, 1184 .reg = R_ECX, 1185 }, 1186 .tcg_features = TCG_14_0_ECX_FEATURES, 1187 }, 1188 1189 [FEAT_SGX_12_0_EAX] = { 1190 .type = CPUID_FEATURE_WORD, 1191 .feat_names = { 1192 "sgx1", "sgx2", NULL, NULL, 1193 NULL, NULL, NULL, NULL, 1194 NULL, NULL, NULL, NULL, 1195 NULL, NULL, NULL, NULL, 1196 NULL, NULL, NULL, NULL, 1197 NULL, NULL, NULL, NULL, 1198 NULL, NULL, NULL, NULL, 1199 NULL, NULL, NULL, NULL, 1200 }, 1201 .cpuid = { 1202 .eax = 0x12, 1203 .needs_ecx = true, .ecx = 0, 1204 .reg = R_EAX, 1205 }, 1206 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1207 }, 1208 1209 [FEAT_SGX_12_0_EBX] = { 1210 .type = CPUID_FEATURE_WORD, 1211 .feat_names = { 1212 "sgx-exinfo" , NULL, NULL, NULL, 1213 NULL, NULL, NULL, NULL, 1214 NULL, NULL, NULL, NULL, 1215 NULL, NULL, NULL, NULL, 1216 NULL, NULL, NULL, NULL, 1217 NULL, NULL, NULL, NULL, 1218 NULL, NULL, NULL, NULL, 1219 NULL, NULL, NULL, NULL, 1220 }, 1221 .cpuid = { 1222 .eax = 0x12, 1223 .needs_ecx = true, .ecx = 0, 1224 .reg = R_EBX, 1225 }, 1226 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1227 }, 1228 1229 [FEAT_SGX_12_1_EAX] = { 1230 .type = CPUID_FEATURE_WORD, 1231 .feat_names = { 1232 NULL, "sgx-debug", "sgx-mode64", NULL, 1233 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1234 NULL, NULL, NULL, NULL, 1235 NULL, NULL, NULL, NULL, 1236 NULL, NULL, NULL, NULL, 1237 NULL, NULL, NULL, NULL, 1238 NULL, NULL, NULL, NULL, 1239 NULL, NULL, NULL, NULL, 1240 }, 1241 .cpuid = { 1242 .eax = 0x12, 1243 .needs_ecx = true, .ecx = 1, 1244 .reg = R_EAX, 1245 }, 1246 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1247 }, 1248}; 1249 1250typedef struct FeatureMask { 1251 FeatureWord index; 1252 uint64_t mask; 1253} FeatureMask; 1254 1255typedef struct FeatureDep { 1256 FeatureMask from, to; 1257} FeatureDep; 1258 1259static FeatureDep feature_dependencies[] = { 1260 { 1261 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1262 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1263 }, 1264 { 1265 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1266 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1267 }, 1268 { 1269 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1270 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1271 }, 1272 { 1273 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1274 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1275 }, 1276 { 1277 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1278 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1279 }, 1280 { 1281 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1282 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1283 }, 1284 { 1285 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1286 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1287 }, 1288 { 1289 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1290 .to = { FEAT_VMX_MISC, ~0ull }, 1291 }, 1292 { 1293 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1294 .to = { FEAT_VMX_BASIC, ~0ull }, 1295 }, 1296 { 1297 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1298 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1299 }, 1300 { 1301 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1302 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1303 }, 1304 { 1305 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1306 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1307 }, 1308 { 1309 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1310 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1311 }, 1312 { 1313 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1314 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1315 }, 1316 { 1317 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1318 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1319 }, 1320 { 1321 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1322 .to = { FEAT_14_0_ECX, ~0ull }, 1323 }, 1324 { 1325 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1326 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1327 }, 1328 { 1329 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1330 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1331 }, 1332 { 1333 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1334 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1335 }, 1336 { 1337 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1338 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1339 }, 1340 { 1341 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1342 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1343 }, 1344 { 1345 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1346 .to = { FEAT_SVM, ~0ull }, 1347 }, 1348}; 1349 1350typedef struct X86RegisterInfo32 { 1351 /* Name of register */ 1352 const char *name; 1353 /* QAPI enum value register */ 1354 X86CPURegister32 qapi_enum; 1355} X86RegisterInfo32; 1356 1357#define REGISTER(reg) \ 1358 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1359static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1360 REGISTER(EAX), 1361 REGISTER(ECX), 1362 REGISTER(EDX), 1363 REGISTER(EBX), 1364 REGISTER(ESP), 1365 REGISTER(EBP), 1366 REGISTER(ESI), 1367 REGISTER(EDI), 1368}; 1369#undef REGISTER 1370 1371ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1372 [XSTATE_FP_BIT] = { 1373 /* x87 FP state component is always enabled if XSAVE is supported */ 1374 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1375 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1376 }, 1377 [XSTATE_SSE_BIT] = { 1378 /* SSE state component is always enabled if XSAVE is supported */ 1379 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1380 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1381 }, 1382 [XSTATE_YMM_BIT] = 1383 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1384 .size = sizeof(XSaveAVX) }, 1385 [XSTATE_BNDREGS_BIT] = 1386 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1387 .size = sizeof(XSaveBNDREG) }, 1388 [XSTATE_BNDCSR_BIT] = 1389 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1390 .size = sizeof(XSaveBNDCSR) }, 1391 [XSTATE_OPMASK_BIT] = 1392 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1393 .size = sizeof(XSaveOpmask) }, 1394 [XSTATE_ZMM_Hi256_BIT] = 1395 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1396 .size = sizeof(XSaveZMM_Hi256) }, 1397 [XSTATE_Hi16_ZMM_BIT] = 1398 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1399 .size = sizeof(XSaveHi16_ZMM) }, 1400 [XSTATE_PKRU_BIT] = 1401 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1402 .size = sizeof(XSavePKRU) }, 1403}; 1404 1405static uint32_t xsave_area_size(uint64_t mask) 1406{ 1407 int i; 1408 uint64_t ret = 0; 1409 1410 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1411 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 1412 if ((mask >> i) & 1) { 1413 ret = MAX(ret, esa->offset + esa->size); 1414 } 1415 } 1416 return ret; 1417} 1418 1419static inline bool accel_uses_host_cpuid(void) 1420{ 1421 return kvm_enabled() || hvf_enabled(); 1422} 1423 1424static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu) 1425{ 1426 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 | 1427 cpu->env.features[FEAT_XSAVE_COMP_LO]; 1428} 1429 1430/* Return name of 32-bit register, from a R_* constant */ 1431static const char *get_register_name_32(unsigned int reg) 1432{ 1433 if (reg >= CPU_NB_REGS32) { 1434 return NULL; 1435 } 1436 return x86_reg_info_32[reg].name; 1437} 1438 1439/* 1440 * Returns the set of feature flags that are supported and migratable by 1441 * QEMU, for a given FeatureWord. 1442 */ 1443static uint64_t x86_cpu_get_migratable_flags(FeatureWord w) 1444{ 1445 FeatureWordInfo *wi = &feature_word_info[w]; 1446 uint64_t r = 0; 1447 int i; 1448 1449 for (i = 0; i < 64; i++) { 1450 uint64_t f = 1ULL << i; 1451 1452 /* If the feature name is known, it is implicitly considered migratable, 1453 * unless it is explicitly set in unmigratable_flags */ 1454 if ((wi->migratable_flags & f) || 1455 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1456 r |= f; 1457 } 1458 } 1459 return r; 1460} 1461 1462void host_cpuid(uint32_t function, uint32_t count, 1463 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1464{ 1465 uint32_t vec[4]; 1466 1467#ifdef __x86_64__ 1468 asm volatile("cpuid" 1469 : "=a"(vec[0]), "=b"(vec[1]), 1470 "=c"(vec[2]), "=d"(vec[3]) 1471 : "0"(function), "c"(count) : "cc"); 1472#elif defined(__i386__) 1473 asm volatile("pusha \n\t" 1474 "cpuid \n\t" 1475 "mov %%eax, 0(%2) \n\t" 1476 "mov %%ebx, 4(%2) \n\t" 1477 "mov %%ecx, 8(%2) \n\t" 1478 "mov %%edx, 12(%2) \n\t" 1479 "popa" 1480 : : "a"(function), "c"(count), "S"(vec) 1481 : "memory", "cc"); 1482#else 1483 abort(); 1484#endif 1485 1486 if (eax) 1487 *eax = vec[0]; 1488 if (ebx) 1489 *ebx = vec[1]; 1490 if (ecx) 1491 *ecx = vec[2]; 1492 if (edx) 1493 *edx = vec[3]; 1494} 1495 1496/* CPU class name definitions: */ 1497 1498/* Return type name for a given CPU model name 1499 * Caller is responsible for freeing the returned string. 1500 */ 1501static char *x86_cpu_type_name(const char *model_name) 1502{ 1503 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1504} 1505 1506static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1507{ 1508 g_autofree char *typename = x86_cpu_type_name(cpu_model); 1509 return object_class_by_name(typename); 1510} 1511 1512static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1513{ 1514 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1515 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1516 return g_strndup(class_name, 1517 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX)); 1518} 1519 1520typedef struct X86CPUVersionDefinition { 1521 X86CPUVersion version; 1522 const char *alias; 1523 const char *note; 1524 PropValue *props; 1525 const CPUCaches *const cache_info; 1526} X86CPUVersionDefinition; 1527 1528/* Base definition for a CPU model */ 1529typedef struct X86CPUDefinition { 1530 const char *name; 1531 uint32_t level; 1532 uint32_t xlevel; 1533 /* vendor is zero-terminated, 12 character ASCII string */ 1534 char vendor[CPUID_VENDOR_SZ + 1]; 1535 int family; 1536 int model; 1537 int stepping; 1538 FeatureWordArray features; 1539 const char *model_id; 1540 const CPUCaches *const cache_info; 1541 /* 1542 * Definitions for alternative versions of CPU model. 1543 * List is terminated by item with version == 0. 1544 * If NULL, version 1 will be registered automatically. 1545 */ 1546 const X86CPUVersionDefinition *versions; 1547 const char *deprecation_note; 1548} X86CPUDefinition; 1549 1550/* Reference to a specific CPU model version */ 1551struct X86CPUModel { 1552 /* Base CPU definition */ 1553 const X86CPUDefinition *cpudef; 1554 /* CPU model version */ 1555 X86CPUVersion version; 1556 const char *note; 1557 /* 1558 * If true, this is an alias CPU model. 1559 * This matters only for "-cpu help" and query-cpu-definitions 1560 */ 1561 bool is_alias; 1562}; 1563 1564/* Get full model name for CPU version */ 1565static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 1566 X86CPUVersion version) 1567{ 1568 assert(version > 0); 1569 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 1570} 1571 1572static const X86CPUVersionDefinition * 1573x86_cpu_def_get_versions(const X86CPUDefinition *def) 1574{ 1575 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 1576 static const X86CPUVersionDefinition default_version_list[] = { 1577 { 1 }, 1578 { /* end of list */ } 1579 }; 1580 1581 return def->versions ?: default_version_list; 1582} 1583 1584static const CPUCaches epyc_cache_info = { 1585 .l1d_cache = &(CPUCacheInfo) { 1586 .type = DATA_CACHE, 1587 .level = 1, 1588 .size = 32 * KiB, 1589 .line_size = 64, 1590 .associativity = 8, 1591 .partitions = 1, 1592 .sets = 64, 1593 .lines_per_tag = 1, 1594 .self_init = 1, 1595 .no_invd_sharing = true, 1596 }, 1597 .l1i_cache = &(CPUCacheInfo) { 1598 .type = INSTRUCTION_CACHE, 1599 .level = 1, 1600 .size = 64 * KiB, 1601 .line_size = 64, 1602 .associativity = 4, 1603 .partitions = 1, 1604 .sets = 256, 1605 .lines_per_tag = 1, 1606 .self_init = 1, 1607 .no_invd_sharing = true, 1608 }, 1609 .l2_cache = &(CPUCacheInfo) { 1610 .type = UNIFIED_CACHE, 1611 .level = 2, 1612 .size = 512 * KiB, 1613 .line_size = 64, 1614 .associativity = 8, 1615 .partitions = 1, 1616 .sets = 1024, 1617 .lines_per_tag = 1, 1618 }, 1619 .l3_cache = &(CPUCacheInfo) { 1620 .type = UNIFIED_CACHE, 1621 .level = 3, 1622 .size = 8 * MiB, 1623 .line_size = 64, 1624 .associativity = 16, 1625 .partitions = 1, 1626 .sets = 8192, 1627 .lines_per_tag = 1, 1628 .self_init = true, 1629 .inclusive = true, 1630 .complex_indexing = true, 1631 }, 1632}; 1633 1634static CPUCaches epyc_v4_cache_info = { 1635 .l1d_cache = &(CPUCacheInfo) { 1636 .type = DATA_CACHE, 1637 .level = 1, 1638 .size = 32 * KiB, 1639 .line_size = 64, 1640 .associativity = 8, 1641 .partitions = 1, 1642 .sets = 64, 1643 .lines_per_tag = 1, 1644 .self_init = 1, 1645 .no_invd_sharing = true, 1646 }, 1647 .l1i_cache = &(CPUCacheInfo) { 1648 .type = INSTRUCTION_CACHE, 1649 .level = 1, 1650 .size = 64 * KiB, 1651 .line_size = 64, 1652 .associativity = 4, 1653 .partitions = 1, 1654 .sets = 256, 1655 .lines_per_tag = 1, 1656 .self_init = 1, 1657 .no_invd_sharing = true, 1658 }, 1659 .l2_cache = &(CPUCacheInfo) { 1660 .type = UNIFIED_CACHE, 1661 .level = 2, 1662 .size = 512 * KiB, 1663 .line_size = 64, 1664 .associativity = 8, 1665 .partitions = 1, 1666 .sets = 1024, 1667 .lines_per_tag = 1, 1668 }, 1669 .l3_cache = &(CPUCacheInfo) { 1670 .type = UNIFIED_CACHE, 1671 .level = 3, 1672 .size = 8 * MiB, 1673 .line_size = 64, 1674 .associativity = 16, 1675 .partitions = 1, 1676 .sets = 8192, 1677 .lines_per_tag = 1, 1678 .self_init = true, 1679 .inclusive = true, 1680 .complex_indexing = false, 1681 }, 1682}; 1683 1684static const CPUCaches epyc_rome_cache_info = { 1685 .l1d_cache = &(CPUCacheInfo) { 1686 .type = DATA_CACHE, 1687 .level = 1, 1688 .size = 32 * KiB, 1689 .line_size = 64, 1690 .associativity = 8, 1691 .partitions = 1, 1692 .sets = 64, 1693 .lines_per_tag = 1, 1694 .self_init = 1, 1695 .no_invd_sharing = true, 1696 }, 1697 .l1i_cache = &(CPUCacheInfo) { 1698 .type = INSTRUCTION_CACHE, 1699 .level = 1, 1700 .size = 32 * KiB, 1701 .line_size = 64, 1702 .associativity = 8, 1703 .partitions = 1, 1704 .sets = 64, 1705 .lines_per_tag = 1, 1706 .self_init = 1, 1707 .no_invd_sharing = true, 1708 }, 1709 .l2_cache = &(CPUCacheInfo) { 1710 .type = UNIFIED_CACHE, 1711 .level = 2, 1712 .size = 512 * KiB, 1713 .line_size = 64, 1714 .associativity = 8, 1715 .partitions = 1, 1716 .sets = 1024, 1717 .lines_per_tag = 1, 1718 }, 1719 .l3_cache = &(CPUCacheInfo) { 1720 .type = UNIFIED_CACHE, 1721 .level = 3, 1722 .size = 16 * MiB, 1723 .line_size = 64, 1724 .associativity = 16, 1725 .partitions = 1, 1726 .sets = 16384, 1727 .lines_per_tag = 1, 1728 .self_init = true, 1729 .inclusive = true, 1730 .complex_indexing = true, 1731 }, 1732}; 1733 1734static const CPUCaches epyc_rome_v3_cache_info = { 1735 .l1d_cache = &(CPUCacheInfo) { 1736 .type = DATA_CACHE, 1737 .level = 1, 1738 .size = 32 * KiB, 1739 .line_size = 64, 1740 .associativity = 8, 1741 .partitions = 1, 1742 .sets = 64, 1743 .lines_per_tag = 1, 1744 .self_init = 1, 1745 .no_invd_sharing = true, 1746 }, 1747 .l1i_cache = &(CPUCacheInfo) { 1748 .type = INSTRUCTION_CACHE, 1749 .level = 1, 1750 .size = 32 * KiB, 1751 .line_size = 64, 1752 .associativity = 8, 1753 .partitions = 1, 1754 .sets = 64, 1755 .lines_per_tag = 1, 1756 .self_init = 1, 1757 .no_invd_sharing = true, 1758 }, 1759 .l2_cache = &(CPUCacheInfo) { 1760 .type = UNIFIED_CACHE, 1761 .level = 2, 1762 .size = 512 * KiB, 1763 .line_size = 64, 1764 .associativity = 8, 1765 .partitions = 1, 1766 .sets = 1024, 1767 .lines_per_tag = 1, 1768 }, 1769 .l3_cache = &(CPUCacheInfo) { 1770 .type = UNIFIED_CACHE, 1771 .level = 3, 1772 .size = 16 * MiB, 1773 .line_size = 64, 1774 .associativity = 16, 1775 .partitions = 1, 1776 .sets = 16384, 1777 .lines_per_tag = 1, 1778 .self_init = true, 1779 .inclusive = true, 1780 .complex_indexing = false, 1781 }, 1782}; 1783 1784static const CPUCaches epyc_milan_cache_info = { 1785 .l1d_cache = &(CPUCacheInfo) { 1786 .type = DATA_CACHE, 1787 .level = 1, 1788 .size = 32 * KiB, 1789 .line_size = 64, 1790 .associativity = 8, 1791 .partitions = 1, 1792 .sets = 64, 1793 .lines_per_tag = 1, 1794 .self_init = 1, 1795 .no_invd_sharing = true, 1796 }, 1797 .l1i_cache = &(CPUCacheInfo) { 1798 .type = INSTRUCTION_CACHE, 1799 .level = 1, 1800 .size = 32 * KiB, 1801 .line_size = 64, 1802 .associativity = 8, 1803 .partitions = 1, 1804 .sets = 64, 1805 .lines_per_tag = 1, 1806 .self_init = 1, 1807 .no_invd_sharing = true, 1808 }, 1809 .l2_cache = &(CPUCacheInfo) { 1810 .type = UNIFIED_CACHE, 1811 .level = 2, 1812 .size = 512 * KiB, 1813 .line_size = 64, 1814 .associativity = 8, 1815 .partitions = 1, 1816 .sets = 1024, 1817 .lines_per_tag = 1, 1818 }, 1819 .l3_cache = &(CPUCacheInfo) { 1820 .type = UNIFIED_CACHE, 1821 .level = 3, 1822 .size = 32 * MiB, 1823 .line_size = 64, 1824 .associativity = 16, 1825 .partitions = 1, 1826 .sets = 32768, 1827 .lines_per_tag = 1, 1828 .self_init = true, 1829 .inclusive = true, 1830 .complex_indexing = true, 1831 }, 1832}; 1833 1834static const CPUCaches epyc_milan_v2_cache_info = { 1835 .l1d_cache = &(CPUCacheInfo) { 1836 .type = DATA_CACHE, 1837 .level = 1, 1838 .size = 32 * KiB, 1839 .line_size = 64, 1840 .associativity = 8, 1841 .partitions = 1, 1842 .sets = 64, 1843 .lines_per_tag = 1, 1844 .self_init = 1, 1845 .no_invd_sharing = true, 1846 }, 1847 .l1i_cache = &(CPUCacheInfo) { 1848 .type = INSTRUCTION_CACHE, 1849 .level = 1, 1850 .size = 32 * KiB, 1851 .line_size = 64, 1852 .associativity = 8, 1853 .partitions = 1, 1854 .sets = 64, 1855 .lines_per_tag = 1, 1856 .self_init = 1, 1857 .no_invd_sharing = true, 1858 }, 1859 .l2_cache = &(CPUCacheInfo) { 1860 .type = UNIFIED_CACHE, 1861 .level = 2, 1862 .size = 512 * KiB, 1863 .line_size = 64, 1864 .associativity = 8, 1865 .partitions = 1, 1866 .sets = 1024, 1867 .lines_per_tag = 1, 1868 }, 1869 .l3_cache = &(CPUCacheInfo) { 1870 .type = UNIFIED_CACHE, 1871 .level = 3, 1872 .size = 32 * MiB, 1873 .line_size = 64, 1874 .associativity = 16, 1875 .partitions = 1, 1876 .sets = 32768, 1877 .lines_per_tag = 1, 1878 .self_init = true, 1879 .inclusive = true, 1880 .complex_indexing = false, 1881 }, 1882}; 1883 1884/* The following VMX features are not supported by KVM and are left out in the 1885 * CPU definitions: 1886 * 1887 * Dual-monitor support (all processors) 1888 * Entry to SMM 1889 * Deactivate dual-monitor treatment 1890 * Number of CR3-target values 1891 * Shutdown activity state 1892 * Wait-for-SIPI activity state 1893 * PAUSE-loop exiting (Westmere and newer) 1894 * EPT-violation #VE (Broadwell and newer) 1895 * Inject event with insn length=0 (Skylake and newer) 1896 * Conceal non-root operation from PT 1897 * Conceal VM exits from PT 1898 * Conceal VM entries from PT 1899 * Enable ENCLS exiting 1900 * Mode-based execute control (XS/XU) 1901 s TSC scaling (Skylake Server and newer) 1902 * GPA translation for PT (IceLake and newer) 1903 * User wait and pause 1904 * ENCLV exiting 1905 * Load IA32_RTIT_CTL 1906 * Clear IA32_RTIT_CTL 1907 * Advanced VM-exit information for EPT violations 1908 * Sub-page write permissions 1909 * PT in VMX operation 1910 */ 1911 1912static const X86CPUDefinition builtin_x86_defs[] = { 1913 { 1914 .name = "qemu64", 1915 .level = 0xd, 1916 .vendor = CPUID_VENDOR_AMD, 1917 .family = 15, 1918 .model = 107, 1919 .stepping = 1, 1920 .features[FEAT_1_EDX] = 1921 PPRO_FEATURES | 1922 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1923 CPUID_PSE36, 1924 .features[FEAT_1_ECX] = 1925 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 1926 .features[FEAT_8000_0001_EDX] = 1927 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1928 .features[FEAT_8000_0001_ECX] = 1929 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 1930 .xlevel = 0x8000000A, 1931 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 1932 }, 1933 { 1934 .name = "phenom", 1935 .level = 5, 1936 .vendor = CPUID_VENDOR_AMD, 1937 .family = 16, 1938 .model = 2, 1939 .stepping = 3, 1940 /* Missing: CPUID_HT */ 1941 .features[FEAT_1_EDX] = 1942 PPRO_FEATURES | 1943 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1944 CPUID_PSE36 | CPUID_VME, 1945 .features[FEAT_1_ECX] = 1946 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 1947 CPUID_EXT_POPCNT, 1948 .features[FEAT_8000_0001_EDX] = 1949 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 1950 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 1951 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 1952 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 1953 CPUID_EXT3_CR8LEG, 1954 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 1955 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 1956 .features[FEAT_8000_0001_ECX] = 1957 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 1958 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 1959 /* Missing: CPUID_SVM_LBRV */ 1960 .features[FEAT_SVM] = 1961 CPUID_SVM_NPT, 1962 .xlevel = 0x8000001A, 1963 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 1964 }, 1965 { 1966 .name = "core2duo", 1967 .level = 10, 1968 .vendor = CPUID_VENDOR_INTEL, 1969 .family = 6, 1970 .model = 15, 1971 .stepping = 11, 1972 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 1973 .features[FEAT_1_EDX] = 1974 PPRO_FEATURES | 1975 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1976 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 1977 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 1978 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 1979 .features[FEAT_1_ECX] = 1980 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 1981 CPUID_EXT_CX16, 1982 .features[FEAT_8000_0001_EDX] = 1983 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1984 .features[FEAT_8000_0001_ECX] = 1985 CPUID_EXT3_LAHF_LM, 1986 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 1987 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1988 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1989 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1990 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1991 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 1992 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1993 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1994 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1995 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1996 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 1997 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 1998 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 1999 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2000 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2001 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2002 .features[FEAT_VMX_SECONDARY_CTLS] = 2003 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2004 .xlevel = 0x80000008, 2005 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2006 }, 2007 { 2008 .name = "kvm64", 2009 .level = 0xd, 2010 .vendor = CPUID_VENDOR_INTEL, 2011 .family = 15, 2012 .model = 6, 2013 .stepping = 1, 2014 /* Missing: CPUID_HT */ 2015 .features[FEAT_1_EDX] = 2016 PPRO_FEATURES | CPUID_VME | 2017 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2018 CPUID_PSE36, 2019 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2020 .features[FEAT_1_ECX] = 2021 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2022 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2023 .features[FEAT_8000_0001_EDX] = 2024 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2025 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2026 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2027 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2028 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2029 .features[FEAT_8000_0001_ECX] = 2030 0, 2031 /* VMX features from Cedar Mill/Prescott */ 2032 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2033 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2034 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2035 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2036 VMX_PIN_BASED_NMI_EXITING, 2037 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2038 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2039 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2040 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2041 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2042 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2043 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2044 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2045 .xlevel = 0x80000008, 2046 .model_id = "Common KVM processor" 2047 }, 2048 { 2049 .name = "qemu32", 2050 .level = 4, 2051 .vendor = CPUID_VENDOR_INTEL, 2052 .family = 6, 2053 .model = 6, 2054 .stepping = 3, 2055 .features[FEAT_1_EDX] = 2056 PPRO_FEATURES, 2057 .features[FEAT_1_ECX] = 2058 CPUID_EXT_SSE3, 2059 .xlevel = 0x80000004, 2060 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2061 }, 2062 { 2063 .name = "kvm32", 2064 .level = 5, 2065 .vendor = CPUID_VENDOR_INTEL, 2066 .family = 15, 2067 .model = 6, 2068 .stepping = 1, 2069 .features[FEAT_1_EDX] = 2070 PPRO_FEATURES | CPUID_VME | 2071 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2072 .features[FEAT_1_ECX] = 2073 CPUID_EXT_SSE3, 2074 .features[FEAT_8000_0001_ECX] = 2075 0, 2076 /* VMX features from Yonah */ 2077 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2078 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2079 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2080 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2081 VMX_PIN_BASED_NMI_EXITING, 2082 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2083 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2084 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2085 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2086 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2087 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2088 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2089 .xlevel = 0x80000008, 2090 .model_id = "Common 32-bit KVM processor" 2091 }, 2092 { 2093 .name = "coreduo", 2094 .level = 10, 2095 .vendor = CPUID_VENDOR_INTEL, 2096 .family = 6, 2097 .model = 14, 2098 .stepping = 8, 2099 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2100 .features[FEAT_1_EDX] = 2101 PPRO_FEATURES | CPUID_VME | 2102 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2103 CPUID_SS, 2104 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2105 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2106 .features[FEAT_1_ECX] = 2107 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2108 .features[FEAT_8000_0001_EDX] = 2109 CPUID_EXT2_NX, 2110 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2111 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2112 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2113 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2114 VMX_PIN_BASED_NMI_EXITING, 2115 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2116 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2117 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2118 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2119 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2120 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2121 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2122 .xlevel = 0x80000008, 2123 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2124 }, 2125 { 2126 .name = "486", 2127 .level = 1, 2128 .vendor = CPUID_VENDOR_INTEL, 2129 .family = 4, 2130 .model = 8, 2131 .stepping = 0, 2132 .features[FEAT_1_EDX] = 2133 I486_FEATURES, 2134 .xlevel = 0, 2135 .model_id = "", 2136 }, 2137 { 2138 .name = "pentium", 2139 .level = 1, 2140 .vendor = CPUID_VENDOR_INTEL, 2141 .family = 5, 2142 .model = 4, 2143 .stepping = 3, 2144 .features[FEAT_1_EDX] = 2145 PENTIUM_FEATURES, 2146 .xlevel = 0, 2147 .model_id = "", 2148 }, 2149 { 2150 .name = "pentium2", 2151 .level = 2, 2152 .vendor = CPUID_VENDOR_INTEL, 2153 .family = 6, 2154 .model = 5, 2155 .stepping = 2, 2156 .features[FEAT_1_EDX] = 2157 PENTIUM2_FEATURES, 2158 .xlevel = 0, 2159 .model_id = "", 2160 }, 2161 { 2162 .name = "pentium3", 2163 .level = 3, 2164 .vendor = CPUID_VENDOR_INTEL, 2165 .family = 6, 2166 .model = 7, 2167 .stepping = 3, 2168 .features[FEAT_1_EDX] = 2169 PENTIUM3_FEATURES, 2170 .xlevel = 0, 2171 .model_id = "", 2172 }, 2173 { 2174 .name = "athlon", 2175 .level = 2, 2176 .vendor = CPUID_VENDOR_AMD, 2177 .family = 6, 2178 .model = 2, 2179 .stepping = 3, 2180 .features[FEAT_1_EDX] = 2181 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2182 CPUID_MCA, 2183 .features[FEAT_8000_0001_EDX] = 2184 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2185 .xlevel = 0x80000008, 2186 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2187 }, 2188 { 2189 .name = "n270", 2190 .level = 10, 2191 .vendor = CPUID_VENDOR_INTEL, 2192 .family = 6, 2193 .model = 28, 2194 .stepping = 2, 2195 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2196 .features[FEAT_1_EDX] = 2197 PPRO_FEATURES | 2198 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2199 CPUID_ACPI | CPUID_SS, 2200 /* Some CPUs got no CPUID_SEP */ 2201 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2202 * CPUID_EXT_XTPR */ 2203 .features[FEAT_1_ECX] = 2204 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2205 CPUID_EXT_MOVBE, 2206 .features[FEAT_8000_0001_EDX] = 2207 CPUID_EXT2_NX, 2208 .features[FEAT_8000_0001_ECX] = 2209 CPUID_EXT3_LAHF_LM, 2210 .xlevel = 0x80000008, 2211 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2212 }, 2213 { 2214 .name = "Conroe", 2215 .level = 10, 2216 .vendor = CPUID_VENDOR_INTEL, 2217 .family = 6, 2218 .model = 15, 2219 .stepping = 3, 2220 .features[FEAT_1_EDX] = 2221 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2222 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2223 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2224 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2225 CPUID_DE | CPUID_FP87, 2226 .features[FEAT_1_ECX] = 2227 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2228 .features[FEAT_8000_0001_EDX] = 2229 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2230 .features[FEAT_8000_0001_ECX] = 2231 CPUID_EXT3_LAHF_LM, 2232 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2233 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2234 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2235 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2236 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2237 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2238 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2239 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2240 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2241 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2242 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2243 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2244 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2245 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2246 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2247 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2248 .features[FEAT_VMX_SECONDARY_CTLS] = 2249 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2250 .xlevel = 0x80000008, 2251 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2252 }, 2253 { 2254 .name = "Penryn", 2255 .level = 10, 2256 .vendor = CPUID_VENDOR_INTEL, 2257 .family = 6, 2258 .model = 23, 2259 .stepping = 3, 2260 .features[FEAT_1_EDX] = 2261 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2262 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2263 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2264 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2265 CPUID_DE | CPUID_FP87, 2266 .features[FEAT_1_ECX] = 2267 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2268 CPUID_EXT_SSE3, 2269 .features[FEAT_8000_0001_EDX] = 2270 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2271 .features[FEAT_8000_0001_ECX] = 2272 CPUID_EXT3_LAHF_LM, 2273 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2274 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2275 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2276 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2277 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2278 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2279 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2280 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2281 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2282 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2283 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2284 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2285 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2286 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2287 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2288 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2289 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2290 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2291 .features[FEAT_VMX_SECONDARY_CTLS] = 2292 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2293 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2294 .xlevel = 0x80000008, 2295 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2296 }, 2297 { 2298 .name = "Nehalem", 2299 .level = 11, 2300 .vendor = CPUID_VENDOR_INTEL, 2301 .family = 6, 2302 .model = 26, 2303 .stepping = 3, 2304 .features[FEAT_1_EDX] = 2305 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2306 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2307 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2308 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2309 CPUID_DE | CPUID_FP87, 2310 .features[FEAT_1_ECX] = 2311 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2312 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2313 .features[FEAT_8000_0001_EDX] = 2314 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2315 .features[FEAT_8000_0001_ECX] = 2316 CPUID_EXT3_LAHF_LM, 2317 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2318 MSR_VMX_BASIC_TRUE_CTLS, 2319 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2320 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2321 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2322 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2323 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2324 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2325 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2326 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2327 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2328 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2329 .features[FEAT_VMX_EXIT_CTLS] = 2330 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2331 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2332 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2333 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2334 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2335 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2336 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2337 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2338 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2339 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2340 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2341 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2342 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2343 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2344 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2345 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2346 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2347 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2348 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2349 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2350 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2351 .features[FEAT_VMX_SECONDARY_CTLS] = 2352 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2353 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2354 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2355 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2356 VMX_SECONDARY_EXEC_ENABLE_VPID, 2357 .xlevel = 0x80000008, 2358 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2359 .versions = (X86CPUVersionDefinition[]) { 2360 { .version = 1 }, 2361 { 2362 .version = 2, 2363 .alias = "Nehalem-IBRS", 2364 .props = (PropValue[]) { 2365 { "spec-ctrl", "on" }, 2366 { "model-id", 2367 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2368 { /* end of list */ } 2369 } 2370 }, 2371 { /* end of list */ } 2372 } 2373 }, 2374 { 2375 .name = "Westmere", 2376 .level = 11, 2377 .vendor = CPUID_VENDOR_INTEL, 2378 .family = 6, 2379 .model = 44, 2380 .stepping = 1, 2381 .features[FEAT_1_EDX] = 2382 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2383 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2384 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2385 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2386 CPUID_DE | CPUID_FP87, 2387 .features[FEAT_1_ECX] = 2388 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2389 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2390 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2391 .features[FEAT_8000_0001_EDX] = 2392 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2393 .features[FEAT_8000_0001_ECX] = 2394 CPUID_EXT3_LAHF_LM, 2395 .features[FEAT_6_EAX] = 2396 CPUID_6_EAX_ARAT, 2397 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2398 MSR_VMX_BASIC_TRUE_CTLS, 2399 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2400 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2401 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2402 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2403 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2404 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2405 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2406 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2407 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2408 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2409 .features[FEAT_VMX_EXIT_CTLS] = 2410 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2411 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2412 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2413 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2414 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2415 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2416 MSR_VMX_MISC_STORE_LMA, 2417 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2418 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2419 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2420 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2421 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2422 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2423 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2424 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2425 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2426 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2427 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2428 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2429 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2430 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2431 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2432 .features[FEAT_VMX_SECONDARY_CTLS] = 2433 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2434 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2435 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2436 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2437 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2438 .xlevel = 0x80000008, 2439 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 2440 .versions = (X86CPUVersionDefinition[]) { 2441 { .version = 1 }, 2442 { 2443 .version = 2, 2444 .alias = "Westmere-IBRS", 2445 .props = (PropValue[]) { 2446 { "spec-ctrl", "on" }, 2447 { "model-id", 2448 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 2449 { /* end of list */ } 2450 } 2451 }, 2452 { /* end of list */ } 2453 } 2454 }, 2455 { 2456 .name = "SandyBridge", 2457 .level = 0xd, 2458 .vendor = CPUID_VENDOR_INTEL, 2459 .family = 6, 2460 .model = 42, 2461 .stepping = 1, 2462 .features[FEAT_1_EDX] = 2463 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2464 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2465 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2466 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2467 CPUID_DE | CPUID_FP87, 2468 .features[FEAT_1_ECX] = 2469 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2470 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2471 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2472 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2473 CPUID_EXT_SSE3, 2474 .features[FEAT_8000_0001_EDX] = 2475 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2476 CPUID_EXT2_SYSCALL, 2477 .features[FEAT_8000_0001_ECX] = 2478 CPUID_EXT3_LAHF_LM, 2479 .features[FEAT_XSAVE] = 2480 CPUID_XSAVE_XSAVEOPT, 2481 .features[FEAT_6_EAX] = 2482 CPUID_6_EAX_ARAT, 2483 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2484 MSR_VMX_BASIC_TRUE_CTLS, 2485 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2486 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2487 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2488 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2489 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2490 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2491 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2492 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2493 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2494 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2495 .features[FEAT_VMX_EXIT_CTLS] = 2496 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2497 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2498 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2499 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2500 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2501 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2502 MSR_VMX_MISC_STORE_LMA, 2503 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2504 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2505 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2506 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2507 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2508 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2509 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2510 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2511 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2512 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2513 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2514 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2515 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2516 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2517 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2518 .features[FEAT_VMX_SECONDARY_CTLS] = 2519 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2520 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2521 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2522 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2523 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2524 .xlevel = 0x80000008, 2525 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 2526 .versions = (X86CPUVersionDefinition[]) { 2527 { .version = 1 }, 2528 { 2529 .version = 2, 2530 .alias = "SandyBridge-IBRS", 2531 .props = (PropValue[]) { 2532 { "spec-ctrl", "on" }, 2533 { "model-id", 2534 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 2535 { /* end of list */ } 2536 } 2537 }, 2538 { /* end of list */ } 2539 } 2540 }, 2541 { 2542 .name = "IvyBridge", 2543 .level = 0xd, 2544 .vendor = CPUID_VENDOR_INTEL, 2545 .family = 6, 2546 .model = 58, 2547 .stepping = 9, 2548 .features[FEAT_1_EDX] = 2549 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2550 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2551 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2552 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2553 CPUID_DE | CPUID_FP87, 2554 .features[FEAT_1_ECX] = 2555 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2556 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2557 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2558 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2559 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2560 .features[FEAT_7_0_EBX] = 2561 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 2562 CPUID_7_0_EBX_ERMS, 2563 .features[FEAT_8000_0001_EDX] = 2564 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2565 CPUID_EXT2_SYSCALL, 2566 .features[FEAT_8000_0001_ECX] = 2567 CPUID_EXT3_LAHF_LM, 2568 .features[FEAT_XSAVE] = 2569 CPUID_XSAVE_XSAVEOPT, 2570 .features[FEAT_6_EAX] = 2571 CPUID_6_EAX_ARAT, 2572 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2573 MSR_VMX_BASIC_TRUE_CTLS, 2574 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2575 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2576 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2577 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2578 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2579 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2580 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2581 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2582 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2583 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2584 .features[FEAT_VMX_EXIT_CTLS] = 2585 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2586 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2587 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2588 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2589 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2590 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2591 MSR_VMX_MISC_STORE_LMA, 2592 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2593 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2594 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2595 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2596 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2597 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2598 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2599 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2600 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2601 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2602 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2603 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2604 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2605 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2606 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2607 .features[FEAT_VMX_SECONDARY_CTLS] = 2608 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2609 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2610 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2611 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2612 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2613 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2614 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2615 VMX_SECONDARY_EXEC_RDRAND_EXITING, 2616 .xlevel = 0x80000008, 2617 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 2618 .versions = (X86CPUVersionDefinition[]) { 2619 { .version = 1 }, 2620 { 2621 .version = 2, 2622 .alias = "IvyBridge-IBRS", 2623 .props = (PropValue[]) { 2624 { "spec-ctrl", "on" }, 2625 { "model-id", 2626 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 2627 { /* end of list */ } 2628 } 2629 }, 2630 { /* end of list */ } 2631 } 2632 }, 2633 { 2634 .name = "Haswell", 2635 .level = 0xd, 2636 .vendor = CPUID_VENDOR_INTEL, 2637 .family = 6, 2638 .model = 60, 2639 .stepping = 4, 2640 .features[FEAT_1_EDX] = 2641 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2642 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2643 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2644 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2645 CPUID_DE | CPUID_FP87, 2646 .features[FEAT_1_ECX] = 2647 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2648 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2649 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2650 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2651 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2652 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2653 .features[FEAT_8000_0001_EDX] = 2654 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2655 CPUID_EXT2_SYSCALL, 2656 .features[FEAT_8000_0001_ECX] = 2657 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 2658 .features[FEAT_7_0_EBX] = 2659 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2660 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2661 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2662 CPUID_7_0_EBX_RTM, 2663 .features[FEAT_XSAVE] = 2664 CPUID_XSAVE_XSAVEOPT, 2665 .features[FEAT_6_EAX] = 2666 CPUID_6_EAX_ARAT, 2667 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2668 MSR_VMX_BASIC_TRUE_CTLS, 2669 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2670 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2671 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2672 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2673 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2674 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2675 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2676 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2677 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2678 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2679 .features[FEAT_VMX_EXIT_CTLS] = 2680 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2681 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2682 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2683 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2684 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2685 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2686 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2687 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2688 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2689 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2690 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2691 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2692 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2693 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2694 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2695 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2696 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2697 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2698 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2699 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2700 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2701 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2702 .features[FEAT_VMX_SECONDARY_CTLS] = 2703 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2704 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2705 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2706 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2707 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2708 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2709 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2710 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2711 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 2712 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2713 .xlevel = 0x80000008, 2714 .model_id = "Intel Core Processor (Haswell)", 2715 .versions = (X86CPUVersionDefinition[]) { 2716 { .version = 1 }, 2717 { 2718 .version = 2, 2719 .alias = "Haswell-noTSX", 2720 .props = (PropValue[]) { 2721 { "hle", "off" }, 2722 { "rtm", "off" }, 2723 { "stepping", "1" }, 2724 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 2725 { /* end of list */ } 2726 }, 2727 }, 2728 { 2729 .version = 3, 2730 .alias = "Haswell-IBRS", 2731 .props = (PropValue[]) { 2732 /* Restore TSX features removed by -v2 above */ 2733 { "hle", "on" }, 2734 { "rtm", "on" }, 2735 /* 2736 * Haswell and Haswell-IBRS had stepping=4 in 2737 * QEMU 4.0 and older 2738 */ 2739 { "stepping", "4" }, 2740 { "spec-ctrl", "on" }, 2741 { "model-id", 2742 "Intel Core Processor (Haswell, IBRS)" }, 2743 { /* end of list */ } 2744 } 2745 }, 2746 { 2747 .version = 4, 2748 .alias = "Haswell-noTSX-IBRS", 2749 .props = (PropValue[]) { 2750 { "hle", "off" }, 2751 { "rtm", "off" }, 2752 /* spec-ctrl was already enabled by -v3 above */ 2753 { "stepping", "1" }, 2754 { "model-id", 2755 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 2756 { /* end of list */ } 2757 } 2758 }, 2759 { /* end of list */ } 2760 } 2761 }, 2762 { 2763 .name = "Broadwell", 2764 .level = 0xd, 2765 .vendor = CPUID_VENDOR_INTEL, 2766 .family = 6, 2767 .model = 61, 2768 .stepping = 2, 2769 .features[FEAT_1_EDX] = 2770 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2771 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2772 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2773 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2774 CPUID_DE | CPUID_FP87, 2775 .features[FEAT_1_ECX] = 2776 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2777 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2778 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2779 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2780 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2781 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2782 .features[FEAT_8000_0001_EDX] = 2783 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2784 CPUID_EXT2_SYSCALL, 2785 .features[FEAT_8000_0001_ECX] = 2786 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2787 .features[FEAT_7_0_EBX] = 2788 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2789 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2790 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2791 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2792 CPUID_7_0_EBX_SMAP, 2793 .features[FEAT_XSAVE] = 2794 CPUID_XSAVE_XSAVEOPT, 2795 .features[FEAT_6_EAX] = 2796 CPUID_6_EAX_ARAT, 2797 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2798 MSR_VMX_BASIC_TRUE_CTLS, 2799 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2800 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2801 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2802 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2803 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2804 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2805 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2806 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2807 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2808 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2809 .features[FEAT_VMX_EXIT_CTLS] = 2810 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2811 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2812 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2813 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2814 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2815 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2816 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2817 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2818 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2819 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2820 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2821 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2822 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2823 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2824 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2825 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2826 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2827 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2828 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2829 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2830 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2831 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2832 .features[FEAT_VMX_SECONDARY_CTLS] = 2833 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2834 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2835 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2836 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2837 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2838 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2839 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2840 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2841 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 2842 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 2843 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2844 .xlevel = 0x80000008, 2845 .model_id = "Intel Core Processor (Broadwell)", 2846 .versions = (X86CPUVersionDefinition[]) { 2847 { .version = 1 }, 2848 { 2849 .version = 2, 2850 .alias = "Broadwell-noTSX", 2851 .props = (PropValue[]) { 2852 { "hle", "off" }, 2853 { "rtm", "off" }, 2854 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 2855 { /* end of list */ } 2856 }, 2857 }, 2858 { 2859 .version = 3, 2860 .alias = "Broadwell-IBRS", 2861 .props = (PropValue[]) { 2862 /* Restore TSX features removed by -v2 above */ 2863 { "hle", "on" }, 2864 { "rtm", "on" }, 2865 { "spec-ctrl", "on" }, 2866 { "model-id", 2867 "Intel Core Processor (Broadwell, IBRS)" }, 2868 { /* end of list */ } 2869 } 2870 }, 2871 { 2872 .version = 4, 2873 .alias = "Broadwell-noTSX-IBRS", 2874 .props = (PropValue[]) { 2875 { "hle", "off" }, 2876 { "rtm", "off" }, 2877 /* spec-ctrl was already enabled by -v3 above */ 2878 { "model-id", 2879 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 2880 { /* end of list */ } 2881 } 2882 }, 2883 { /* end of list */ } 2884 } 2885 }, 2886 { 2887 .name = "Skylake-Client", 2888 .level = 0xd, 2889 .vendor = CPUID_VENDOR_INTEL, 2890 .family = 6, 2891 .model = 94, 2892 .stepping = 3, 2893 .features[FEAT_1_EDX] = 2894 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2895 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2896 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2897 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2898 CPUID_DE | CPUID_FP87, 2899 .features[FEAT_1_ECX] = 2900 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2901 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2902 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2903 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2904 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2905 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2906 .features[FEAT_8000_0001_EDX] = 2907 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2908 CPUID_EXT2_SYSCALL, 2909 .features[FEAT_8000_0001_ECX] = 2910 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2911 .features[FEAT_7_0_EBX] = 2912 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2913 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2914 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2915 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2916 CPUID_7_0_EBX_SMAP, 2917 /* XSAVES is added in version 4 */ 2918 .features[FEAT_XSAVE] = 2919 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2920 CPUID_XSAVE_XGETBV1, 2921 .features[FEAT_6_EAX] = 2922 CPUID_6_EAX_ARAT, 2923 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 2924 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2925 MSR_VMX_BASIC_TRUE_CTLS, 2926 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2927 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2928 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2929 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2930 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2931 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2932 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2933 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2934 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2935 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2936 .features[FEAT_VMX_EXIT_CTLS] = 2937 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2938 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2939 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2940 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2941 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2942 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2943 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2944 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2945 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2946 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2947 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2948 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2949 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2950 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2951 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2952 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2953 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2954 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2955 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2956 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2957 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2958 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2959 .features[FEAT_VMX_SECONDARY_CTLS] = 2960 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2961 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2962 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2963 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2964 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2965 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 2966 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 2967 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2968 .xlevel = 0x80000008, 2969 .model_id = "Intel Core Processor (Skylake)", 2970 .versions = (X86CPUVersionDefinition[]) { 2971 { .version = 1 }, 2972 { 2973 .version = 2, 2974 .alias = "Skylake-Client-IBRS", 2975 .props = (PropValue[]) { 2976 { "spec-ctrl", "on" }, 2977 { "model-id", 2978 "Intel Core Processor (Skylake, IBRS)" }, 2979 { /* end of list */ } 2980 } 2981 }, 2982 { 2983 .version = 3, 2984 .alias = "Skylake-Client-noTSX-IBRS", 2985 .props = (PropValue[]) { 2986 { "hle", "off" }, 2987 { "rtm", "off" }, 2988 { "model-id", 2989 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 2990 { /* end of list */ } 2991 } 2992 }, 2993 { 2994 .version = 4, 2995 .note = "IBRS, XSAVES, no TSX", 2996 .props = (PropValue[]) { 2997 { "xsaves", "on" }, 2998 { "vmx-xsaves", "on" }, 2999 { /* end of list */ } 3000 } 3001 }, 3002 { /* end of list */ } 3003 } 3004 }, 3005 { 3006 .name = "Skylake-Server", 3007 .level = 0xd, 3008 .vendor = CPUID_VENDOR_INTEL, 3009 .family = 6, 3010 .model = 85, 3011 .stepping = 4, 3012 .features[FEAT_1_EDX] = 3013 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3014 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3015 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3016 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3017 CPUID_DE | CPUID_FP87, 3018 .features[FEAT_1_ECX] = 3019 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3020 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3021 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3022 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3023 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3024 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3025 .features[FEAT_8000_0001_EDX] = 3026 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3027 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3028 .features[FEAT_8000_0001_ECX] = 3029 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3030 .features[FEAT_7_0_EBX] = 3031 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3032 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3033 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3034 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3035 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3036 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3037 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3038 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3039 .features[FEAT_7_0_ECX] = 3040 CPUID_7_0_ECX_PKU, 3041 /* XSAVES is added in version 5 */ 3042 .features[FEAT_XSAVE] = 3043 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3044 CPUID_XSAVE_XGETBV1, 3045 .features[FEAT_6_EAX] = 3046 CPUID_6_EAX_ARAT, 3047 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3048 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3049 MSR_VMX_BASIC_TRUE_CTLS, 3050 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3051 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3052 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3053 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3054 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3055 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3056 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3057 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3058 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3059 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3060 .features[FEAT_VMX_EXIT_CTLS] = 3061 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3062 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3063 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3064 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3065 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3066 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3067 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3068 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3069 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3070 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3071 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3072 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3073 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3074 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3075 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3076 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3077 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3078 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3079 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3080 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3081 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3082 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3083 .features[FEAT_VMX_SECONDARY_CTLS] = 3084 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3085 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3086 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3087 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3088 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3089 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3090 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3091 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3092 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3093 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3094 .xlevel = 0x80000008, 3095 .model_id = "Intel Xeon Processor (Skylake)", 3096 .versions = (X86CPUVersionDefinition[]) { 3097 { .version = 1 }, 3098 { 3099 .version = 2, 3100 .alias = "Skylake-Server-IBRS", 3101 .props = (PropValue[]) { 3102 /* clflushopt was not added to Skylake-Server-IBRS */ 3103 /* TODO: add -v3 including clflushopt */ 3104 { "clflushopt", "off" }, 3105 { "spec-ctrl", "on" }, 3106 { "model-id", 3107 "Intel Xeon Processor (Skylake, IBRS)" }, 3108 { /* end of list */ } 3109 } 3110 }, 3111 { 3112 .version = 3, 3113 .alias = "Skylake-Server-noTSX-IBRS", 3114 .props = (PropValue[]) { 3115 { "hle", "off" }, 3116 { "rtm", "off" }, 3117 { "model-id", 3118 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3119 { /* end of list */ } 3120 } 3121 }, 3122 { 3123 .version = 4, 3124 .props = (PropValue[]) { 3125 { "vmx-eptp-switching", "on" }, 3126 { /* end of list */ } 3127 } 3128 }, 3129 { 3130 .version = 5, 3131 .note = "IBRS, XSAVES, EPT switching, no TSX", 3132 .props = (PropValue[]) { 3133 { "xsaves", "on" }, 3134 { "vmx-xsaves", "on" }, 3135 { /* end of list */ } 3136 } 3137 }, 3138 { /* end of list */ } 3139 } 3140 }, 3141 { 3142 .name = "Cascadelake-Server", 3143 .level = 0xd, 3144 .vendor = CPUID_VENDOR_INTEL, 3145 .family = 6, 3146 .model = 85, 3147 .stepping = 6, 3148 .features[FEAT_1_EDX] = 3149 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3150 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3151 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3152 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3153 CPUID_DE | CPUID_FP87, 3154 .features[FEAT_1_ECX] = 3155 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3156 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3157 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3158 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3159 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3160 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3161 .features[FEAT_8000_0001_EDX] = 3162 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3163 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3164 .features[FEAT_8000_0001_ECX] = 3165 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3166 .features[FEAT_7_0_EBX] = 3167 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3168 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3169 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3170 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3171 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3172 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3173 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3174 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3175 .features[FEAT_7_0_ECX] = 3176 CPUID_7_0_ECX_PKU | 3177 CPUID_7_0_ECX_AVX512VNNI, 3178 .features[FEAT_7_0_EDX] = 3179 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3180 /* XSAVES is added in version 5 */ 3181 .features[FEAT_XSAVE] = 3182 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3183 CPUID_XSAVE_XGETBV1, 3184 .features[FEAT_6_EAX] = 3185 CPUID_6_EAX_ARAT, 3186 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3187 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3188 MSR_VMX_BASIC_TRUE_CTLS, 3189 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3190 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3191 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3192 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3193 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3194 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3195 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3196 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3197 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3198 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3199 .features[FEAT_VMX_EXIT_CTLS] = 3200 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3201 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3202 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3203 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3204 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3205 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3206 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3207 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3208 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3209 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3210 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3211 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3212 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3213 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3214 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3215 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3216 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3217 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3218 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3219 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3220 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3221 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3222 .features[FEAT_VMX_SECONDARY_CTLS] = 3223 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3224 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3225 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3226 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3227 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3228 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3229 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3230 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3231 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3232 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3233 .xlevel = 0x80000008, 3234 .model_id = "Intel Xeon Processor (Cascadelake)", 3235 .versions = (X86CPUVersionDefinition[]) { 3236 { .version = 1 }, 3237 { .version = 2, 3238 .note = "ARCH_CAPABILITIES", 3239 .props = (PropValue[]) { 3240 { "arch-capabilities", "on" }, 3241 { "rdctl-no", "on" }, 3242 { "ibrs-all", "on" }, 3243 { "skip-l1dfl-vmentry", "on" }, 3244 { "mds-no", "on" }, 3245 { /* end of list */ } 3246 }, 3247 }, 3248 { .version = 3, 3249 .alias = "Cascadelake-Server-noTSX", 3250 .note = "ARCH_CAPABILITIES, no TSX", 3251 .props = (PropValue[]) { 3252 { "hle", "off" }, 3253 { "rtm", "off" }, 3254 { /* end of list */ } 3255 }, 3256 }, 3257 { .version = 4, 3258 .note = "ARCH_CAPABILITIES, no TSX", 3259 .props = (PropValue[]) { 3260 { "vmx-eptp-switching", "on" }, 3261 { /* end of list */ } 3262 }, 3263 }, 3264 { .version = 5, 3265 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3266 .props = (PropValue[]) { 3267 { "xsaves", "on" }, 3268 { "vmx-xsaves", "on" }, 3269 { /* end of list */ } 3270 }, 3271 }, 3272 { /* end of list */ } 3273 } 3274 }, 3275 { 3276 .name = "Cooperlake", 3277 .level = 0xd, 3278 .vendor = CPUID_VENDOR_INTEL, 3279 .family = 6, 3280 .model = 85, 3281 .stepping = 10, 3282 .features[FEAT_1_EDX] = 3283 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3284 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3285 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3286 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3287 CPUID_DE | CPUID_FP87, 3288 .features[FEAT_1_ECX] = 3289 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3290 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3291 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3292 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3293 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3294 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3295 .features[FEAT_8000_0001_EDX] = 3296 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3297 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3298 .features[FEAT_8000_0001_ECX] = 3299 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3300 .features[FEAT_7_0_EBX] = 3301 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3302 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3303 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3304 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3305 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3306 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3307 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3308 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3309 .features[FEAT_7_0_ECX] = 3310 CPUID_7_0_ECX_PKU | 3311 CPUID_7_0_ECX_AVX512VNNI, 3312 .features[FEAT_7_0_EDX] = 3313 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3314 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3315 .features[FEAT_ARCH_CAPABILITIES] = 3316 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3317 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3318 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3319 .features[FEAT_7_1_EAX] = 3320 CPUID_7_1_EAX_AVX512_BF16, 3321 /* XSAVES is added in version 2 */ 3322 .features[FEAT_XSAVE] = 3323 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3324 CPUID_XSAVE_XGETBV1, 3325 .features[FEAT_6_EAX] = 3326 CPUID_6_EAX_ARAT, 3327 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3328 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3329 MSR_VMX_BASIC_TRUE_CTLS, 3330 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3331 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3332 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3333 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3334 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3335 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3336 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3337 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3338 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3339 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3340 .features[FEAT_VMX_EXIT_CTLS] = 3341 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3342 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3343 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3344 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3345 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3346 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3347 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3348 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3349 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3350 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3351 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3352 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3353 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3354 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3355 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3356 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3357 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3358 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3359 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3360 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3361 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3362 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3363 .features[FEAT_VMX_SECONDARY_CTLS] = 3364 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3365 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3366 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3367 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3368 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3369 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3370 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3371 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3372 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3373 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3374 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3375 .xlevel = 0x80000008, 3376 .model_id = "Intel Xeon Processor (Cooperlake)", 3377 .versions = (X86CPUVersionDefinition[]) { 3378 { .version = 1 }, 3379 { .version = 2, 3380 .note = "XSAVES", 3381 .props = (PropValue[]) { 3382 { "xsaves", "on" }, 3383 { "vmx-xsaves", "on" }, 3384 { /* end of list */ } 3385 }, 3386 }, 3387 { /* end of list */ } 3388 } 3389 }, 3390 { 3391 .name = "Icelake-Client", 3392 .level = 0xd, 3393 .vendor = CPUID_VENDOR_INTEL, 3394 .family = 6, 3395 .model = 126, 3396 .stepping = 0, 3397 .features[FEAT_1_EDX] = 3398 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3399 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3400 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3401 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3402 CPUID_DE | CPUID_FP87, 3403 .features[FEAT_1_ECX] = 3404 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3405 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3406 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3407 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3408 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3409 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3410 .features[FEAT_8000_0001_EDX] = 3411 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3412 CPUID_EXT2_SYSCALL, 3413 .features[FEAT_8000_0001_ECX] = 3414 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3415 .features[FEAT_8000_0008_EBX] = 3416 CPUID_8000_0008_EBX_WBNOINVD, 3417 .features[FEAT_7_0_EBX] = 3418 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3419 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3420 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3421 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3422 CPUID_7_0_EBX_SMAP, 3423 .features[FEAT_7_0_ECX] = 3424 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3425 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3426 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3427 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3428 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 3429 .features[FEAT_7_0_EDX] = 3430 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3431 /* XSAVES is added in version 3 */ 3432 .features[FEAT_XSAVE] = 3433 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3434 CPUID_XSAVE_XGETBV1, 3435 .features[FEAT_6_EAX] = 3436 CPUID_6_EAX_ARAT, 3437 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3438 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3439 MSR_VMX_BASIC_TRUE_CTLS, 3440 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3441 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3442 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3443 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3444 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3445 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3446 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3447 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3448 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3449 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3450 .features[FEAT_VMX_EXIT_CTLS] = 3451 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3452 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3453 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3454 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3455 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3456 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3457 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3458 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3459 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3460 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3461 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3462 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3463 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3464 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3465 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3466 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3467 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3468 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3469 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3470 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3471 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3472 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3473 .features[FEAT_VMX_SECONDARY_CTLS] = 3474 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3475 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3476 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3477 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3478 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3479 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3480 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3481 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3482 .xlevel = 0x80000008, 3483 .model_id = "Intel Core Processor (Icelake)", 3484 .versions = (X86CPUVersionDefinition[]) { 3485 { 3486 .version = 1, 3487 .note = "deprecated" 3488 }, 3489 { 3490 .version = 2, 3491 .note = "no TSX, deprecated", 3492 .alias = "Icelake-Client-noTSX", 3493 .props = (PropValue[]) { 3494 { "hle", "off" }, 3495 { "rtm", "off" }, 3496 { /* end of list */ } 3497 }, 3498 }, 3499 { 3500 .version = 3, 3501 .note = "no TSX, XSAVES, deprecated", 3502 .props = (PropValue[]) { 3503 { "xsaves", "on" }, 3504 { "vmx-xsaves", "on" }, 3505 { /* end of list */ } 3506 }, 3507 }, 3508 { /* end of list */ } 3509 }, 3510 .deprecation_note = "use Icelake-Server instead" 3511 }, 3512 { 3513 .name = "Icelake-Server", 3514 .level = 0xd, 3515 .vendor = CPUID_VENDOR_INTEL, 3516 .family = 6, 3517 .model = 134, 3518 .stepping = 0, 3519 .features[FEAT_1_EDX] = 3520 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3521 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3522 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3523 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3524 CPUID_DE | CPUID_FP87, 3525 .features[FEAT_1_ECX] = 3526 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3527 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3528 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3529 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3530 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3531 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3532 .features[FEAT_8000_0001_EDX] = 3533 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3534 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3535 .features[FEAT_8000_0001_ECX] = 3536 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3537 .features[FEAT_8000_0008_EBX] = 3538 CPUID_8000_0008_EBX_WBNOINVD, 3539 .features[FEAT_7_0_EBX] = 3540 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3541 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3542 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3543 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3544 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3545 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3546 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3547 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3548 .features[FEAT_7_0_ECX] = 3549 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3550 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3551 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3552 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3553 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 3554 .features[FEAT_7_0_EDX] = 3555 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3556 /* XSAVES is added in version 5 */ 3557 .features[FEAT_XSAVE] = 3558 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3559 CPUID_XSAVE_XGETBV1, 3560 .features[FEAT_6_EAX] = 3561 CPUID_6_EAX_ARAT, 3562 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3563 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3564 MSR_VMX_BASIC_TRUE_CTLS, 3565 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3566 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3567 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3568 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3569 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3570 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3571 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3572 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3573 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3574 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3575 .features[FEAT_VMX_EXIT_CTLS] = 3576 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3577 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3578 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3579 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3580 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3581 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3582 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3583 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3584 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3585 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3586 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3587 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3588 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3589 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3590 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3591 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3592 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3593 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3594 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3595 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3596 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3597 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3598 .features[FEAT_VMX_SECONDARY_CTLS] = 3599 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3600 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3601 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3602 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3603 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3604 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3605 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3606 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3607 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3608 .xlevel = 0x80000008, 3609 .model_id = "Intel Xeon Processor (Icelake)", 3610 .versions = (X86CPUVersionDefinition[]) { 3611 { .version = 1 }, 3612 { 3613 .version = 2, 3614 .note = "no TSX", 3615 .alias = "Icelake-Server-noTSX", 3616 .props = (PropValue[]) { 3617 { "hle", "off" }, 3618 { "rtm", "off" }, 3619 { /* end of list */ } 3620 }, 3621 }, 3622 { 3623 .version = 3, 3624 .props = (PropValue[]) { 3625 { "arch-capabilities", "on" }, 3626 { "rdctl-no", "on" }, 3627 { "ibrs-all", "on" }, 3628 { "skip-l1dfl-vmentry", "on" }, 3629 { "mds-no", "on" }, 3630 { "pschange-mc-no", "on" }, 3631 { "taa-no", "on" }, 3632 { /* end of list */ } 3633 }, 3634 }, 3635 { 3636 .version = 4, 3637 .props = (PropValue[]) { 3638 { "sha-ni", "on" }, 3639 { "avx512ifma", "on" }, 3640 { "rdpid", "on" }, 3641 { "fsrm", "on" }, 3642 { "vmx-rdseed-exit", "on" }, 3643 { "vmx-pml", "on" }, 3644 { "vmx-eptp-switching", "on" }, 3645 { "model", "106" }, 3646 { /* end of list */ } 3647 }, 3648 }, 3649 { 3650 .version = 5, 3651 .note = "XSAVES", 3652 .props = (PropValue[]) { 3653 { "xsaves", "on" }, 3654 { "vmx-xsaves", "on" }, 3655 { /* end of list */ } 3656 }, 3657 }, 3658 { /* end of list */ } 3659 } 3660 }, 3661 { 3662 .name = "Denverton", 3663 .level = 21, 3664 .vendor = CPUID_VENDOR_INTEL, 3665 .family = 6, 3666 .model = 95, 3667 .stepping = 1, 3668 .features[FEAT_1_EDX] = 3669 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 3670 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 3671 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3672 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 3673 CPUID_SSE | CPUID_SSE2, 3674 .features[FEAT_1_ECX] = 3675 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 3676 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 3677 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3678 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 3679 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 3680 .features[FEAT_8000_0001_EDX] = 3681 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 3682 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 3683 .features[FEAT_8000_0001_ECX] = 3684 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3685 .features[FEAT_7_0_EBX] = 3686 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 3687 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 3688 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 3689 .features[FEAT_7_0_EDX] = 3690 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 3691 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3692 /* XSAVES is added in version 3 */ 3693 .features[FEAT_XSAVE] = 3694 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 3695 .features[FEAT_6_EAX] = 3696 CPUID_6_EAX_ARAT, 3697 .features[FEAT_ARCH_CAPABILITIES] = 3698 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 3699 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3700 MSR_VMX_BASIC_TRUE_CTLS, 3701 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3702 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3703 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3704 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3705 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3706 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3707 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3708 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3709 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3710 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3711 .features[FEAT_VMX_EXIT_CTLS] = 3712 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3713 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3714 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3715 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3716 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3717 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3718 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3719 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3720 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3721 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3722 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3723 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3724 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3725 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3726 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3727 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3728 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3729 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3730 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3731 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3732 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3733 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3734 .features[FEAT_VMX_SECONDARY_CTLS] = 3735 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3736 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3737 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3738 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3739 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3740 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3741 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3742 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3743 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3744 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3745 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3746 .xlevel = 0x80000008, 3747 .model_id = "Intel Atom Processor (Denverton)", 3748 .versions = (X86CPUVersionDefinition[]) { 3749 { .version = 1 }, 3750 { 3751 .version = 2, 3752 .note = "no MPX, no MONITOR", 3753 .props = (PropValue[]) { 3754 { "monitor", "off" }, 3755 { "mpx", "off" }, 3756 { /* end of list */ }, 3757 }, 3758 }, 3759 { 3760 .version = 3, 3761 .note = "XSAVES, no MPX, no MONITOR", 3762 .props = (PropValue[]) { 3763 { "xsaves", "on" }, 3764 { "vmx-xsaves", "on" }, 3765 { /* end of list */ }, 3766 }, 3767 }, 3768 { /* end of list */ }, 3769 }, 3770 }, 3771 { 3772 .name = "Snowridge", 3773 .level = 27, 3774 .vendor = CPUID_VENDOR_INTEL, 3775 .family = 6, 3776 .model = 134, 3777 .stepping = 1, 3778 .features[FEAT_1_EDX] = 3779 /* missing: CPUID_PN CPUID_IA64 */ 3780 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 3781 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 3782 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 3783 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 3784 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3785 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 3786 CPUID_MMX | 3787 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 3788 .features[FEAT_1_ECX] = 3789 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 3790 CPUID_EXT_SSSE3 | 3791 CPUID_EXT_CX16 | 3792 CPUID_EXT_SSE41 | 3793 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3794 CPUID_EXT_POPCNT | 3795 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 3796 CPUID_EXT_RDRAND, 3797 .features[FEAT_8000_0001_EDX] = 3798 CPUID_EXT2_SYSCALL | 3799 CPUID_EXT2_NX | 3800 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3801 CPUID_EXT2_LM, 3802 .features[FEAT_8000_0001_ECX] = 3803 CPUID_EXT3_LAHF_LM | 3804 CPUID_EXT3_3DNOWPREFETCH, 3805 .features[FEAT_7_0_EBX] = 3806 CPUID_7_0_EBX_FSGSBASE | 3807 CPUID_7_0_EBX_SMEP | 3808 CPUID_7_0_EBX_ERMS | 3809 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 3810 CPUID_7_0_EBX_RDSEED | 3811 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 3812 CPUID_7_0_EBX_CLWB | 3813 CPUID_7_0_EBX_SHA_NI, 3814 .features[FEAT_7_0_ECX] = 3815 CPUID_7_0_ECX_UMIP | 3816 /* missing bit 5 */ 3817 CPUID_7_0_ECX_GFNI | 3818 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 3819 CPUID_7_0_ECX_MOVDIR64B, 3820 .features[FEAT_7_0_EDX] = 3821 CPUID_7_0_EDX_SPEC_CTRL | 3822 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 3823 CPUID_7_0_EDX_CORE_CAPABILITY, 3824 .features[FEAT_CORE_CAPABILITY] = 3825 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 3826 /* XSAVES is is added in version 3 */ 3827 .features[FEAT_XSAVE] = 3828 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3829 CPUID_XSAVE_XGETBV1, 3830 .features[FEAT_6_EAX] = 3831 CPUID_6_EAX_ARAT, 3832 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3833 MSR_VMX_BASIC_TRUE_CTLS, 3834 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3835 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3836 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3837 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3838 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3839 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3840 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3841 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3842 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3843 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3844 .features[FEAT_VMX_EXIT_CTLS] = 3845 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3846 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3847 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3848 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3849 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3850 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3851 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3852 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3853 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3854 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3855 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3856 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3857 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3858 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3859 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3860 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3861 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3862 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3863 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3864 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3865 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3866 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3867 .features[FEAT_VMX_SECONDARY_CTLS] = 3868 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3869 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3870 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3871 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3872 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3873 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3874 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3875 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3876 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3877 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3878 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3879 .xlevel = 0x80000008, 3880 .model_id = "Intel Atom Processor (SnowRidge)", 3881 .versions = (X86CPUVersionDefinition[]) { 3882 { .version = 1 }, 3883 { 3884 .version = 2, 3885 .props = (PropValue[]) { 3886 { "mpx", "off" }, 3887 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 3888 { /* end of list */ }, 3889 }, 3890 }, 3891 { 3892 .version = 3, 3893 .note = "XSAVES, no MPX", 3894 .props = (PropValue[]) { 3895 { "xsaves", "on" }, 3896 { "vmx-xsaves", "on" }, 3897 { /* end of list */ }, 3898 }, 3899 }, 3900 { 3901 .version = 4, 3902 .note = "no split lock detect", 3903 .props = (PropValue[]) { 3904 { "split-lock-detect", "off" }, 3905 { /* end of list */ }, 3906 }, 3907 }, 3908 { /* end of list */ }, 3909 }, 3910 }, 3911 { 3912 .name = "KnightsMill", 3913 .level = 0xd, 3914 .vendor = CPUID_VENDOR_INTEL, 3915 .family = 6, 3916 .model = 133, 3917 .stepping = 0, 3918 .features[FEAT_1_EDX] = 3919 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 3920 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 3921 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 3922 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 3923 CPUID_PSE | CPUID_DE | CPUID_FP87, 3924 .features[FEAT_1_ECX] = 3925 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3926 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3927 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3928 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3929 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3930 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3931 .features[FEAT_8000_0001_EDX] = 3932 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3933 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3934 .features[FEAT_8000_0001_ECX] = 3935 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3936 .features[FEAT_7_0_EBX] = 3937 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 3938 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 3939 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 3940 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 3941 CPUID_7_0_EBX_AVX512ER, 3942 .features[FEAT_7_0_ECX] = 3943 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 3944 .features[FEAT_7_0_EDX] = 3945 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 3946 .features[FEAT_XSAVE] = 3947 CPUID_XSAVE_XSAVEOPT, 3948 .features[FEAT_6_EAX] = 3949 CPUID_6_EAX_ARAT, 3950 .xlevel = 0x80000008, 3951 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 3952 }, 3953 { 3954 .name = "Opteron_G1", 3955 .level = 5, 3956 .vendor = CPUID_VENDOR_AMD, 3957 .family = 15, 3958 .model = 6, 3959 .stepping = 1, 3960 .features[FEAT_1_EDX] = 3961 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3962 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3963 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3964 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3965 CPUID_DE | CPUID_FP87, 3966 .features[FEAT_1_ECX] = 3967 CPUID_EXT_SSE3, 3968 .features[FEAT_8000_0001_EDX] = 3969 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3970 .xlevel = 0x80000008, 3971 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 3972 }, 3973 { 3974 .name = "Opteron_G2", 3975 .level = 5, 3976 .vendor = CPUID_VENDOR_AMD, 3977 .family = 15, 3978 .model = 6, 3979 .stepping = 1, 3980 .features[FEAT_1_EDX] = 3981 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3982 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3983 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3984 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3985 CPUID_DE | CPUID_FP87, 3986 .features[FEAT_1_ECX] = 3987 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 3988 .features[FEAT_8000_0001_EDX] = 3989 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3990 .features[FEAT_8000_0001_ECX] = 3991 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 3992 .xlevel = 0x80000008, 3993 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 3994 }, 3995 { 3996 .name = "Opteron_G3", 3997 .level = 5, 3998 .vendor = CPUID_VENDOR_AMD, 3999 .family = 16, 4000 .model = 2, 4001 .stepping = 3, 4002 .features[FEAT_1_EDX] = 4003 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4004 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4005 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4006 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4007 CPUID_DE | CPUID_FP87, 4008 .features[FEAT_1_ECX] = 4009 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 4010 CPUID_EXT_SSE3, 4011 .features[FEAT_8000_0001_EDX] = 4012 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 4013 CPUID_EXT2_RDTSCP, 4014 .features[FEAT_8000_0001_ECX] = 4015 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 4016 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4017 .xlevel = 0x80000008, 4018 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 4019 }, 4020 { 4021 .name = "Opteron_G4", 4022 .level = 0xd, 4023 .vendor = CPUID_VENDOR_AMD, 4024 .family = 21, 4025 .model = 1, 4026 .stepping = 2, 4027 .features[FEAT_1_EDX] = 4028 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4029 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4030 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4031 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4032 CPUID_DE | CPUID_FP87, 4033 .features[FEAT_1_ECX] = 4034 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4035 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4036 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 4037 CPUID_EXT_SSE3, 4038 .features[FEAT_8000_0001_EDX] = 4039 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4040 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4041 .features[FEAT_8000_0001_ECX] = 4042 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4043 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4044 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4045 CPUID_EXT3_LAHF_LM, 4046 .features[FEAT_SVM] = 4047 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4048 /* no xsaveopt! */ 4049 .xlevel = 0x8000001A, 4050 .model_id = "AMD Opteron 62xx class CPU", 4051 }, 4052 { 4053 .name = "Opteron_G5", 4054 .level = 0xd, 4055 .vendor = CPUID_VENDOR_AMD, 4056 .family = 21, 4057 .model = 2, 4058 .stepping = 0, 4059 .features[FEAT_1_EDX] = 4060 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4061 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4062 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4063 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4064 CPUID_DE | CPUID_FP87, 4065 .features[FEAT_1_ECX] = 4066 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 4067 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 4068 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4069 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4070 .features[FEAT_8000_0001_EDX] = 4071 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4072 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4073 .features[FEAT_8000_0001_ECX] = 4074 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4075 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4076 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4077 CPUID_EXT3_LAHF_LM, 4078 .features[FEAT_SVM] = 4079 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4080 /* no xsaveopt! */ 4081 .xlevel = 0x8000001A, 4082 .model_id = "AMD Opteron 63xx class CPU", 4083 }, 4084 { 4085 .name = "EPYC", 4086 .level = 0xd, 4087 .vendor = CPUID_VENDOR_AMD, 4088 .family = 23, 4089 .model = 1, 4090 .stepping = 2, 4091 .features[FEAT_1_EDX] = 4092 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4093 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4094 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4095 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4096 CPUID_VME | CPUID_FP87, 4097 .features[FEAT_1_ECX] = 4098 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4099 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4100 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4101 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4102 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4103 .features[FEAT_8000_0001_EDX] = 4104 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4105 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4106 CPUID_EXT2_SYSCALL, 4107 .features[FEAT_8000_0001_ECX] = 4108 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4109 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4110 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4111 CPUID_EXT3_TOPOEXT, 4112 .features[FEAT_7_0_EBX] = 4113 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4114 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4115 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4116 CPUID_7_0_EBX_SHA_NI, 4117 .features[FEAT_XSAVE] = 4118 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4119 CPUID_XSAVE_XGETBV1, 4120 .features[FEAT_6_EAX] = 4121 CPUID_6_EAX_ARAT, 4122 .features[FEAT_SVM] = 4123 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4124 .xlevel = 0x8000001E, 4125 .model_id = "AMD EPYC Processor", 4126 .cache_info = &epyc_cache_info, 4127 .versions = (X86CPUVersionDefinition[]) { 4128 { .version = 1 }, 4129 { 4130 .version = 2, 4131 .alias = "EPYC-IBPB", 4132 .props = (PropValue[]) { 4133 { "ibpb", "on" }, 4134 { "model-id", 4135 "AMD EPYC Processor (with IBPB)" }, 4136 { /* end of list */ } 4137 } 4138 }, 4139 { 4140 .version = 3, 4141 .props = (PropValue[]) { 4142 { "ibpb", "on" }, 4143 { "perfctr-core", "on" }, 4144 { "clzero", "on" }, 4145 { "xsaveerptr", "on" }, 4146 { "xsaves", "on" }, 4147 { "model-id", 4148 "AMD EPYC Processor" }, 4149 { /* end of list */ } 4150 } 4151 }, 4152 { 4153 .version = 4, 4154 .note = "compatible with SEV-SNP CPUID enforcement", 4155 .props = (PropValue[]) { 4156 { "model-id", 4157 "AMD EPYC-v4 Processor" }, 4158 { /* end of list */ } 4159 }, 4160 .cache_info = &epyc_v4_cache_info 4161 }, 4162 { /* end of list */ } 4163 } 4164 }, 4165 { 4166 .name = "Dhyana", 4167 .level = 0xd, 4168 .vendor = CPUID_VENDOR_HYGON, 4169 .family = 24, 4170 .model = 0, 4171 .stepping = 1, 4172 .features[FEAT_1_EDX] = 4173 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4174 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4175 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4176 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4177 CPUID_VME | CPUID_FP87, 4178 .features[FEAT_1_ECX] = 4179 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4180 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 4181 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4182 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4183 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 4184 .features[FEAT_8000_0001_EDX] = 4185 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4186 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4187 CPUID_EXT2_SYSCALL, 4188 .features[FEAT_8000_0001_ECX] = 4189 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4190 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4191 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4192 CPUID_EXT3_TOPOEXT, 4193 .features[FEAT_8000_0008_EBX] = 4194 CPUID_8000_0008_EBX_IBPB, 4195 .features[FEAT_7_0_EBX] = 4196 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4197 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4198 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 4199 /* XSAVES is added in version 2 */ 4200 .features[FEAT_XSAVE] = 4201 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4202 CPUID_XSAVE_XGETBV1, 4203 .features[FEAT_6_EAX] = 4204 CPUID_6_EAX_ARAT, 4205 .features[FEAT_SVM] = 4206 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4207 .xlevel = 0x8000001E, 4208 .model_id = "Hygon Dhyana Processor", 4209 .cache_info = &epyc_cache_info, 4210 .versions = (X86CPUVersionDefinition[]) { 4211 { .version = 1 }, 4212 { .version = 2, 4213 .note = "XSAVES", 4214 .props = (PropValue[]) { 4215 { "xsaves", "on" }, 4216 { /* end of list */ } 4217 }, 4218 }, 4219 { /* end of list */ } 4220 } 4221 }, 4222 { 4223 .name = "EPYC-Rome", 4224 .level = 0xd, 4225 .vendor = CPUID_VENDOR_AMD, 4226 .family = 23, 4227 .model = 49, 4228 .stepping = 0, 4229 .features[FEAT_1_EDX] = 4230 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4231 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4232 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4233 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4234 CPUID_VME | CPUID_FP87, 4235 .features[FEAT_1_ECX] = 4236 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4237 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4238 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4239 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4240 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4241 .features[FEAT_8000_0001_EDX] = 4242 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4243 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4244 CPUID_EXT2_SYSCALL, 4245 .features[FEAT_8000_0001_ECX] = 4246 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4247 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4248 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4249 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4250 .features[FEAT_8000_0008_EBX] = 4251 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4252 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4253 CPUID_8000_0008_EBX_STIBP, 4254 .features[FEAT_7_0_EBX] = 4255 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4256 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4257 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4258 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 4259 .features[FEAT_7_0_ECX] = 4260 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 4261 .features[FEAT_XSAVE] = 4262 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4263 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4264 .features[FEAT_6_EAX] = 4265 CPUID_6_EAX_ARAT, 4266 .features[FEAT_SVM] = 4267 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4268 .xlevel = 0x8000001E, 4269 .model_id = "AMD EPYC-Rome Processor", 4270 .cache_info = &epyc_rome_cache_info, 4271 .versions = (X86CPUVersionDefinition[]) { 4272 { .version = 1 }, 4273 { 4274 .version = 2, 4275 .props = (PropValue[]) { 4276 { "ibrs", "on" }, 4277 { "amd-ssbd", "on" }, 4278 { /* end of list */ } 4279 } 4280 }, 4281 { 4282 .version = 3, 4283 .note = "compatible with SEV-SNP CPUID enforcement", 4284 .props = (PropValue[]) { 4285 { "model-id", 4286 "AMD EPYC-Rome-v3 Processor" }, 4287 { /* end of list */ } 4288 }, 4289 .cache_info = &epyc_rome_v3_cache_info 4290 }, 4291 { /* end of list */ } 4292 } 4293 }, 4294 { 4295 .name = "EPYC-Milan", 4296 .level = 0xd, 4297 .vendor = CPUID_VENDOR_AMD, 4298 .family = 25, 4299 .model = 1, 4300 .stepping = 1, 4301 .features[FEAT_1_EDX] = 4302 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4303 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4304 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4305 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4306 CPUID_VME | CPUID_FP87, 4307 .features[FEAT_1_ECX] = 4308 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4309 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4310 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4311 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4312 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4313 CPUID_EXT_PCID, 4314 .features[FEAT_8000_0001_EDX] = 4315 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4316 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4317 CPUID_EXT2_SYSCALL, 4318 .features[FEAT_8000_0001_ECX] = 4319 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4320 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4321 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4322 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4323 .features[FEAT_8000_0008_EBX] = 4324 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4325 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4326 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 4327 CPUID_8000_0008_EBX_AMD_SSBD, 4328 .features[FEAT_7_0_EBX] = 4329 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4330 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4331 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4332 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 4333 CPUID_7_0_EBX_INVPCID, 4334 .features[FEAT_7_0_ECX] = 4335 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 4336 .features[FEAT_7_0_EDX] = 4337 CPUID_7_0_EDX_FSRM, 4338 .features[FEAT_XSAVE] = 4339 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4340 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4341 .features[FEAT_6_EAX] = 4342 CPUID_6_EAX_ARAT, 4343 .features[FEAT_SVM] = 4344 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 4345 .xlevel = 0x8000001E, 4346 .model_id = "AMD EPYC-Milan Processor", 4347 .cache_info = &epyc_milan_cache_info, 4348 .versions = (X86CPUVersionDefinition[]) { 4349 { .version = 1 }, 4350 { 4351 .version = 2, 4352 .note = "compatible with SEV-SNP CPUID enforcement", 4353 .props = (PropValue[]) { 4354 { "model-id", 4355 "AMD EPYC-Milan-v2 Processor" }, 4356 { /* end of list */ } 4357 }, 4358 .cache_info = &epyc_milan_v2_cache_info 4359 }, 4360 { /* end of list */ } 4361 } 4362 }, 4363}; 4364 4365/* 4366 * We resolve CPU model aliases using -v1 when using "-machine 4367 * none", but this is just for compatibility while libvirt isn't 4368 * adapted to resolve CPU model versions before creating VMs. 4369 * See "Runnability guarantee of CPU models" at 4370 * docs/about/deprecated.rst. 4371 */ 4372X86CPUVersion default_cpu_version = 1; 4373 4374void x86_cpu_set_default_version(X86CPUVersion version) 4375{ 4376 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 4377 assert(version != CPU_VERSION_AUTO); 4378 default_cpu_version = version; 4379} 4380 4381static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 4382{ 4383 int v = 0; 4384 const X86CPUVersionDefinition *vdef = 4385 x86_cpu_def_get_versions(model->cpudef); 4386 while (vdef->version) { 4387 v = vdef->version; 4388 vdef++; 4389 } 4390 return v; 4391} 4392 4393/* Return the actual version being used for a specific CPU model */ 4394static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 4395{ 4396 X86CPUVersion v = model->version; 4397 if (v == CPU_VERSION_AUTO) { 4398 v = default_cpu_version; 4399 } 4400 if (v == CPU_VERSION_LATEST) { 4401 return x86_cpu_model_last_version(model); 4402 } 4403 return v; 4404} 4405 4406static Property max_x86_cpu_properties[] = { 4407 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 4408 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 4409 DEFINE_PROP_END_OF_LIST() 4410}; 4411 4412static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 4413{ 4414 DeviceClass *dc = DEVICE_CLASS(oc); 4415 X86CPUClass *xcc = X86_CPU_CLASS(oc); 4416 4417 xcc->ordering = 9; 4418 4419 xcc->model_description = 4420 "Enables all features supported by the accelerator in the current host"; 4421 4422 device_class_set_props(dc, max_x86_cpu_properties); 4423} 4424 4425static void max_x86_cpu_initfn(Object *obj) 4426{ 4427 X86CPU *cpu = X86_CPU(obj); 4428 4429 /* We can't fill the features array here because we don't know yet if 4430 * "migratable" is true or false. 4431 */ 4432 cpu->max_features = true; 4433 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 4434 4435 /* 4436 * these defaults are used for TCG and all other accelerators 4437 * besides KVM and HVF, which overwrite these values 4438 */ 4439 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 4440 &error_abort); 4441#ifdef TARGET_X86_64 4442 object_property_set_int(OBJECT(cpu), "family", 15, &error_abort); 4443 object_property_set_int(OBJECT(cpu), "model", 107, &error_abort); 4444 object_property_set_int(OBJECT(cpu), "stepping", 1, &error_abort); 4445#else 4446 object_property_set_int(OBJECT(cpu), "family", 6, &error_abort); 4447 object_property_set_int(OBJECT(cpu), "model", 6, &error_abort); 4448 object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort); 4449#endif 4450 object_property_set_str(OBJECT(cpu), "model-id", 4451 "QEMU TCG CPU version " QEMU_HW_VERSION, 4452 &error_abort); 4453} 4454 4455static const TypeInfo max_x86_cpu_type_info = { 4456 .name = X86_CPU_TYPE_NAME("max"), 4457 .parent = TYPE_X86_CPU, 4458 .instance_init = max_x86_cpu_initfn, 4459 .class_init = max_x86_cpu_class_init, 4460}; 4461 4462static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 4463{ 4464 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 4465 4466 switch (f->type) { 4467 case CPUID_FEATURE_WORD: 4468 { 4469 const char *reg = get_register_name_32(f->cpuid.reg); 4470 assert(reg); 4471 return g_strdup_printf("CPUID.%02XH:%s", 4472 f->cpuid.eax, reg); 4473 } 4474 case MSR_FEATURE_WORD: 4475 return g_strdup_printf("MSR(%02XH)", 4476 f->msr.index); 4477 } 4478 4479 return NULL; 4480} 4481 4482static bool x86_cpu_have_filtered_features(X86CPU *cpu) 4483{ 4484 FeatureWord w; 4485 4486 for (w = 0; w < FEATURE_WORDS; w++) { 4487 if (cpu->filtered_features[w]) { 4488 return true; 4489 } 4490 } 4491 4492 return false; 4493} 4494 4495static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 4496 const char *verbose_prefix) 4497{ 4498 CPUX86State *env = &cpu->env; 4499 FeatureWordInfo *f = &feature_word_info[w]; 4500 int i; 4501 4502 if (!cpu->force_features) { 4503 env->features[w] &= ~mask; 4504 } 4505 cpu->filtered_features[w] |= mask; 4506 4507 if (!verbose_prefix) { 4508 return; 4509 } 4510 4511 for (i = 0; i < 64; ++i) { 4512 if ((1ULL << i) & mask) { 4513 g_autofree char *feat_word_str = feature_word_description(f, i); 4514 warn_report("%s: %s%s%s [bit %d]", 4515 verbose_prefix, 4516 feat_word_str, 4517 f->feat_names[i] ? "." : "", 4518 f->feat_names[i] ? f->feat_names[i] : "", i); 4519 } 4520 } 4521} 4522 4523static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 4524 const char *name, void *opaque, 4525 Error **errp) 4526{ 4527 X86CPU *cpu = X86_CPU(obj); 4528 CPUX86State *env = &cpu->env; 4529 int64_t value; 4530 4531 value = (env->cpuid_version >> 8) & 0xf; 4532 if (value == 0xf) { 4533 value += (env->cpuid_version >> 20) & 0xff; 4534 } 4535 visit_type_int(v, name, &value, errp); 4536} 4537 4538static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 4539 const char *name, void *opaque, 4540 Error **errp) 4541{ 4542 X86CPU *cpu = X86_CPU(obj); 4543 CPUX86State *env = &cpu->env; 4544 const int64_t min = 0; 4545 const int64_t max = 0xff + 0xf; 4546 int64_t value; 4547 4548 if (!visit_type_int(v, name, &value, errp)) { 4549 return; 4550 } 4551 if (value < min || value > max) { 4552 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4553 name ? name : "null", value, min, max); 4554 return; 4555 } 4556 4557 env->cpuid_version &= ~0xff00f00; 4558 if (value > 0x0f) { 4559 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 4560 } else { 4561 env->cpuid_version |= value << 8; 4562 } 4563} 4564 4565static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 4566 const char *name, void *opaque, 4567 Error **errp) 4568{ 4569 X86CPU *cpu = X86_CPU(obj); 4570 CPUX86State *env = &cpu->env; 4571 int64_t value; 4572 4573 value = (env->cpuid_version >> 4) & 0xf; 4574 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 4575 visit_type_int(v, name, &value, errp); 4576} 4577 4578static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 4579 const char *name, void *opaque, 4580 Error **errp) 4581{ 4582 X86CPU *cpu = X86_CPU(obj); 4583 CPUX86State *env = &cpu->env; 4584 const int64_t min = 0; 4585 const int64_t max = 0xff; 4586 int64_t value; 4587 4588 if (!visit_type_int(v, name, &value, errp)) { 4589 return; 4590 } 4591 if (value < min || value > max) { 4592 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4593 name ? name : "null", value, min, max); 4594 return; 4595 } 4596 4597 env->cpuid_version &= ~0xf00f0; 4598 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 4599} 4600 4601static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 4602 const char *name, void *opaque, 4603 Error **errp) 4604{ 4605 X86CPU *cpu = X86_CPU(obj); 4606 CPUX86State *env = &cpu->env; 4607 int64_t value; 4608 4609 value = env->cpuid_version & 0xf; 4610 visit_type_int(v, name, &value, errp); 4611} 4612 4613static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 4614 const char *name, void *opaque, 4615 Error **errp) 4616{ 4617 X86CPU *cpu = X86_CPU(obj); 4618 CPUX86State *env = &cpu->env; 4619 const int64_t min = 0; 4620 const int64_t max = 0xf; 4621 int64_t value; 4622 4623 if (!visit_type_int(v, name, &value, errp)) { 4624 return; 4625 } 4626 if (value < min || value > max) { 4627 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4628 name ? name : "null", value, min, max); 4629 return; 4630 } 4631 4632 env->cpuid_version &= ~0xf; 4633 env->cpuid_version |= value & 0xf; 4634} 4635 4636static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 4637{ 4638 X86CPU *cpu = X86_CPU(obj); 4639 CPUX86State *env = &cpu->env; 4640 char *value; 4641 4642 value = g_malloc(CPUID_VENDOR_SZ + 1); 4643 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 4644 env->cpuid_vendor3); 4645 return value; 4646} 4647 4648static void x86_cpuid_set_vendor(Object *obj, const char *value, 4649 Error **errp) 4650{ 4651 X86CPU *cpu = X86_CPU(obj); 4652 CPUX86State *env = &cpu->env; 4653 int i; 4654 4655 if (strlen(value) != CPUID_VENDOR_SZ) { 4656 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value); 4657 return; 4658 } 4659 4660 env->cpuid_vendor1 = 0; 4661 env->cpuid_vendor2 = 0; 4662 env->cpuid_vendor3 = 0; 4663 for (i = 0; i < 4; i++) { 4664 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 4665 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 4666 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 4667 } 4668} 4669 4670static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 4671{ 4672 X86CPU *cpu = X86_CPU(obj); 4673 CPUX86State *env = &cpu->env; 4674 char *value; 4675 int i; 4676 4677 value = g_malloc(48 + 1); 4678 for (i = 0; i < 48; i++) { 4679 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 4680 } 4681 value[48] = '\0'; 4682 return value; 4683} 4684 4685static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 4686 Error **errp) 4687{ 4688 X86CPU *cpu = X86_CPU(obj); 4689 CPUX86State *env = &cpu->env; 4690 int c, len, i; 4691 4692 if (model_id == NULL) { 4693 model_id = ""; 4694 } 4695 len = strlen(model_id); 4696 memset(env->cpuid_model, 0, 48); 4697 for (i = 0; i < 48; i++) { 4698 if (i >= len) { 4699 c = '\0'; 4700 } else { 4701 c = (uint8_t)model_id[i]; 4702 } 4703 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 4704 } 4705} 4706 4707static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 4708 void *opaque, Error **errp) 4709{ 4710 X86CPU *cpu = X86_CPU(obj); 4711 int64_t value; 4712 4713 value = cpu->env.tsc_khz * 1000; 4714 visit_type_int(v, name, &value, errp); 4715} 4716 4717static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 4718 void *opaque, Error **errp) 4719{ 4720 X86CPU *cpu = X86_CPU(obj); 4721 const int64_t min = 0; 4722 const int64_t max = INT64_MAX; 4723 int64_t value; 4724 4725 if (!visit_type_int(v, name, &value, errp)) { 4726 return; 4727 } 4728 if (value < min || value > max) { 4729 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4730 name ? name : "null", value, min, max); 4731 return; 4732 } 4733 4734 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 4735} 4736 4737/* Generic getter for "feature-words" and "filtered-features" properties */ 4738static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 4739 const char *name, void *opaque, 4740 Error **errp) 4741{ 4742 uint64_t *array = (uint64_t *)opaque; 4743 FeatureWord w; 4744 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 4745 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 4746 X86CPUFeatureWordInfoList *list = NULL; 4747 4748 for (w = 0; w < FEATURE_WORDS; w++) { 4749 FeatureWordInfo *wi = &feature_word_info[w]; 4750 /* 4751 * We didn't have MSR features when "feature-words" was 4752 * introduced. Therefore skipped other type entries. 4753 */ 4754 if (wi->type != CPUID_FEATURE_WORD) { 4755 continue; 4756 } 4757 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 4758 qwi->cpuid_input_eax = wi->cpuid.eax; 4759 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 4760 qwi->cpuid_input_ecx = wi->cpuid.ecx; 4761 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 4762 qwi->features = array[w]; 4763 4764 /* List will be in reverse order, but order shouldn't matter */ 4765 list_entries[w].next = list; 4766 list_entries[w].value = &word_infos[w]; 4767 list = &list_entries[w]; 4768 } 4769 4770 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 4771} 4772 4773/* Convert all '_' in a feature string option name to '-', to make feature 4774 * name conform to QOM property naming rule, which uses '-' instead of '_'. 4775 */ 4776static inline void feat2prop(char *s) 4777{ 4778 while ((s = strchr(s, '_'))) { 4779 *s = '-'; 4780 } 4781} 4782 4783/* Return the feature property name for a feature flag bit */ 4784static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 4785{ 4786 const char *name; 4787 /* XSAVE components are automatically enabled by other features, 4788 * so return the original feature name instead 4789 */ 4790 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) { 4791 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr; 4792 4793 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 4794 x86_ext_save_areas[comp].bits) { 4795 w = x86_ext_save_areas[comp].feature; 4796 bitnr = ctz32(x86_ext_save_areas[comp].bits); 4797 } 4798 } 4799 4800 assert(bitnr < 64); 4801 assert(w < FEATURE_WORDS); 4802 name = feature_word_info[w].feat_names[bitnr]; 4803 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 4804 return name; 4805} 4806 4807/* Compatibily hack to maintain legacy +-feat semantic, 4808 * where +-feat overwrites any feature set by 4809 * feat=on|feat even if the later is parsed after +-feat 4810 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 4811 */ 4812static GList *plus_features, *minus_features; 4813 4814static gint compare_string(gconstpointer a, gconstpointer b) 4815{ 4816 return g_strcmp0(a, b); 4817} 4818 4819/* Parse "+feature,-feature,feature=foo" CPU feature string 4820 */ 4821static void x86_cpu_parse_featurestr(const char *typename, char *features, 4822 Error **errp) 4823{ 4824 char *featurestr; /* Single 'key=value" string being parsed */ 4825 static bool cpu_globals_initialized; 4826 bool ambiguous = false; 4827 4828 if (cpu_globals_initialized) { 4829 return; 4830 } 4831 cpu_globals_initialized = true; 4832 4833 if (!features) { 4834 return; 4835 } 4836 4837 for (featurestr = strtok(features, ","); 4838 featurestr; 4839 featurestr = strtok(NULL, ",")) { 4840 const char *name; 4841 const char *val = NULL; 4842 char *eq = NULL; 4843 char num[32]; 4844 GlobalProperty *prop; 4845 4846 /* Compatibility syntax: */ 4847 if (featurestr[0] == '+') { 4848 plus_features = g_list_append(plus_features, 4849 g_strdup(featurestr + 1)); 4850 continue; 4851 } else if (featurestr[0] == '-') { 4852 minus_features = g_list_append(minus_features, 4853 g_strdup(featurestr + 1)); 4854 continue; 4855 } 4856 4857 eq = strchr(featurestr, '='); 4858 if (eq) { 4859 *eq++ = 0; 4860 val = eq; 4861 } else { 4862 val = "on"; 4863 } 4864 4865 feat2prop(featurestr); 4866 name = featurestr; 4867 4868 if (g_list_find_custom(plus_features, name, compare_string)) { 4869 warn_report("Ambiguous CPU model string. " 4870 "Don't mix both \"+%s\" and \"%s=%s\"", 4871 name, name, val); 4872 ambiguous = true; 4873 } 4874 if (g_list_find_custom(minus_features, name, compare_string)) { 4875 warn_report("Ambiguous CPU model string. " 4876 "Don't mix both \"-%s\" and \"%s=%s\"", 4877 name, name, val); 4878 ambiguous = true; 4879 } 4880 4881 /* Special case: */ 4882 if (!strcmp(name, "tsc-freq")) { 4883 int ret; 4884 uint64_t tsc_freq; 4885 4886 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 4887 if (ret < 0 || tsc_freq > INT64_MAX) { 4888 error_setg(errp, "bad numerical value %s", val); 4889 return; 4890 } 4891 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 4892 val = num; 4893 name = "tsc-frequency"; 4894 } 4895 4896 prop = g_new0(typeof(*prop), 1); 4897 prop->driver = typename; 4898 prop->property = g_strdup(name); 4899 prop->value = g_strdup(val); 4900 qdev_prop_register_global(prop); 4901 } 4902 4903 if (ambiguous) { 4904 warn_report("Compatibility of ambiguous CPU model " 4905 "strings won't be kept on future QEMU versions"); 4906 } 4907} 4908 4909static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 4910 4911/* Build a list with the name of all features on a feature word array */ 4912static void x86_cpu_list_feature_names(FeatureWordArray features, 4913 strList **list) 4914{ 4915 strList **tail = list; 4916 FeatureWord w; 4917 4918 for (w = 0; w < FEATURE_WORDS; w++) { 4919 uint64_t filtered = features[w]; 4920 int i; 4921 for (i = 0; i < 64; i++) { 4922 if (filtered & (1ULL << i)) { 4923 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 4924 } 4925 } 4926 } 4927} 4928 4929static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 4930 const char *name, void *opaque, 4931 Error **errp) 4932{ 4933 X86CPU *xc = X86_CPU(obj); 4934 strList *result = NULL; 4935 4936 x86_cpu_list_feature_names(xc->filtered_features, &result); 4937 visit_type_strList(v, "unavailable-features", &result, errp); 4938} 4939 4940/* Check for missing features that may prevent the CPU class from 4941 * running using the current machine and accelerator. 4942 */ 4943static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 4944 strList **list) 4945{ 4946 strList **tail = list; 4947 X86CPU *xc; 4948 Error *err = NULL; 4949 4950 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 4951 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 4952 return; 4953 } 4954 4955 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 4956 4957 x86_cpu_expand_features(xc, &err); 4958 if (err) { 4959 /* Errors at x86_cpu_expand_features should never happen, 4960 * but in case it does, just report the model as not 4961 * runnable at all using the "type" property. 4962 */ 4963 QAPI_LIST_APPEND(tail, g_strdup("type")); 4964 error_free(err); 4965 } 4966 4967 x86_cpu_filter_features(xc, false); 4968 4969 x86_cpu_list_feature_names(xc->filtered_features, tail); 4970 4971 object_unref(OBJECT(xc)); 4972} 4973 4974/* Print all cpuid feature names in featureset 4975 */ 4976static void listflags(GList *features) 4977{ 4978 size_t len = 0; 4979 GList *tmp; 4980 4981 for (tmp = features; tmp; tmp = tmp->next) { 4982 const char *name = tmp->data; 4983 if ((len + strlen(name) + 1) >= 75) { 4984 qemu_printf("\n"); 4985 len = 0; 4986 } 4987 qemu_printf("%s%s", len == 0 ? " " : " ", name); 4988 len += strlen(name) + 1; 4989 } 4990 qemu_printf("\n"); 4991} 4992 4993/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 4994static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 4995{ 4996 ObjectClass *class_a = (ObjectClass *)a; 4997 ObjectClass *class_b = (ObjectClass *)b; 4998 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 4999 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 5000 int ret; 5001 5002 if (cc_a->ordering != cc_b->ordering) { 5003 ret = cc_a->ordering - cc_b->ordering; 5004 } else { 5005 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 5006 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 5007 ret = strcmp(name_a, name_b); 5008 } 5009 return ret; 5010} 5011 5012static GSList *get_sorted_cpu_model_list(void) 5013{ 5014 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 5015 list = g_slist_sort(list, x86_cpu_list_compare); 5016 return list; 5017} 5018 5019static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 5020{ 5021 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 5022 char *r = object_property_get_str(obj, "model-id", &error_abort); 5023 object_unref(obj); 5024 return r; 5025} 5026 5027static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 5028{ 5029 X86CPUVersion version; 5030 5031 if (!cc->model || !cc->model->is_alias) { 5032 return NULL; 5033 } 5034 version = x86_cpu_model_resolve_version(cc->model); 5035 if (version <= 0) { 5036 return NULL; 5037 } 5038 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 5039} 5040 5041static void x86_cpu_list_entry(gpointer data, gpointer user_data) 5042{ 5043 ObjectClass *oc = data; 5044 X86CPUClass *cc = X86_CPU_CLASS(oc); 5045 g_autofree char *name = x86_cpu_class_get_model_name(cc); 5046 g_autofree char *desc = g_strdup(cc->model_description); 5047 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 5048 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 5049 5050 if (!desc && alias_of) { 5051 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 5052 desc = g_strdup("(alias configured by machine type)"); 5053 } else { 5054 desc = g_strdup_printf("(alias of %s)", alias_of); 5055 } 5056 } 5057 if (!desc && cc->model && cc->model->note) { 5058 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 5059 } 5060 if (!desc) { 5061 desc = g_strdup_printf("%s", model_id); 5062 } 5063 5064 qemu_printf("x86 %-20s %-58s\n", name, desc); 5065} 5066 5067/* list available CPU models and flags */ 5068void x86_cpu_list(void) 5069{ 5070 int i, j; 5071 GSList *list; 5072 GList *names = NULL; 5073 5074 qemu_printf("Available CPUs:\n"); 5075 list = get_sorted_cpu_model_list(); 5076 g_slist_foreach(list, x86_cpu_list_entry, NULL); 5077 g_slist_free(list); 5078 5079 names = NULL; 5080 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 5081 FeatureWordInfo *fw = &feature_word_info[i]; 5082 for (j = 0; j < 64; j++) { 5083 if (fw->feat_names[j]) { 5084 names = g_list_append(names, (gpointer)fw->feat_names[j]); 5085 } 5086 } 5087 } 5088 5089 names = g_list_sort(names, (GCompareFunc)strcmp); 5090 5091 qemu_printf("\nRecognized CPUID flags:\n"); 5092 listflags(names); 5093 qemu_printf("\n"); 5094 g_list_free(names); 5095} 5096 5097static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 5098{ 5099 ObjectClass *oc = data; 5100 X86CPUClass *cc = X86_CPU_CLASS(oc); 5101 CpuDefinitionInfoList **cpu_list = user_data; 5102 CpuDefinitionInfo *info; 5103 5104 info = g_malloc0(sizeof(*info)); 5105 info->name = x86_cpu_class_get_model_name(cc); 5106 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 5107 info->has_unavailable_features = true; 5108 info->q_typename = g_strdup(object_class_get_name(oc)); 5109 info->migration_safe = cc->migration_safe; 5110 info->has_migration_safe = true; 5111 info->q_static = cc->static_model; 5112 if (cc->model && cc->model->cpudef->deprecation_note) { 5113 info->deprecated = true; 5114 } else { 5115 info->deprecated = false; 5116 } 5117 /* 5118 * Old machine types won't report aliases, so that alias translation 5119 * doesn't break compatibility with previous QEMU versions. 5120 */ 5121 if (default_cpu_version != CPU_VERSION_LEGACY) { 5122 info->alias_of = x86_cpu_class_get_alias_of(cc); 5123 info->has_alias_of = !!info->alias_of; 5124 } 5125 5126 QAPI_LIST_PREPEND(*cpu_list, info); 5127} 5128 5129CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 5130{ 5131 CpuDefinitionInfoList *cpu_list = NULL; 5132 GSList *list = get_sorted_cpu_model_list(); 5133 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 5134 g_slist_free(list); 5135 return cpu_list; 5136} 5137 5138static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, 5139 bool migratable_only) 5140{ 5141 FeatureWordInfo *wi = &feature_word_info[w]; 5142 uint64_t r = 0; 5143 5144 if (kvm_enabled()) { 5145 switch (wi->type) { 5146 case CPUID_FEATURE_WORD: 5147 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 5148 wi->cpuid.ecx, 5149 wi->cpuid.reg); 5150 break; 5151 case MSR_FEATURE_WORD: 5152 r = kvm_arch_get_supported_msr_feature(kvm_state, 5153 wi->msr.index); 5154 break; 5155 } 5156 } else if (hvf_enabled()) { 5157 if (wi->type != CPUID_FEATURE_WORD) { 5158 return 0; 5159 } 5160 r = hvf_get_supported_cpuid(wi->cpuid.eax, 5161 wi->cpuid.ecx, 5162 wi->cpuid.reg); 5163 } else if (tcg_enabled()) { 5164 r = wi->tcg_features; 5165 } else { 5166 return ~0; 5167 } 5168#ifndef TARGET_X86_64 5169 if (w == FEAT_8000_0001_EDX) { 5170 r &= ~CPUID_EXT2_LM; 5171 } 5172#endif 5173 if (migratable_only) { 5174 r &= x86_cpu_get_migratable_flags(w); 5175 } 5176 return r; 5177} 5178 5179/* 5180 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5181 */ 5182void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 5183{ 5184 PropValue *pv; 5185 for (pv = props; pv->prop; pv++) { 5186 if (!pv->value) { 5187 continue; 5188 } 5189 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 5190 &error_abort); 5191 } 5192} 5193 5194/* 5195 * Apply properties for the CPU model version specified in model. 5196 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5197 */ 5198 5199static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 5200{ 5201 const X86CPUVersionDefinition *vdef; 5202 X86CPUVersion version = x86_cpu_model_resolve_version(model); 5203 5204 if (version == CPU_VERSION_LEGACY) { 5205 return; 5206 } 5207 5208 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 5209 PropValue *p; 5210 5211 for (p = vdef->props; p && p->prop; p++) { 5212 object_property_parse(OBJECT(cpu), p->prop, p->value, 5213 &error_abort); 5214 } 5215 5216 if (vdef->version == version) { 5217 break; 5218 } 5219 } 5220 5221 /* 5222 * If we reached the end of the list, version number was invalid 5223 */ 5224 assert(vdef->version == version); 5225} 5226 5227/* Apply properties for the CPU model version specified in model */ 5228static const CPUCaches *x86_cpu_get_version_cache_info(X86CPU *cpu, 5229 X86CPUModel *model) 5230{ 5231 const X86CPUVersionDefinition *vdef; 5232 X86CPUVersion version = x86_cpu_model_resolve_version(model); 5233 const CPUCaches *cache_info = model->cpudef->cache_info; 5234 5235 if (version == CPU_VERSION_LEGACY) { 5236 return cache_info; 5237 } 5238 5239 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 5240 if (vdef->cache_info) { 5241 cache_info = vdef->cache_info; 5242 } 5243 5244 if (vdef->version == version) { 5245 break; 5246 } 5247 } 5248 5249 assert(vdef->version == version); 5250 return cache_info; 5251} 5252 5253/* 5254 * Load data from X86CPUDefinition into a X86CPU object. 5255 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5256 */ 5257static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 5258{ 5259 const X86CPUDefinition *def = model->cpudef; 5260 CPUX86State *env = &cpu->env; 5261 FeatureWord w; 5262 5263 /*NOTE: any property set by this function should be returned by 5264 * x86_cpu_static_props(), so static expansion of 5265 * query-cpu-model-expansion is always complete. 5266 */ 5267 5268 /* CPU models only set _minimum_ values for level/xlevel: */ 5269 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 5270 &error_abort); 5271 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 5272 &error_abort); 5273 5274 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 5275 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 5276 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 5277 &error_abort); 5278 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 5279 &error_abort); 5280 for (w = 0; w < FEATURE_WORDS; w++) { 5281 env->features[w] = def->features[w]; 5282 } 5283 5284 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 5285 cpu->legacy_cache = !x86_cpu_get_version_cache_info(cpu, model); 5286 5287 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 5288 5289 /* sysenter isn't supported in compatibility mode on AMD, 5290 * syscall isn't supported in compatibility mode on Intel. 5291 * Normally we advertise the actual CPU vendor, but you can 5292 * override this using the 'vendor' property if you want to use 5293 * KVM's sysenter/syscall emulation in compatibility mode and 5294 * when doing cross vendor migration 5295 */ 5296 5297 /* 5298 * vendor property is set here but then overloaded with the 5299 * host cpu vendor for KVM and HVF. 5300 */ 5301 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 5302 5303 x86_cpu_apply_version_props(cpu, model); 5304 5305 /* 5306 * Properties in versioned CPU model are not user specified features. 5307 * We can simply clear env->user_features here since it will be filled later 5308 * in x86_cpu_expand_features() based on plus_features and minus_features. 5309 */ 5310 memset(&env->user_features, 0, sizeof(env->user_features)); 5311} 5312 5313static gchar *x86_gdb_arch_name(CPUState *cs) 5314{ 5315#ifdef TARGET_X86_64 5316 return g_strdup("i386:x86-64"); 5317#else 5318 return g_strdup("i386"); 5319#endif 5320} 5321 5322static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 5323{ 5324 X86CPUModel *model = data; 5325 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5326 CPUClass *cc = CPU_CLASS(oc); 5327 5328 xcc->model = model; 5329 xcc->migration_safe = true; 5330 cc->deprecation_note = model->cpudef->deprecation_note; 5331} 5332 5333static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 5334{ 5335 g_autofree char *typename = x86_cpu_type_name(name); 5336 TypeInfo ti = { 5337 .name = typename, 5338 .parent = TYPE_X86_CPU, 5339 .class_init = x86_cpu_cpudef_class_init, 5340 .class_data = model, 5341 }; 5342 5343 type_register(&ti); 5344} 5345 5346 5347/* 5348 * register builtin_x86_defs; 5349 * "max", "base" and subclasses ("host") are not registered here. 5350 * See x86_cpu_register_types for all model registrations. 5351 */ 5352static void x86_register_cpudef_types(const X86CPUDefinition *def) 5353{ 5354 X86CPUModel *m; 5355 const X86CPUVersionDefinition *vdef; 5356 5357 /* AMD aliases are handled at runtime based on CPUID vendor, so 5358 * they shouldn't be set on the CPU model table. 5359 */ 5360 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 5361 /* catch mistakes instead of silently truncating model_id when too long */ 5362 assert(def->model_id && strlen(def->model_id) <= 48); 5363 5364 /* Unversioned model: */ 5365 m = g_new0(X86CPUModel, 1); 5366 m->cpudef = def; 5367 m->version = CPU_VERSION_AUTO; 5368 m->is_alias = true; 5369 x86_register_cpu_model_type(def->name, m); 5370 5371 /* Versioned models: */ 5372 5373 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 5374 X86CPUModel *m = g_new0(X86CPUModel, 1); 5375 g_autofree char *name = 5376 x86_cpu_versioned_model_name(def, vdef->version); 5377 m->cpudef = def; 5378 m->version = vdef->version; 5379 m->note = vdef->note; 5380 x86_register_cpu_model_type(name, m); 5381 5382 if (vdef->alias) { 5383 X86CPUModel *am = g_new0(X86CPUModel, 1); 5384 am->cpudef = def; 5385 am->version = vdef->version; 5386 am->is_alias = true; 5387 x86_register_cpu_model_type(vdef->alias, am); 5388 } 5389 } 5390 5391} 5392 5393uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 5394{ 5395 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 5396 return 57; /* 57 bits virtual */ 5397 } else { 5398 return 48; /* 48 bits virtual */ 5399 } 5400} 5401 5402void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 5403 uint32_t *eax, uint32_t *ebx, 5404 uint32_t *ecx, uint32_t *edx) 5405{ 5406 X86CPU *cpu = env_archcpu(env); 5407 CPUState *cs = env_cpu(env); 5408 uint32_t die_offset; 5409 uint32_t limit; 5410 uint32_t signature[3]; 5411 X86CPUTopoInfo topo_info; 5412 5413 topo_info.dies_per_pkg = env->nr_dies; 5414 topo_info.cores_per_die = cs->nr_cores; 5415 topo_info.threads_per_core = cs->nr_threads; 5416 5417 /* Calculate & apply limits for different index ranges */ 5418 if (index >= 0xC0000000) { 5419 limit = env->cpuid_xlevel2; 5420 } else if (index >= 0x80000000) { 5421 limit = env->cpuid_xlevel; 5422 } else if (index >= 0x40000000) { 5423 limit = 0x40000001; 5424 } else { 5425 limit = env->cpuid_level; 5426 } 5427 5428 if (index > limit) { 5429 /* Intel documentation states that invalid EAX input will 5430 * return the same information as EAX=cpuid_level 5431 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 5432 */ 5433 index = env->cpuid_level; 5434 } 5435 5436 switch(index) { 5437 case 0: 5438 *eax = env->cpuid_level; 5439 *ebx = env->cpuid_vendor1; 5440 *edx = env->cpuid_vendor2; 5441 *ecx = env->cpuid_vendor3; 5442 break; 5443 case 1: 5444 *eax = env->cpuid_version; 5445 *ebx = (cpu->apic_id << 24) | 5446 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 5447 *ecx = env->features[FEAT_1_ECX]; 5448 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 5449 *ecx |= CPUID_EXT_OSXSAVE; 5450 } 5451 *edx = env->features[FEAT_1_EDX]; 5452 if (cs->nr_cores * cs->nr_threads > 1) { 5453 *ebx |= (cs->nr_cores * cs->nr_threads) << 16; 5454 *edx |= CPUID_HT; 5455 } 5456 if (!cpu->enable_pmu) { 5457 *ecx &= ~CPUID_EXT_PDCM; 5458 } 5459 break; 5460 case 2: 5461 /* cache info: needed for Pentium Pro compatibility */ 5462 if (cpu->cache_info_passthrough) { 5463 host_cpuid(index, 0, eax, ebx, ecx, edx); 5464 break; 5465 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 5466 *eax = *ebx = *ecx = *edx = 0; 5467 break; 5468 } 5469 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 5470 *ebx = 0; 5471 if (!cpu->enable_l3_cache) { 5472 *ecx = 0; 5473 } else { 5474 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 5475 } 5476 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 5477 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 5478 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 5479 break; 5480 case 4: 5481 /* cache info: needed for Core compatibility */ 5482 if (cpu->cache_info_passthrough) { 5483 host_cpuid(index, count, eax, ebx, ecx, edx); 5484 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */ 5485 *eax &= ~0xFC000000; 5486 if ((*eax & 31) && cs->nr_cores > 1) { 5487 *eax |= (cs->nr_cores - 1) << 26; 5488 } 5489 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 5490 *eax = *ebx = *ecx = *edx = 0; 5491 } else { 5492 *eax = 0; 5493 switch (count) { 5494 case 0: /* L1 dcache info */ 5495 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 5496 1, cs->nr_cores, 5497 eax, ebx, ecx, edx); 5498 break; 5499 case 1: /* L1 icache info */ 5500 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 5501 1, cs->nr_cores, 5502 eax, ebx, ecx, edx); 5503 break; 5504 case 2: /* L2 cache info */ 5505 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 5506 cs->nr_threads, cs->nr_cores, 5507 eax, ebx, ecx, edx); 5508 break; 5509 case 3: /* L3 cache info */ 5510 die_offset = apicid_die_offset(&topo_info); 5511 if (cpu->enable_l3_cache) { 5512 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 5513 (1 << die_offset), cs->nr_cores, 5514 eax, ebx, ecx, edx); 5515 break; 5516 } 5517 /* fall through */ 5518 default: /* end of info */ 5519 *eax = *ebx = *ecx = *edx = 0; 5520 break; 5521 } 5522 } 5523 break; 5524 case 5: 5525 /* MONITOR/MWAIT Leaf */ 5526 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 5527 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 5528 *ecx = cpu->mwait.ecx; /* flags */ 5529 *edx = cpu->mwait.edx; /* mwait substates */ 5530 break; 5531 case 6: 5532 /* Thermal and Power Leaf */ 5533 *eax = env->features[FEAT_6_EAX]; 5534 *ebx = 0; 5535 *ecx = 0; 5536 *edx = 0; 5537 break; 5538 case 7: 5539 /* Structured Extended Feature Flags Enumeration Leaf */ 5540 if (count == 0) { 5541 /* Maximum ECX value for sub-leaves */ 5542 *eax = env->cpuid_level_func7; 5543 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 5544 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 5545 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 5546 *ecx |= CPUID_7_0_ECX_OSPKE; 5547 } 5548 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 5549 5550 /* 5551 * SGX cannot be emulated in software. If hardware does not 5552 * support enabling SGX and/or SGX flexible launch control, 5553 * then we need to update the VM's CPUID values accordingly. 5554 */ 5555 if ((*ebx & CPUID_7_0_EBX_SGX) && 5556 (!kvm_enabled() || 5557 !(kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7, 0, R_EBX) & 5558 CPUID_7_0_EBX_SGX))) { 5559 *ebx &= ~CPUID_7_0_EBX_SGX; 5560 } 5561 5562 if ((*ecx & CPUID_7_0_ECX_SGX_LC) && 5563 (!(*ebx & CPUID_7_0_EBX_SGX) || !kvm_enabled() || 5564 !(kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7, 0, R_ECX) & 5565 CPUID_7_0_ECX_SGX_LC))) { 5566 *ecx &= ~CPUID_7_0_ECX_SGX_LC; 5567 } 5568 } else if (count == 1) { 5569 *eax = env->features[FEAT_7_1_EAX]; 5570 *ebx = 0; 5571 *ecx = 0; 5572 *edx = 0; 5573 } else { 5574 *eax = 0; 5575 *ebx = 0; 5576 *ecx = 0; 5577 *edx = 0; 5578 } 5579 break; 5580 case 9: 5581 /* Direct Cache Access Information Leaf */ 5582 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 5583 *ebx = 0; 5584 *ecx = 0; 5585 *edx = 0; 5586 break; 5587 case 0xA: 5588 /* Architectural Performance Monitoring Leaf */ 5589 if (kvm_enabled() && cpu->enable_pmu) { 5590 KVMState *s = cs->kvm_state; 5591 5592 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX); 5593 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX); 5594 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX); 5595 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX); 5596 } else if (hvf_enabled() && cpu->enable_pmu) { 5597 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX); 5598 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX); 5599 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX); 5600 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX); 5601 } else { 5602 *eax = 0; 5603 *ebx = 0; 5604 *ecx = 0; 5605 *edx = 0; 5606 } 5607 break; 5608 case 0xB: 5609 /* Extended Topology Enumeration Leaf */ 5610 if (!cpu->enable_cpuid_0xb) { 5611 *eax = *ebx = *ecx = *edx = 0; 5612 break; 5613 } 5614 5615 *ecx = count & 0xff; 5616 *edx = cpu->apic_id; 5617 5618 switch (count) { 5619 case 0: 5620 *eax = apicid_core_offset(&topo_info); 5621 *ebx = cs->nr_threads; 5622 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 5623 break; 5624 case 1: 5625 *eax = apicid_pkg_offset(&topo_info); 5626 *ebx = cs->nr_cores * cs->nr_threads; 5627 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 5628 break; 5629 default: 5630 *eax = 0; 5631 *ebx = 0; 5632 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 5633 } 5634 5635 assert(!(*eax & ~0x1f)); 5636 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 5637 break; 5638 case 0x1F: 5639 /* V2 Extended Topology Enumeration Leaf */ 5640 if (env->nr_dies < 2) { 5641 *eax = *ebx = *ecx = *edx = 0; 5642 break; 5643 } 5644 5645 *ecx = count & 0xff; 5646 *edx = cpu->apic_id; 5647 switch (count) { 5648 case 0: 5649 *eax = apicid_core_offset(&topo_info); 5650 *ebx = cs->nr_threads; 5651 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 5652 break; 5653 case 1: 5654 *eax = apicid_die_offset(&topo_info); 5655 *ebx = cs->nr_cores * cs->nr_threads; 5656 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 5657 break; 5658 case 2: 5659 *eax = apicid_pkg_offset(&topo_info); 5660 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads; 5661 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; 5662 break; 5663 default: 5664 *eax = 0; 5665 *ebx = 0; 5666 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 5667 } 5668 assert(!(*eax & ~0x1f)); 5669 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 5670 break; 5671 case 0xD: { 5672 /* Processor Extended State */ 5673 *eax = 0; 5674 *ebx = 0; 5675 *ecx = 0; 5676 *edx = 0; 5677 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 5678 break; 5679 } 5680 5681 if (count == 0) { 5682 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu)); 5683 *eax = env->features[FEAT_XSAVE_COMP_LO]; 5684 *edx = env->features[FEAT_XSAVE_COMP_HI]; 5685 /* 5686 * The initial value of xcr0 and ebx == 0, On host without kvm 5687 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 5688 * even through guest update xcr0, this will crash some legacy guest 5689 * (e.g., CentOS 6), So set ebx == ecx to workaroud it. 5690 */ 5691 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0); 5692 } else if (count == 1) { 5693 *eax = env->features[FEAT_XSAVE]; 5694 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 5695 if ((x86_cpu_xsave_components(cpu) >> count) & 1) { 5696 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 5697 *eax = esa->size; 5698 *ebx = esa->offset; 5699 } 5700 } 5701 break; 5702 } 5703 case 0x12: 5704#ifndef CONFIG_USER_ONLY 5705 if (!kvm_enabled() || 5706 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 5707 *eax = *ebx = *ecx = *edx = 0; 5708 break; 5709 } 5710 5711 /* 5712 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 5713 * the EPC properties, e.g. confidentiality and integrity, from the 5714 * host's first EPC section, i.e. assume there is one EPC section or 5715 * that all EPC sections have the same security properties. 5716 */ 5717 if (count > 1) { 5718 uint64_t epc_addr, epc_size; 5719 5720 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 5721 *eax = *ebx = *ecx = *edx = 0; 5722 break; 5723 } 5724 host_cpuid(index, 2, eax, ebx, ecx, edx); 5725 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 5726 *ebx = (uint32_t)(epc_addr >> 32); 5727 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 5728 *edx = (uint32_t)(epc_size >> 32); 5729 break; 5730 } 5731 5732 /* 5733 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 5734 * and KVM, i.e. QEMU cannot emulate features to override what KVM 5735 * supports. Features can be further restricted by userspace, but not 5736 * made more permissive. 5737 */ 5738 *eax = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x12, count, R_EAX); 5739 *ebx = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x12, count, R_EBX); 5740 *ecx = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x12, count, R_ECX); 5741 *edx = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x12, count, R_EDX); 5742 5743 if (count == 0) { 5744 *eax &= env->features[FEAT_SGX_12_0_EAX]; 5745 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 5746 } else { 5747 *eax &= env->features[FEAT_SGX_12_1_EAX]; 5748 *ebx &= 0; /* ebx reserve */ 5749 *ecx &= env->features[FEAT_XSAVE_COMP_LO]; 5750 *edx &= env->features[FEAT_XSAVE_COMP_HI]; 5751 5752 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 5753 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 5754 5755 /* Access to PROVISIONKEY requires additional credentials. */ 5756 if ((*eax & (1U << 4)) && 5757 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 5758 *eax &= ~(1U << 4); 5759 } 5760 } 5761#endif 5762 break; 5763 case 0x14: { 5764 /* Intel Processor Trace Enumeration */ 5765 *eax = 0; 5766 *ebx = 0; 5767 *ecx = 0; 5768 *edx = 0; 5769 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 5770 !kvm_enabled()) { 5771 break; 5772 } 5773 5774 if (count == 0) { 5775 *eax = INTEL_PT_MAX_SUBLEAF; 5776 *ebx = INTEL_PT_MINIMAL_EBX; 5777 *ecx = INTEL_PT_MINIMAL_ECX; 5778 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 5779 *ecx |= CPUID_14_0_ECX_LIP; 5780 } 5781 } else if (count == 1) { 5782 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 5783 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 5784 } 5785 break; 5786 } 5787 case 0x40000000: 5788 /* 5789 * CPUID code in kvm_arch_init_vcpu() ignores stuff 5790 * set here, but we restrict to TCG none the less. 5791 */ 5792 if (tcg_enabled() && cpu->expose_tcg) { 5793 memcpy(signature, "TCGTCGTCGTCG", 12); 5794 *eax = 0x40000001; 5795 *ebx = signature[0]; 5796 *ecx = signature[1]; 5797 *edx = signature[2]; 5798 } else { 5799 *eax = 0; 5800 *ebx = 0; 5801 *ecx = 0; 5802 *edx = 0; 5803 } 5804 break; 5805 case 0x40000001: 5806 *eax = 0; 5807 *ebx = 0; 5808 *ecx = 0; 5809 *edx = 0; 5810 break; 5811 case 0x80000000: 5812 *eax = env->cpuid_xlevel; 5813 *ebx = env->cpuid_vendor1; 5814 *edx = env->cpuid_vendor2; 5815 *ecx = env->cpuid_vendor3; 5816 break; 5817 case 0x80000001: 5818 *eax = env->cpuid_version; 5819 *ebx = 0; 5820 *ecx = env->features[FEAT_8000_0001_ECX]; 5821 *edx = env->features[FEAT_8000_0001_EDX]; 5822 5823 /* The Linux kernel checks for the CMPLegacy bit and 5824 * discards multiple thread information if it is set. 5825 * So don't set it here for Intel to make Linux guests happy. 5826 */ 5827 if (cs->nr_cores * cs->nr_threads > 1) { 5828 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 5829 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 5830 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 5831 *ecx |= 1 << 1; /* CmpLegacy bit */ 5832 } 5833 } 5834 break; 5835 case 0x80000002: 5836 case 0x80000003: 5837 case 0x80000004: 5838 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 5839 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 5840 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 5841 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 5842 break; 5843 case 0x80000005: 5844 /* cache info (L1 cache) */ 5845 if (cpu->cache_info_passthrough) { 5846 host_cpuid(index, 0, eax, ebx, ecx, edx); 5847 break; 5848 } 5849 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 5850 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 5851 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 5852 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 5853 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 5854 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 5855 break; 5856 case 0x80000006: 5857 /* cache info (L2 cache) */ 5858 if (cpu->cache_info_passthrough) { 5859 host_cpuid(index, 0, eax, ebx, ecx, edx); 5860 break; 5861 } 5862 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 5863 (L2_DTLB_2M_ENTRIES << 16) | 5864 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 5865 (L2_ITLB_2M_ENTRIES); 5866 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 5867 (L2_DTLB_4K_ENTRIES << 16) | 5868 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 5869 (L2_ITLB_4K_ENTRIES); 5870 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 5871 cpu->enable_l3_cache ? 5872 env->cache_info_amd.l3_cache : NULL, 5873 ecx, edx); 5874 break; 5875 case 0x80000007: 5876 *eax = 0; 5877 *ebx = 0; 5878 *ecx = 0; 5879 *edx = env->features[FEAT_8000_0007_EDX]; 5880 break; 5881 case 0x80000008: 5882 /* virtual & phys address size in low 2 bytes. */ 5883 *eax = cpu->phys_bits; 5884 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5885 /* 64 bit processor */ 5886 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 5887 } 5888 *ebx = env->features[FEAT_8000_0008_EBX]; 5889 if (cs->nr_cores * cs->nr_threads > 1) { 5890 /* 5891 * Bits 15:12 is "The number of bits in the initial 5892 * Core::X86::Apic::ApicId[ApicId] value that indicate 5893 * thread ID within a package". 5894 * Bits 7:0 is "The number of threads in the package is NC+1" 5895 */ 5896 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 5897 ((cs->nr_cores * cs->nr_threads) - 1); 5898 } else { 5899 *ecx = 0; 5900 } 5901 *edx = 0; 5902 break; 5903 case 0x8000000A: 5904 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 5905 *eax = 0x00000001; /* SVM Revision */ 5906 *ebx = 0x00000010; /* nr of ASIDs */ 5907 *ecx = 0; 5908 *edx = env->features[FEAT_SVM]; /* optional features */ 5909 } else { 5910 *eax = 0; 5911 *ebx = 0; 5912 *ecx = 0; 5913 *edx = 0; 5914 } 5915 break; 5916 case 0x8000001D: 5917 *eax = 0; 5918 if (cpu->cache_info_passthrough) { 5919 host_cpuid(index, count, eax, ebx, ecx, edx); 5920 break; 5921 } 5922 switch (count) { 5923 case 0: /* L1 dcache info */ 5924 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 5925 &topo_info, eax, ebx, ecx, edx); 5926 break; 5927 case 1: /* L1 icache info */ 5928 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 5929 &topo_info, eax, ebx, ecx, edx); 5930 break; 5931 case 2: /* L2 cache info */ 5932 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 5933 &topo_info, eax, ebx, ecx, edx); 5934 break; 5935 case 3: /* L3 cache info */ 5936 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 5937 &topo_info, eax, ebx, ecx, edx); 5938 break; 5939 default: /* end of info */ 5940 *eax = *ebx = *ecx = *edx = 0; 5941 break; 5942 } 5943 break; 5944 case 0x8000001E: 5945 if (cpu->core_id <= 255) { 5946 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 5947 } else { 5948 *eax = 0; 5949 *ebx = 0; 5950 *ecx = 0; 5951 *edx = 0; 5952 } 5953 break; 5954 case 0xC0000000: 5955 *eax = env->cpuid_xlevel2; 5956 *ebx = 0; 5957 *ecx = 0; 5958 *edx = 0; 5959 break; 5960 case 0xC0000001: 5961 /* Support for VIA CPU's CPUID instruction */ 5962 *eax = env->cpuid_version; 5963 *ebx = 0; 5964 *ecx = 0; 5965 *edx = env->features[FEAT_C000_0001_EDX]; 5966 break; 5967 case 0xC0000002: 5968 case 0xC0000003: 5969 case 0xC0000004: 5970 /* Reserved for the future, and now filled with zero */ 5971 *eax = 0; 5972 *ebx = 0; 5973 *ecx = 0; 5974 *edx = 0; 5975 break; 5976 case 0x8000001F: 5977 *eax = sev_enabled() ? 0x2 : 0; 5978 *eax |= sev_es_enabled() ? 0x8 : 0; 5979 *eax |= sev_snp_enabled() ? 0x10 : 0; 5980 *ebx = sev_get_cbit_position(); 5981 *ebx |= sev_get_reduced_phys_bits() << 6; 5982 *ecx = 0; 5983 *edx = 0; 5984 break; 5985 default: 5986 /* reserved values: zero */ 5987 *eax = 0; 5988 *ebx = 0; 5989 *ecx = 0; 5990 *edx = 0; 5991 break; 5992 } 5993} 5994 5995static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 5996{ 5997#ifndef CONFIG_USER_ONLY 5998 /* Those default values are defined in Skylake HW */ 5999 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 6000 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 6001 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 6002 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 6003#endif 6004} 6005 6006static void x86_cpu_reset(DeviceState *dev) 6007{ 6008 CPUState *s = CPU(dev); 6009 X86CPU *cpu = X86_CPU(s); 6010 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); 6011 CPUX86State *env = &cpu->env; 6012 target_ulong cr4; 6013 uint64_t xcr0; 6014 int i; 6015 6016 xcc->parent_reset(dev); 6017 6018 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 6019 6020 env->old_exception = -1; 6021 6022 /* init to reset state */ 6023 env->int_ctl = 0; 6024 env->hflags2 |= HF2_GIF_MASK; 6025 env->hflags2 |= HF2_VGIF_MASK; 6026 env->hflags &= ~HF_GUEST_MASK; 6027 6028 cpu_x86_update_cr0(env, 0x60000010); 6029 env->a20_mask = ~0x0; 6030 env->smbase = 0x30000; 6031 env->msr_smi_count = 0; 6032 6033 env->idt.limit = 0xffff; 6034 env->gdt.limit = 0xffff; 6035 env->ldt.limit = 0xffff; 6036 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 6037 env->tr.limit = 0xffff; 6038 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 6039 6040 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 6041 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 6042 DESC_R_MASK | DESC_A_MASK); 6043 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 6044 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6045 DESC_A_MASK); 6046 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 6047 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6048 DESC_A_MASK); 6049 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 6050 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6051 DESC_A_MASK); 6052 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 6053 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6054 DESC_A_MASK); 6055 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 6056 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6057 DESC_A_MASK); 6058 6059 env->eip = 0xfff0; 6060 env->regs[R_EDX] = env->cpuid_version; 6061 6062 env->eflags = 0x2; 6063 6064 /* FPU init */ 6065 for (i = 0; i < 8; i++) { 6066 env->fptags[i] = 1; 6067 } 6068 cpu_set_fpuc(env, 0x37f); 6069 6070 env->mxcsr = 0x1f80; 6071 /* All units are in INIT state. */ 6072 env->xstate_bv = 0; 6073 6074 env->pat = 0x0007040600070406ULL; 6075 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 6076 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 6077 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 6078 } 6079 6080 memset(env->dr, 0, sizeof(env->dr)); 6081 env->dr[6] = DR6_FIXED_1; 6082 env->dr[7] = DR7_FIXED_1; 6083 cpu_breakpoint_remove_all(s, BP_CPU); 6084 cpu_watchpoint_remove_all(s, BP_CPU); 6085 6086 cr4 = 0; 6087 xcr0 = XSTATE_FP_MASK; 6088 6089#ifdef CONFIG_USER_ONLY 6090 /* Enable all the features for user-mode. */ 6091 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 6092 xcr0 |= XSTATE_SSE_MASK; 6093 } 6094 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6095 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6096 if (env->features[esa->feature] & esa->bits) { 6097 xcr0 |= 1ull << i; 6098 } 6099 } 6100 6101 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 6102 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 6103 } 6104 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 6105 cr4 |= CR4_FSGSBASE_MASK; 6106 } 6107#endif 6108 6109 env->xcr0 = xcr0; 6110 cpu_x86_update_cr4(env, cr4); 6111 6112 /* 6113 * SDM 11.11.5 requires: 6114 * - IA32_MTRR_DEF_TYPE MSR.E = 0 6115 * - IA32_MTRR_PHYSMASKn.V = 0 6116 * All other bits are undefined. For simplification, zero it all. 6117 */ 6118 env->mtrr_deftype = 0; 6119 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 6120 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 6121 6122 env->interrupt_injected = -1; 6123 env->exception_nr = -1; 6124 env->exception_pending = 0; 6125 env->exception_injected = 0; 6126 env->exception_has_payload = false; 6127 env->exception_payload = 0; 6128 env->nmi_injected = false; 6129#if !defined(CONFIG_USER_ONLY) 6130 /* We hard-wire the BSP to the first CPU. */ 6131 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0); 6132 6133 s->halted = !cpu_is_bsp(cpu); 6134 6135 if (kvm_enabled()) { 6136 kvm_arch_reset_vcpu(cpu); 6137 } 6138 6139 x86_cpu_set_sgxlepubkeyhash(env); 6140#endif 6141} 6142 6143static void mce_init(X86CPU *cpu) 6144{ 6145 CPUX86State *cenv = &cpu->env; 6146 unsigned int bank; 6147 6148 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 6149 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 6150 (CPUID_MCE | CPUID_MCA)) { 6151 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 6152 (cpu->enable_lmce ? MCG_LMCE_P : 0); 6153 cenv->mcg_ctl = ~(uint64_t)0; 6154 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 6155 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 6156 } 6157 } 6158} 6159 6160static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 6161{ 6162 if (*min < value) { 6163 *min = value; 6164 } 6165} 6166 6167/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 6168static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 6169{ 6170 CPUX86State *env = &cpu->env; 6171 FeatureWordInfo *fi = &feature_word_info[w]; 6172 uint32_t eax = fi->cpuid.eax; 6173 uint32_t region = eax & 0xF0000000; 6174 6175 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 6176 if (!env->features[w]) { 6177 return; 6178 } 6179 6180 switch (region) { 6181 case 0x00000000: 6182 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 6183 break; 6184 case 0x80000000: 6185 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 6186 break; 6187 case 0xC0000000: 6188 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 6189 break; 6190 } 6191 6192 if (eax == 7) { 6193 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 6194 fi->cpuid.ecx); 6195 } 6196} 6197 6198/* Calculate XSAVE components based on the configured CPU feature flags */ 6199static void x86_cpu_enable_xsave_components(X86CPU *cpu) 6200{ 6201 CPUX86State *env = &cpu->env; 6202 int i; 6203 uint64_t mask; 6204 6205 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6206 env->features[FEAT_XSAVE_COMP_LO] = 0; 6207 env->features[FEAT_XSAVE_COMP_HI] = 0; 6208 return; 6209 } 6210 6211 mask = 0; 6212 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6213 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6214 if (env->features[esa->feature] & esa->bits) { 6215 mask |= (1ULL << i); 6216 } 6217 } 6218 6219 env->features[FEAT_XSAVE_COMP_LO] = mask; 6220 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32; 6221} 6222 6223/***** Steps involved on loading and filtering CPUID data 6224 * 6225 * When initializing and realizing a CPU object, the steps 6226 * involved in setting up CPUID data are: 6227 * 6228 * 1) Loading CPU model definition (X86CPUDefinition). This is 6229 * implemented by x86_cpu_load_model() and should be completely 6230 * transparent, as it is done automatically by instance_init. 6231 * No code should need to look at X86CPUDefinition structs 6232 * outside instance_init. 6233 * 6234 * 2) CPU expansion. This is done by realize before CPUID 6235 * filtering, and will make sure host/accelerator data is 6236 * loaded for CPU models that depend on host capabilities 6237 * (e.g. "host"). Done by x86_cpu_expand_features(). 6238 * 6239 * 3) CPUID filtering. This initializes extra data related to 6240 * CPUID, and checks if the host supports all capabilities 6241 * required by the CPU. Runnability of a CPU model is 6242 * determined at this step. Done by x86_cpu_filter_features(). 6243 * 6244 * Some operations don't require all steps to be performed. 6245 * More precisely: 6246 * 6247 * - CPU instance creation (instance_init) will run only CPU 6248 * model loading. CPU expansion can't run at instance_init-time 6249 * because host/accelerator data may be not available yet. 6250 * - CPU realization will perform both CPU model expansion and CPUID 6251 * filtering, and return an error in case one of them fails. 6252 * - query-cpu-definitions needs to run all 3 steps. It needs 6253 * to run CPUID filtering, as the 'unavailable-features' 6254 * field is set based on the filtering results. 6255 * - The query-cpu-model-expansion QMP command only needs to run 6256 * CPU model loading and CPU expansion. It should not filter 6257 * any CPUID data based on host capabilities. 6258 */ 6259 6260/* Expand CPU configuration data, based on configured features 6261 * and host/accelerator capabilities when appropriate. 6262 */ 6263void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 6264{ 6265 CPUX86State *env = &cpu->env; 6266 FeatureWord w; 6267 int i; 6268 GList *l; 6269 6270 for (l = plus_features; l; l = l->next) { 6271 const char *prop = l->data; 6272 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 6273 return; 6274 } 6275 } 6276 6277 for (l = minus_features; l; l = l->next) { 6278 const char *prop = l->data; 6279 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 6280 return; 6281 } 6282 } 6283 6284 /*TODO: Now cpu->max_features doesn't overwrite features 6285 * set using QOM properties, and we can convert 6286 * plus_features & minus_features to global properties 6287 * inside x86_cpu_parse_featurestr() too. 6288 */ 6289 if (cpu->max_features) { 6290 for (w = 0; w < FEATURE_WORDS; w++) { 6291 /* Override only features that weren't set explicitly 6292 * by the user. 6293 */ 6294 env->features[w] |= 6295 x86_cpu_get_supported_feature_word(w, cpu->migratable) & 6296 ~env->user_features[w] & 6297 ~feature_word_info[w].no_autoenable_flags; 6298 } 6299 } 6300 6301 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 6302 FeatureDep *d = &feature_dependencies[i]; 6303 if (!(env->features[d->from.index] & d->from.mask)) { 6304 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 6305 6306 /* Not an error unless the dependent feature was added explicitly. */ 6307 mark_unavailable_features(cpu, d->to.index, 6308 unavailable_features & env->user_features[d->to.index], 6309 "This feature depends on other features that were not requested"); 6310 6311 env->features[d->to.index] &= ~unavailable_features; 6312 } 6313 } 6314 6315 if (!kvm_enabled() || !cpu->expose_kvm) { 6316 env->features[FEAT_KVM] = 0; 6317 } 6318 6319 x86_cpu_enable_xsave_components(cpu); 6320 6321 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 6322 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 6323 if (cpu->full_cpuid_auto_level) { 6324 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 6325 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 6326 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 6327 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 6328 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 6329 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 6330 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 6331 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 6332 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 6333 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 6334 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 6335 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 6336 6337 /* Intel Processor Trace requires CPUID[0x14] */ 6338 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 6339 if (cpu->intel_pt_auto_level) { 6340 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 6341 } else if (cpu->env.cpuid_min_level < 0x14) { 6342 mark_unavailable_features(cpu, FEAT_7_0_EBX, 6343 CPUID_7_0_EBX_INTEL_PT, 6344 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 6345 } 6346 } 6347 6348 /* 6349 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 6350 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 6351 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 6352 * cpu->vendor_cpuid_only has been unset for compatibility with older 6353 * machine types. 6354 */ 6355 if ((env->nr_dies > 1) && 6356 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 6357 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 6358 } 6359 6360 /* SVM requires CPUID[0x8000000A] */ 6361 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6362 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 6363 } 6364 6365 /* SEV requires CPUID[0x8000001F] */ 6366 if (sev_enabled()) { 6367 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 6368 } 6369 6370 /* SGX requires CPUID[0x12] for EPC enumeration */ 6371 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 6372 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 6373 } 6374 } 6375 6376 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 6377 if (env->cpuid_level_func7 == UINT32_MAX) { 6378 env->cpuid_level_func7 = env->cpuid_min_level_func7; 6379 } 6380 if (env->cpuid_level == UINT32_MAX) { 6381 env->cpuid_level = env->cpuid_min_level; 6382 } 6383 if (env->cpuid_xlevel == UINT32_MAX) { 6384 env->cpuid_xlevel = env->cpuid_min_xlevel; 6385 } 6386 if (env->cpuid_xlevel2 == UINT32_MAX) { 6387 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 6388 } 6389 6390 if (kvm_enabled()) { 6391 kvm_hyperv_expand_features(cpu, errp); 6392 } 6393} 6394 6395/* 6396 * Finishes initialization of CPUID data, filters CPU feature 6397 * words based on host availability of each feature. 6398 * 6399 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 6400 */ 6401static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 6402{ 6403 CPUX86State *env = &cpu->env; 6404 FeatureWord w; 6405 const char *prefix = NULL; 6406 6407 if (verbose) { 6408 prefix = accel_uses_host_cpuid() 6409 ? "host doesn't support requested feature" 6410 : "TCG doesn't support requested feature"; 6411 } 6412 6413 for (w = 0; w < FEATURE_WORDS; w++) { 6414 uint64_t host_feat = 6415 x86_cpu_get_supported_feature_word(w, false); 6416 uint64_t requested_features = env->features[w]; 6417 uint64_t unavailable_features = requested_features & ~host_feat; 6418 mark_unavailable_features(cpu, w, unavailable_features, prefix); 6419 } 6420 6421 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 6422 kvm_enabled()) { 6423 KVMState *s = CPU(cpu)->kvm_state; 6424 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX); 6425 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX); 6426 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX); 6427 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX); 6428 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX); 6429 6430 if (!eax_0 || 6431 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 6432 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 6433 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 6434 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 6435 INTEL_PT_ADDR_RANGES_NUM) || 6436 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 6437 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 6438 ((ecx_0 & CPUID_14_0_ECX_LIP) != 6439 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 6440 /* 6441 * Processor Trace capabilities aren't configurable, so if the 6442 * host can't emulate the capabilities we report on 6443 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 6444 */ 6445 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 6446 } 6447 } 6448} 6449 6450static void x86_cpu_hyperv_realize(X86CPU *cpu) 6451{ 6452 size_t len; 6453 6454 /* Hyper-V vendor id */ 6455 if (!cpu->hyperv_vendor) { 6456 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 6457 &error_abort); 6458 } 6459 len = strlen(cpu->hyperv_vendor); 6460 if (len > 12) { 6461 warn_report("hv-vendor-id truncated to 12 characters"); 6462 len = 12; 6463 } 6464 memset(cpu->hyperv_vendor_id, 0, 12); 6465 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 6466 6467 /* 'Hv#1' interface identification*/ 6468 cpu->hyperv_interface_id[0] = 0x31237648; 6469 cpu->hyperv_interface_id[1] = 0; 6470 cpu->hyperv_interface_id[2] = 0; 6471 cpu->hyperv_interface_id[3] = 0; 6472 6473 /* Hypervisor implementation limits */ 6474 cpu->hyperv_limits[0] = 64; 6475 cpu->hyperv_limits[1] = 0; 6476 cpu->hyperv_limits[2] = 0; 6477} 6478 6479static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 6480{ 6481 CPUState *cs = CPU(dev); 6482 X86CPU *cpu = X86_CPU(dev); 6483 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 6484 CPUX86State *env = &cpu->env; 6485 Error *local_err = NULL; 6486 static bool ht_warned; 6487 6488 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 6489 error_setg(errp, "apic-id property was not initialized properly"); 6490 return; 6491 } 6492 6493 /* 6494 * Process Hyper-V enlightenments. 6495 * Note: this currently has to happen before the expansion of CPU features. 6496 */ 6497 x86_cpu_hyperv_realize(cpu); 6498 6499 x86_cpu_expand_features(cpu, &local_err); 6500 if (local_err) { 6501 goto out; 6502 } 6503 6504 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 6505 6506 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 6507 error_setg(&local_err, 6508 accel_uses_host_cpuid() ? 6509 "Host doesn't support requested features" : 6510 "TCG doesn't support requested features"); 6511 goto out; 6512 } 6513 6514 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 6515 * CPUID[1].EDX. 6516 */ 6517 if (IS_AMD_CPU(env)) { 6518 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 6519 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 6520 & CPUID_EXT2_AMD_ALIASES); 6521 } 6522 6523 x86_cpu_set_sgxlepubkeyhash(env); 6524 6525 /* 6526 * note: the call to the framework needs to happen after feature expansion, 6527 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 6528 * These may be set by the accel-specific code, 6529 * and the results are subsequently checked / assumed in this function. 6530 */ 6531 cpu_exec_realizefn(cs, &local_err); 6532 if (local_err != NULL) { 6533 error_propagate(errp, local_err); 6534 return; 6535 } 6536 6537 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 6538 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 6539 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 6540 goto out; 6541 } 6542 6543 if (cpu->ucode_rev == 0) { 6544 /* 6545 * The default is the same as KVM's. Note that this check 6546 * needs to happen after the evenual setting of ucode_rev in 6547 * accel-specific code in cpu_exec_realizefn. 6548 */ 6549 if (IS_AMD_CPU(env)) { 6550 cpu->ucode_rev = 0x01000065; 6551 } else { 6552 cpu->ucode_rev = 0x100000000ULL; 6553 } 6554 } 6555 6556 /* 6557 * mwait extended info: needed for Core compatibility 6558 * We always wake on interrupt even if host does not have the capability. 6559 * 6560 * requires the accel-specific code in cpu_exec_realizefn to 6561 * have already acquired the CPUID data into cpu->mwait. 6562 */ 6563 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 6564 6565 /* For 64bit systems think about the number of physical bits to present. 6566 * ideally this should be the same as the host; anything other than matching 6567 * the host can cause incorrect guest behaviour. 6568 * QEMU used to pick the magic value of 40 bits that corresponds to 6569 * consumer AMD devices but nothing else. 6570 * 6571 * Note that this code assumes features expansion has already been done 6572 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 6573 * phys_bits adjustments to match the host have been already done in 6574 * accel-specific code in cpu_exec_realizefn. 6575 */ 6576 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6577 if (cpu->phys_bits && 6578 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 6579 cpu->phys_bits < 32)) { 6580 error_setg(errp, "phys-bits should be between 32 and %u " 6581 " (but is %u)", 6582 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 6583 return; 6584 } 6585 /* 6586 * 0 means it was not explicitly set by the user (or by machine 6587 * compat_props or by the host code in host-cpu.c). 6588 * In this case, the default is the value used by TCG (40). 6589 */ 6590 if (cpu->phys_bits == 0) { 6591 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 6592 } 6593 } else { 6594 /* For 32 bit systems don't use the user set value, but keep 6595 * phys_bits consistent with what we tell the guest. 6596 */ 6597 if (cpu->phys_bits != 0) { 6598 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 6599 return; 6600 } 6601 6602 if (env->features[FEAT_1_EDX] & CPUID_PSE36) { 6603 cpu->phys_bits = 36; 6604 } else { 6605 cpu->phys_bits = 32; 6606 } 6607 } 6608 6609 /* Cache information initialization */ 6610 if (!cpu->legacy_cache) { 6611 const CPUCaches *cache_info = 6612 x86_cpu_get_version_cache_info(cpu, xcc->model); 6613 6614 if (!xcc->model || !cache_info) { 6615 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 6616 error_setg(errp, 6617 "CPU model '%s' doesn't support legacy-cache=off", name); 6618 return; 6619 } 6620 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 6621 *cache_info; 6622 } else { 6623 /* Build legacy cache information */ 6624 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 6625 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 6626 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 6627 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 6628 6629 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 6630 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 6631 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 6632 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 6633 6634 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 6635 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 6636 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 6637 env->cache_info_amd.l3_cache = &legacy_l3_cache; 6638 } 6639 6640#ifndef CONFIG_USER_ONLY 6641 MachineState *ms = MACHINE(qdev_get_machine()); 6642 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 6643 6644 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 6645 x86_cpu_apic_create(cpu, &local_err); 6646 if (local_err != NULL) { 6647 goto out; 6648 } 6649 } 6650#endif 6651 6652 mce_init(cpu); 6653 6654 qemu_init_vcpu(cs); 6655 6656 /* 6657 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 6658 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 6659 * based on inputs (sockets,cores,threads), it is still better to give 6660 * users a warning. 6661 * 6662 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 6663 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 6664 */ 6665 if (IS_AMD_CPU(env) && 6666 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 6667 cs->nr_threads > 1 && !ht_warned) { 6668 warn_report("This family of AMD CPU doesn't support " 6669 "hyperthreading(%d)", 6670 cs->nr_threads); 6671 error_printf("Please configure -smp options properly" 6672 " or try enabling topoext feature.\n"); 6673 ht_warned = true; 6674 } 6675 6676#ifndef CONFIG_USER_ONLY 6677 x86_cpu_apic_realize(cpu, &local_err); 6678 if (local_err != NULL) { 6679 goto out; 6680 } 6681#endif /* !CONFIG_USER_ONLY */ 6682 cpu_reset(cs); 6683 6684 xcc->parent_realize(dev, &local_err); 6685 6686out: 6687 if (local_err != NULL) { 6688 error_propagate(errp, local_err); 6689 return; 6690 } 6691} 6692 6693static void x86_cpu_unrealizefn(DeviceState *dev) 6694{ 6695 X86CPU *cpu = X86_CPU(dev); 6696 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 6697 6698#ifndef CONFIG_USER_ONLY 6699 cpu_remove_sync(CPU(dev)); 6700 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 6701#endif 6702 6703 if (cpu->apic_state) { 6704 object_unparent(OBJECT(cpu->apic_state)); 6705 cpu->apic_state = NULL; 6706 } 6707 6708 xcc->parent_unrealize(dev); 6709} 6710 6711typedef struct BitProperty { 6712 FeatureWord w; 6713 uint64_t mask; 6714} BitProperty; 6715 6716static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 6717 void *opaque, Error **errp) 6718{ 6719 X86CPU *cpu = X86_CPU(obj); 6720 BitProperty *fp = opaque; 6721 uint64_t f = cpu->env.features[fp->w]; 6722 bool value = (f & fp->mask) == fp->mask; 6723 visit_type_bool(v, name, &value, errp); 6724} 6725 6726static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 6727 void *opaque, Error **errp) 6728{ 6729 DeviceState *dev = DEVICE(obj); 6730 X86CPU *cpu = X86_CPU(obj); 6731 BitProperty *fp = opaque; 6732 bool value; 6733 6734 if (dev->realized) { 6735 qdev_prop_set_after_realize(dev, name, errp); 6736 return; 6737 } 6738 6739 if (!visit_type_bool(v, name, &value, errp)) { 6740 return; 6741 } 6742 6743 if (value) { 6744 cpu->env.features[fp->w] |= fp->mask; 6745 } else { 6746 cpu->env.features[fp->w] &= ~fp->mask; 6747 } 6748 cpu->env.user_features[fp->w] |= fp->mask; 6749} 6750 6751/* Register a boolean property to get/set a single bit in a uint32_t field. 6752 * 6753 * The same property name can be registered multiple times to make it affect 6754 * multiple bits in the same FeatureWord. In that case, the getter will return 6755 * true only if all bits are set. 6756 */ 6757static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 6758 const char *prop_name, 6759 FeatureWord w, 6760 int bitnr) 6761{ 6762 ObjectClass *oc = OBJECT_CLASS(xcc); 6763 BitProperty *fp; 6764 ObjectProperty *op; 6765 uint64_t mask = (1ULL << bitnr); 6766 6767 op = object_class_property_find(oc, prop_name); 6768 if (op) { 6769 fp = op->opaque; 6770 assert(fp->w == w); 6771 fp->mask |= mask; 6772 } else { 6773 fp = g_new0(BitProperty, 1); 6774 fp->w = w; 6775 fp->mask = mask; 6776 object_class_property_add(oc, prop_name, "bool", 6777 x86_cpu_get_bit_prop, 6778 x86_cpu_set_bit_prop, 6779 NULL, fp); 6780 } 6781} 6782 6783static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 6784 FeatureWord w, 6785 int bitnr) 6786{ 6787 FeatureWordInfo *fi = &feature_word_info[w]; 6788 const char *name = fi->feat_names[bitnr]; 6789 6790 if (!name) { 6791 return; 6792 } 6793 6794 /* Property names should use "-" instead of "_". 6795 * Old names containing underscores are registered as aliases 6796 * using object_property_add_alias() 6797 */ 6798 assert(!strchr(name, '_')); 6799 /* aliases don't use "|" delimiters anymore, they are registered 6800 * manually using object_property_add_alias() */ 6801 assert(!strchr(name, '|')); 6802 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 6803} 6804 6805static void x86_cpu_post_initfn(Object *obj) 6806{ 6807 accel_cpu_instance_init(CPU(obj)); 6808} 6809 6810static void x86_cpu_initfn(Object *obj) 6811{ 6812 X86CPU *cpu = X86_CPU(obj); 6813 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 6814 CPUX86State *env = &cpu->env; 6815 6816 env->nr_dies = 1; 6817 cpu_set_cpustate_pointers(cpu); 6818 6819 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 6820 x86_cpu_get_feature_words, 6821 NULL, NULL, (void *)env->features); 6822 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 6823 x86_cpu_get_feature_words, 6824 NULL, NULL, (void *)cpu->filtered_features); 6825 6826 object_property_add_alias(obj, "sse3", obj, "pni"); 6827 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 6828 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 6829 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 6830 object_property_add_alias(obj, "xd", obj, "nx"); 6831 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 6832 object_property_add_alias(obj, "i64", obj, "lm"); 6833 6834 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 6835 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 6836 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 6837 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 6838 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 6839 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 6840 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 6841 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 6842 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 6843 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 6844 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 6845 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 6846 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 6847 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 6848 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 6849 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 6850 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 6851 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 6852 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 6853 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 6854 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 6855 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 6856 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 6857 6858 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 6859 6860 if (xcc->model) { 6861 x86_cpu_load_model(cpu, xcc->model); 6862 } 6863} 6864 6865static int64_t x86_cpu_get_arch_id(CPUState *cs) 6866{ 6867 X86CPU *cpu = X86_CPU(cs); 6868 6869 return cpu->apic_id; 6870} 6871 6872#if !defined(CONFIG_USER_ONLY) 6873static bool x86_cpu_get_paging_enabled(const CPUState *cs) 6874{ 6875 X86CPU *cpu = X86_CPU(cs); 6876 6877 return cpu->env.cr[0] & CR0_PG_MASK; 6878} 6879#endif /* !CONFIG_USER_ONLY */ 6880 6881static void x86_cpu_set_pc(CPUState *cs, vaddr value) 6882{ 6883 X86CPU *cpu = X86_CPU(cs); 6884 6885 cpu->env.eip = value; 6886} 6887 6888int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 6889{ 6890 X86CPU *cpu = X86_CPU(cs); 6891 CPUX86State *env = &cpu->env; 6892 6893#if !defined(CONFIG_USER_ONLY) 6894 if (interrupt_request & CPU_INTERRUPT_POLL) { 6895 return CPU_INTERRUPT_POLL; 6896 } 6897#endif 6898 if (interrupt_request & CPU_INTERRUPT_SIPI) { 6899 return CPU_INTERRUPT_SIPI; 6900 } 6901 6902 if (env->hflags2 & HF2_GIF_MASK) { 6903 if ((interrupt_request & CPU_INTERRUPT_SMI) && 6904 !(env->hflags & HF_SMM_MASK)) { 6905 return CPU_INTERRUPT_SMI; 6906 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 6907 !(env->hflags2 & HF2_NMI_MASK)) { 6908 return CPU_INTERRUPT_NMI; 6909 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 6910 return CPU_INTERRUPT_MCE; 6911 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 6912 (((env->hflags2 & HF2_VINTR_MASK) && 6913 (env->hflags2 & HF2_HIF_MASK)) || 6914 (!(env->hflags2 & HF2_VINTR_MASK) && 6915 (env->eflags & IF_MASK && 6916 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 6917 return CPU_INTERRUPT_HARD; 6918#if !defined(CONFIG_USER_ONLY) 6919 } else if (env->hflags2 & HF2_VGIF_MASK) { 6920 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 6921 (env->eflags & IF_MASK) && 6922 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 6923 return CPU_INTERRUPT_VIRQ; 6924 } 6925#endif 6926 } 6927 } 6928 6929 return 0; 6930} 6931 6932static bool x86_cpu_has_work(CPUState *cs) 6933{ 6934 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 6935} 6936 6937static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 6938{ 6939 X86CPU *cpu = X86_CPU(cs); 6940 CPUX86State *env = &cpu->env; 6941 6942 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 6943 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 6944 : bfd_mach_i386_i8086); 6945 info->print_insn = print_insn_i386; 6946 6947 info->cap_arch = CS_ARCH_X86; 6948 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 6949 : env->hflags & HF_CS32_MASK ? CS_MODE_32 6950 : CS_MODE_16); 6951 info->cap_insn_unit = 1; 6952 info->cap_insn_split = 8; 6953} 6954 6955void x86_update_hflags(CPUX86State *env) 6956{ 6957 uint32_t hflags; 6958#define HFLAG_COPY_MASK \ 6959 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 6960 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 6961 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 6962 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 6963 6964 hflags = env->hflags & HFLAG_COPY_MASK; 6965 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 6966 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 6967 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 6968 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 6969 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 6970 6971 if (env->cr[4] & CR4_OSFXSR_MASK) { 6972 hflags |= HF_OSFXSR_MASK; 6973 } 6974 6975 if (env->efer & MSR_EFER_LMA) { 6976 hflags |= HF_LMA_MASK; 6977 } 6978 6979 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 6980 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 6981 } else { 6982 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 6983 (DESC_B_SHIFT - HF_CS32_SHIFT); 6984 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 6985 (DESC_B_SHIFT - HF_SS32_SHIFT); 6986 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 6987 !(hflags & HF_CS32_MASK)) { 6988 hflags |= HF_ADDSEG_MASK; 6989 } else { 6990 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 6991 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 6992 } 6993 } 6994 env->hflags = hflags; 6995} 6996 6997static Property x86_cpu_properties[] = { 6998#ifdef CONFIG_USER_ONLY 6999 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 7000 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 7001 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 7002 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 7003 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 7004 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 7005#else 7006 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 7007 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 7008 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 7009 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 7010 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 7011#endif 7012 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 7013 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 7014 7015 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 7016 HYPERV_SPINLOCK_NEVER_NOTIFY), 7017 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 7018 HYPERV_FEAT_RELAXED, 0), 7019 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 7020 HYPERV_FEAT_VAPIC, 0), 7021 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 7022 HYPERV_FEAT_TIME, 0), 7023 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 7024 HYPERV_FEAT_CRASH, 0), 7025 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 7026 HYPERV_FEAT_RESET, 0), 7027 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 7028 HYPERV_FEAT_VPINDEX, 0), 7029 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 7030 HYPERV_FEAT_RUNTIME, 0), 7031 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 7032 HYPERV_FEAT_SYNIC, 0), 7033 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 7034 HYPERV_FEAT_STIMER, 0), 7035 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 7036 HYPERV_FEAT_FREQUENCIES, 0), 7037 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 7038 HYPERV_FEAT_REENLIGHTENMENT, 0), 7039 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 7040 HYPERV_FEAT_TLBFLUSH, 0), 7041 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 7042 HYPERV_FEAT_EVMCS, 0), 7043 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 7044 HYPERV_FEAT_IPI, 0), 7045 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 7046 HYPERV_FEAT_STIMER_DIRECT, 0), 7047 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 7048 HYPERV_FEAT_AVIC, 0), 7049 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 7050 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 7051 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 7052 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 7053 7054 /* WS2008R2 identify by default */ 7055 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 7056 0x3839), 7057 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 7058 0x000A), 7059 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 7060 0x0000), 7061 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 7062 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 7063 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 7064 7065 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 7066 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 7067 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 7068 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 7069 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 7070 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 7071 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 7072 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 7073 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 7074 UINT32_MAX), 7075 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 7076 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 7077 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 7078 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 7079 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 7080 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 7081 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 7082 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 7083 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 7084 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 7085 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 7086 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 7087 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 7088 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, 7089 false), 7090 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 7091 false), 7092 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 7093 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 7094 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 7095 true), 7096 /* 7097 * lecacy_cache defaults to true unless the CPU model provides its 7098 * own cache information (see x86_cpu_load_def()). 7099 */ 7100 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 7101 7102 /* 7103 * From "Requirements for Implementing the Microsoft 7104 * Hypervisor Interface": 7105 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7106 * 7107 * "Starting with Windows Server 2012 and Windows 8, if 7108 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 7109 * the hypervisor imposes no specific limit to the number of VPs. 7110 * In this case, Windows Server 2012 guest VMs may use more than 7111 * 64 VPs, up to the maximum supported number of processors applicable 7112 * to the specific Windows version being used." 7113 */ 7114 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 7115 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 7116 false), 7117 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 7118 true), 7119 DEFINE_PROP_END_OF_LIST() 7120}; 7121 7122#ifndef CONFIG_USER_ONLY 7123#include "hw/core/sysemu-cpu-ops.h" 7124 7125static const struct SysemuCPUOps i386_sysemu_ops = { 7126 .get_memory_mapping = x86_cpu_get_memory_mapping, 7127 .get_paging_enabled = x86_cpu_get_paging_enabled, 7128 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 7129 .asidx_from_attrs = x86_asidx_from_attrs, 7130 .get_crash_info = x86_cpu_get_crash_info, 7131 .write_elf32_note = x86_cpu_write_elf32_note, 7132 .write_elf64_note = x86_cpu_write_elf64_note, 7133 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 7134 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 7135 .legacy_vmsd = &vmstate_x86_cpu, 7136}; 7137#endif 7138 7139static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 7140{ 7141 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7142 CPUClass *cc = CPU_CLASS(oc); 7143 DeviceClass *dc = DEVICE_CLASS(oc); 7144 FeatureWord w; 7145 7146 device_class_set_parent_realize(dc, x86_cpu_realizefn, 7147 &xcc->parent_realize); 7148 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 7149 &xcc->parent_unrealize); 7150 device_class_set_props(dc, x86_cpu_properties); 7151 7152 device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset); 7153 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 7154 7155 cc->class_by_name = x86_cpu_class_by_name; 7156 cc->parse_features = x86_cpu_parse_featurestr; 7157 cc->has_work = x86_cpu_has_work; 7158 cc->dump_state = x86_cpu_dump_state; 7159 cc->set_pc = x86_cpu_set_pc; 7160 cc->gdb_read_register = x86_cpu_gdb_read_register; 7161 cc->gdb_write_register = x86_cpu_gdb_write_register; 7162 cc->get_arch_id = x86_cpu_get_arch_id; 7163 7164#ifndef CONFIG_USER_ONLY 7165 cc->sysemu_ops = &i386_sysemu_ops; 7166#endif /* !CONFIG_USER_ONLY */ 7167 7168 cc->gdb_arch_name = x86_gdb_arch_name; 7169#ifdef TARGET_X86_64 7170 cc->gdb_core_xml_file = "i386-64bit.xml"; 7171 cc->gdb_num_core_regs = 66; 7172#else 7173 cc->gdb_core_xml_file = "i386-32bit.xml"; 7174 cc->gdb_num_core_regs = 50; 7175#endif 7176 cc->disas_set_info = x86_disas_set_info; 7177 7178 dc->user_creatable = true; 7179 7180 object_class_property_add(oc, "family", "int", 7181 x86_cpuid_version_get_family, 7182 x86_cpuid_version_set_family, NULL, NULL); 7183 object_class_property_add(oc, "model", "int", 7184 x86_cpuid_version_get_model, 7185 x86_cpuid_version_set_model, NULL, NULL); 7186 object_class_property_add(oc, "stepping", "int", 7187 x86_cpuid_version_get_stepping, 7188 x86_cpuid_version_set_stepping, NULL, NULL); 7189 object_class_property_add_str(oc, "vendor", 7190 x86_cpuid_get_vendor, 7191 x86_cpuid_set_vendor); 7192 object_class_property_add_str(oc, "model-id", 7193 x86_cpuid_get_model_id, 7194 x86_cpuid_set_model_id); 7195 object_class_property_add(oc, "tsc-frequency", "int", 7196 x86_cpuid_get_tsc_freq, 7197 x86_cpuid_set_tsc_freq, NULL, NULL); 7198 /* 7199 * The "unavailable-features" property has the same semantics as 7200 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 7201 * QMP command: they list the features that would have prevented the 7202 * CPU from running if the "enforce" flag was set. 7203 */ 7204 object_class_property_add(oc, "unavailable-features", "strList", 7205 x86_cpu_get_unavailable_features, 7206 NULL, NULL, NULL); 7207 7208#if !defined(CONFIG_USER_ONLY) 7209 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 7210 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 7211#endif 7212 7213 for (w = 0; w < FEATURE_WORDS; w++) { 7214 int bitnr; 7215 for (bitnr = 0; bitnr < 64; bitnr++) { 7216 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 7217 } 7218 } 7219} 7220 7221static const TypeInfo x86_cpu_type_info = { 7222 .name = TYPE_X86_CPU, 7223 .parent = TYPE_CPU, 7224 .instance_size = sizeof(X86CPU), 7225 .instance_init = x86_cpu_initfn, 7226 .instance_post_init = x86_cpu_post_initfn, 7227 7228 .abstract = true, 7229 .class_size = sizeof(X86CPUClass), 7230 .class_init = x86_cpu_common_class_init, 7231}; 7232 7233/* "base" CPU model, used by query-cpu-model-expansion */ 7234static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 7235{ 7236 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7237 7238 xcc->static_model = true; 7239 xcc->migration_safe = true; 7240 xcc->model_description = "base CPU model type with no features enabled"; 7241 xcc->ordering = 8; 7242} 7243 7244static const TypeInfo x86_base_cpu_type_info = { 7245 .name = X86_CPU_TYPE_NAME("base"), 7246 .parent = TYPE_X86_CPU, 7247 .class_init = x86_cpu_base_class_init, 7248}; 7249 7250static void x86_cpu_register_types(void) 7251{ 7252 int i; 7253 7254 type_register_static(&x86_cpu_type_info); 7255 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 7256 x86_register_cpudef_types(&builtin_x86_defs[i]); 7257 } 7258 type_register_static(&max_x86_cpu_type_info); 7259 type_register_static(&x86_base_cpu_type_info); 7260} 7261 7262type_init(x86_cpu_register_types)