cpu.h (19141B)
1/* 2 * m68k virtual CPU header 3 * 4 * Copyright (c) 2005-2007 CodeSourcery 5 * Written by Paul Brook 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21#ifndef M68K_CPU_H 22#define M68K_CPU_H 23 24#include "exec/cpu-defs.h" 25#include "cpu-qom.h" 26 27#define OS_BYTE 0 28#define OS_WORD 1 29#define OS_LONG 2 30#define OS_SINGLE 3 31#define OS_DOUBLE 4 32#define OS_EXTENDED 5 33#define OS_PACKED 6 34#define OS_UNSIZED 7 35 36#define EXCP_ACCESS 2 /* Access (MMU) error. */ 37#define EXCP_ADDRESS 3 /* Address error. */ 38#define EXCP_ILLEGAL 4 /* Illegal instruction. */ 39#define EXCP_DIV0 5 /* Divide by zero */ 40#define EXCP_CHK 6 /* CHK, CHK2 Instructions */ 41#define EXCP_TRAPCC 7 /* FTRAPcc, TRAPcc, TRAPV Instructions */ 42#define EXCP_PRIVILEGE 8 /* Privilege violation. */ 43#define EXCP_TRACE 9 44#define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ 45#define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ 46#define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ 47#define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ 48#define EXCP_FORMAT 14 /* RTE format error. */ 49#define EXCP_UNINITIALIZED 15 50#define EXCP_SPURIOUS 24 /* Spurious interrupt */ 51#define EXCP_INT_LEVEL_1 25 /* Level 1 Interrupt autovector */ 52#define EXCP_INT_LEVEL_7 31 /* Level 7 Interrupt autovector */ 53#define EXCP_TRAP0 32 /* User trap #0. */ 54#define EXCP_TRAP15 47 /* User trap #15. */ 55#define EXCP_FP_BSUN 48 /* Branch Set on Unordered */ 56#define EXCP_FP_INEX 49 /* Inexact result */ 57#define EXCP_FP_DZ 50 /* Divide by Zero */ 58#define EXCP_FP_UNFL 51 /* Underflow */ 59#define EXCP_FP_OPERR 52 /* Operand Error */ 60#define EXCP_FP_OVFL 53 /* Overflow */ 61#define EXCP_FP_SNAN 54 /* Signaling Not-A-Number */ 62#define EXCP_FP_UNIMP 55 /* Unimplemented Data type */ 63#define EXCP_MMU_CONF 56 /* MMU Configuration Error */ 64#define EXCP_MMU_ILLEGAL 57 /* MMU Illegal Operation Error */ 65#define EXCP_MMU_ACCESS 58 /* MMU Access Level Violation Error */ 66 67#define EXCP_RTE 0x100 68#define EXCP_HALT_INSN 0x101 69 70#define M68K_DTTR0 0 71#define M68K_DTTR1 1 72#define M68K_ITTR0 2 73#define M68K_ITTR1 3 74 75#define M68K_MAX_TTR 2 76#define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index] 77 78#define TARGET_INSN_START_EXTRA_WORDS 1 79 80typedef CPU_LDoubleU FPReg; 81 82typedef struct CPUM68KState { 83 uint32_t dregs[8]; 84 uint32_t aregs[8]; 85 uint32_t pc; 86 uint32_t sr; 87 88 /* 89 * The 68020/30/40 support two supervisor stacks, ISP and MSP. 90 * The 68000/10, Coldfire, and CPU32 only have USP/SSP. 91 * 92 * The current_sp is stored in aregs[7], the other here. 93 * The USP, SSP, and if used the additional ISP for 68020/30/40. 94 */ 95 int current_sp; 96 uint32_t sp[3]; 97 98 /* Condition flags. */ 99 uint32_t cc_op; 100 uint32_t cc_x; /* always 0/1 */ 101 uint32_t cc_n; /* in bit 31 (i.e. negative) */ 102 uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */ 103 uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */ 104 uint32_t cc_z; /* == 0 or unused */ 105 106 FPReg fregs[8]; 107 FPReg fp_result; 108 uint32_t fpcr; 109 uint32_t fpsr; 110 float_status fp_status; 111 112 uint64_t mactmp; 113 /* 114 * EMAC Hardware deals with 48-bit values composed of one 32-bit and 115 * two 8-bit parts. We store a single 64-bit value and 116 * rearrange/extend this when changing modes. 117 */ 118 uint64_t macc[4]; 119 uint32_t macsr; 120 uint32_t mac_mask; 121 122 /* MMU status. */ 123 struct { 124 uint32_t ar; 125 uint32_t ssw; 126 /* 68040 */ 127 uint16_t tcr; 128 uint32_t urp; 129 uint32_t srp; 130 bool fault; 131 uint32_t ttr[4]; 132 uint32_t mmusr; 133 } mmu; 134 135 /* Control registers. */ 136 uint32_t vbr; 137 uint32_t mbar; 138 uint32_t rambar0; 139 uint32_t cacr; 140 uint32_t sfc; 141 uint32_t dfc; 142 143 int pending_vector; 144 int pending_level; 145 146 /* Fields up to this point are cleared by a CPU reset */ 147 struct {} end_reset_fields; 148 149 /* Fields from here on are preserved across CPU reset. */ 150 uint32_t features; 151} CPUM68KState; 152 153/* 154 * M68kCPU: 155 * @env: #CPUM68KState 156 * 157 * A Motorola 68k CPU. 158 */ 159struct M68kCPU { 160 /*< private >*/ 161 CPUState parent_obj; 162 /*< public >*/ 163 164 CPUNegativeOffsetState neg; 165 CPUM68KState env; 166}; 167 168 169#ifndef CONFIG_USER_ONLY 170void m68k_cpu_do_interrupt(CPUState *cpu); 171bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); 172#endif /* !CONFIG_USER_ONLY */ 173void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 174hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 175int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 176int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 177 178void m68k_tcg_init(void); 179void m68k_cpu_init_gdb(M68kCPU *cpu); 180uint32_t cpu_m68k_get_ccr(CPUM68KState *env); 181void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); 182void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); 183void cpu_m68k_restore_fp_status(CPUM68KState *env); 184void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val); 185 186 187/* 188 * Instead of computing the condition codes after each m68k instruction, 189 * QEMU just stores one operand (called CC_SRC), the result 190 * (called CC_DEST) and the type of operation (called CC_OP). When the 191 * condition codes are needed, the condition codes can be calculated 192 * using this information. Condition codes are not generated if they 193 * are only needed for conditional branches. 194 */ 195typedef enum { 196 /* Translator only -- use env->cc_op. */ 197 CC_OP_DYNAMIC, 198 199 /* Each flag bit computed into cc_[xcnvz]. */ 200 CC_OP_FLAGS, 201 202 /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */ 203 CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL, 204 CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL, 205 206 /* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */ 207 CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL, 208 209 /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */ 210 CC_OP_LOGIC, 211 212 CC_OP_NB 213} CCOp; 214 215#define CCF_C 0x01 216#define CCF_V 0x02 217#define CCF_Z 0x04 218#define CCF_N 0x08 219#define CCF_X 0x10 220 221#define SR_I_SHIFT 8 222#define SR_I 0x0700 223#define SR_M 0x1000 224#define SR_S 0x2000 225#define SR_T_SHIFT 14 226#define SR_T 0xc000 227 228#define M68K_SR_TRACE(sr) ((sr & SR_T) >> SR_T_SHIFT) 229#define M68K_SR_TRACE_ANY_INS 0x2 230 231#define M68K_SSP 0 232#define M68K_USP 1 233#define M68K_ISP 2 234 235/* bits for 68040 special status word */ 236#define M68K_CP_040 0x8000 237#define M68K_CU_040 0x4000 238#define M68K_CT_040 0x2000 239#define M68K_CM_040 0x1000 240#define M68K_MA_040 0x0800 241#define M68K_ATC_040 0x0400 242#define M68K_LK_040 0x0200 243#define M68K_RW_040 0x0100 244#define M68K_SIZ_040 0x0060 245#define M68K_TT_040 0x0018 246#define M68K_TM_040 0x0007 247 248#define M68K_TM_040_DATA 0x0001 249#define M68K_TM_040_CODE 0x0002 250#define M68K_TM_040_SUPER 0x0004 251 252/* bits for 68040 write back status word */ 253#define M68K_WBV_040 0x80 254#define M68K_WBSIZ_040 0x60 255#define M68K_WBBYT_040 0x20 256#define M68K_WBWRD_040 0x40 257#define M68K_WBLNG_040 0x00 258#define M68K_WBTT_040 0x18 259#define M68K_WBTM_040 0x07 260 261/* bus access size codes */ 262#define M68K_BA_SIZE_MASK 0x60 263#define M68K_BA_SIZE_BYTE 0x20 264#define M68K_BA_SIZE_WORD 0x40 265#define M68K_BA_SIZE_LONG 0x00 266#define M68K_BA_SIZE_LINE 0x60 267 268/* bus access transfer type codes */ 269#define M68K_BA_TT_MOVE16 0x08 270 271/* bits for 68040 MMU status register (mmusr) */ 272#define M68K_MMU_B_040 0x0800 273#define M68K_MMU_G_040 0x0400 274#define M68K_MMU_U1_040 0x0200 275#define M68K_MMU_U0_040 0x0100 276#define M68K_MMU_S_040 0x0080 277#define M68K_MMU_CM_040 0x0060 278#define M68K_MMU_M_040 0x0010 279#define M68K_MMU_WP_040 0x0004 280#define M68K_MMU_T_040 0x0002 281#define M68K_MMU_R_040 0x0001 282 283#define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \ 284 M68K_MMU_U0_040 | M68K_MMU_S_040 | \ 285 M68K_MMU_CM_040 | M68K_MMU_M_040 | \ 286 M68K_MMU_WP_040) 287 288/* bits for 68040 MMU Translation Control Register */ 289#define M68K_TCR_ENABLED 0x8000 290#define M68K_TCR_PAGE_8K 0x4000 291 292/* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */ 293#define M68K_DESC_WRITEPROT 0x00000004 294#define M68K_DESC_USED 0x00000008 295#define M68K_DESC_MODIFIED 0x00000010 296#define M68K_DESC_CACHEMODE 0x00000060 297#define M68K_DESC_CM_WRTHRU 0x00000000 298#define M68K_DESC_CM_COPYBK 0x00000020 299#define M68K_DESC_CM_SERIAL 0x00000040 300#define M68K_DESC_CM_NCACHE 0x00000060 301#define M68K_DESC_SUPERONLY 0x00000080 302#define M68K_DESC_USERATTR 0x00000300 303#define M68K_DESC_USERATTR_SHIFT 8 304#define M68K_DESC_GLOBAL 0x00000400 305#define M68K_DESC_URESERVED 0x00000800 306 307#define M68K_ROOT_POINTER_ENTRIES 128 308#define M68K_4K_PAGE_MASK (~0xff) 309#define M68K_POINTER_BASE(entry) (entry & ~0x1ff) 310#define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc) 311#define M68K_POINTER_INDEX(addr) ((address >> 16) & 0x1fc) 312#define M68K_4K_PAGE_BASE(entry) (next & M68K_4K_PAGE_MASK) 313#define M68K_4K_PAGE_INDEX(addr) ((address >> 10) & 0xfc) 314#define M68K_8K_PAGE_MASK (~0x7f) 315#define M68K_8K_PAGE_BASE(entry) (next & M68K_8K_PAGE_MASK) 316#define M68K_8K_PAGE_INDEX(addr) ((address >> 11) & 0x7c) 317#define M68K_UDT_VALID(entry) (entry & 2) 318#define M68K_PDT_VALID(entry) (entry & 3) 319#define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2) 320#define M68K_INDIRECT_POINTER(addr) (addr & ~3) 321#define M68K_TTS_POINTER_SHIFT 18 322#define M68K_TTS_ROOT_SHIFT 25 323 324/* bits for 68040 MMU Transparent Translation Registers */ 325#define M68K_TTR_ADDR_BASE 0xff000000 326#define M68K_TTR_ADDR_MASK 0x00ff0000 327#define M68K_TTR_ADDR_MASK_SHIFT 8 328#define M68K_TTR_ENABLED 0x00008000 329#define M68K_TTR_SFIELD 0x00006000 330#define M68K_TTR_SFIELD_USER 0x0000 331#define M68K_TTR_SFIELD_SUPER 0x2000 332 333/* m68k Control Registers */ 334 335/* ColdFire */ 336/* Memory Management Control Registers */ 337#define M68K_CR_ASID 0x003 338#define M68K_CR_ACR0 0x004 339#define M68K_CR_ACR1 0x005 340#define M68K_CR_ACR2 0x006 341#define M68K_CR_ACR3 0x007 342#define M68K_CR_MMUBAR 0x008 343 344/* Processor Miscellaneous Registers */ 345#define M68K_CR_PC 0x80F 346 347/* Local Memory and Module Control Registers */ 348#define M68K_CR_ROMBAR0 0xC00 349#define M68K_CR_ROMBAR1 0xC01 350#define M68K_CR_RAMBAR0 0xC04 351#define M68K_CR_RAMBAR1 0xC05 352#define M68K_CR_MPCR 0xC0C 353#define M68K_CR_EDRAMBAR 0xC0D 354#define M68K_CR_SECMBAR 0xC0E 355#define M68K_CR_MBAR 0xC0F 356 357/* Local Memory Address Permutation Control Registers */ 358#define M68K_CR_PCR1U0 0xD02 359#define M68K_CR_PCR1L0 0xD03 360#define M68K_CR_PCR2U0 0xD04 361#define M68K_CR_PCR2L0 0xD05 362#define M68K_CR_PCR3U0 0xD06 363#define M68K_CR_PCR3L0 0xD07 364#define M68K_CR_PCR1U1 0xD0A 365#define M68K_CR_PCR1L1 0xD0B 366#define M68K_CR_PCR2U1 0xD0C 367#define M68K_CR_PCR2L1 0xD0D 368#define M68K_CR_PCR3U1 0xD0E 369#define M68K_CR_PCR3L1 0xD0F 370 371/* MC680x0 */ 372/* MC680[1234]0/CPU32 */ 373#define M68K_CR_SFC 0x000 374#define M68K_CR_DFC 0x001 375#define M68K_CR_USP 0x800 376#define M68K_CR_VBR 0x801 /* + Coldfire */ 377 378/* MC680[234]0 */ 379#define M68K_CR_CACR 0x002 /* + Coldfire */ 380#define M68K_CR_CAAR 0x802 /* MC68020 and MC68030 only */ 381#define M68K_CR_MSP 0x803 382#define M68K_CR_ISP 0x804 383 384/* MC68040/MC68LC040 */ 385#define M68K_CR_TC 0x003 386#define M68K_CR_ITT0 0x004 387#define M68K_CR_ITT1 0x005 388#define M68K_CR_DTT0 0x006 389#define M68K_CR_DTT1 0x007 390#define M68K_CR_MMUSR 0x805 391#define M68K_CR_URP 0x806 392#define M68K_CR_SRP 0x807 393 394/* MC68EC040 */ 395#define M68K_CR_IACR0 0x004 396#define M68K_CR_IACR1 0x005 397#define M68K_CR_DACR0 0x006 398#define M68K_CR_DACR1 0x007 399 400/* MC68060 */ 401#define M68K_CR_BUSCR 0x008 402#define M68K_CR_PCR 0x808 403 404#define M68K_FPIAR_SHIFT 0 405#define M68K_FPIAR (1 << M68K_FPIAR_SHIFT) 406#define M68K_FPSR_SHIFT 1 407#define M68K_FPSR (1 << M68K_FPSR_SHIFT) 408#define M68K_FPCR_SHIFT 2 409#define M68K_FPCR (1 << M68K_FPCR_SHIFT) 410 411/* Floating-Point Status Register */ 412 413/* Condition Code */ 414#define FPSR_CC_MASK 0x0f000000 415#define FPSR_CC_A 0x01000000 /* Not-A-Number */ 416#define FPSR_CC_I 0x02000000 /* Infinity */ 417#define FPSR_CC_Z 0x04000000 /* Zero */ 418#define FPSR_CC_N 0x08000000 /* Negative */ 419 420/* Quotient */ 421 422#define FPSR_QT_MASK 0x00ff0000 423#define FPSR_QT_SHIFT 16 424 425/* Floating-Point Control Register */ 426/* Rounding mode */ 427#define FPCR_RND_MASK 0x0030 428#define FPCR_RND_N 0x0000 429#define FPCR_RND_Z 0x0010 430#define FPCR_RND_M 0x0020 431#define FPCR_RND_P 0x0030 432 433/* Rounding precision */ 434#define FPCR_PREC_MASK 0x00c0 435#define FPCR_PREC_X 0x0000 436#define FPCR_PREC_S 0x0040 437#define FPCR_PREC_D 0x0080 438#define FPCR_PREC_U 0x00c0 439 440#define FPCR_EXCP_MASK 0xff00 441 442/* CACR fields are implementation defined, but some bits are common. */ 443#define M68K_CACR_EUSP 0x10 444 445#define MACSR_PAV0 0x100 446#define MACSR_OMC 0x080 447#define MACSR_SU 0x040 448#define MACSR_FI 0x020 449#define MACSR_RT 0x010 450#define MACSR_N 0x008 451#define MACSR_Z 0x004 452#define MACSR_V 0x002 453#define MACSR_EV 0x001 454 455void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector); 456void m68k_switch_sp(CPUM68KState *env); 457 458void do_m68k_semihosting(CPUM68KState *env, int nr); 459 460/* 461 * The 68000 family is defined in six main CPU classes, the 680[012346]0. 462 * Generally each successive CPU adds enhanced data/stack/instructions. 463 * However, some features are only common to one, or a few classes. 464 * The features covers those subsets of instructons. 465 * 466 * CPU32/32+ are basically 680010 compatible with some 68020 class instructons, 467 * and some additional CPU32 instructions. Mostly Supervisor state differences. 468 * 469 * The ColdFire core ISA is a RISC-style reduction of the 68000 series cpu. 470 * There are 4 ColdFire core ISA revisions: A, A+, B and C. 471 * Each feature covers the subset of instructions common to the 472 * ISA revisions mentioned. 473 */ 474 475enum m68k_features { 476 /* Base m68k instruction set */ 477 M68K_FEATURE_M68000, 478 M68K_FEATURE_M68010, 479 M68K_FEATURE_M68020, 480 M68K_FEATURE_M68030, 481 M68K_FEATURE_M68040, 482 M68K_FEATURE_M68060, 483 /* Base Coldfire set Rev A. */ 484 M68K_FEATURE_CF_ISA_A, 485 /* (ISA B or C). */ 486 M68K_FEATURE_CF_ISA_B, 487 /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ 488 M68K_FEATURE_CF_ISA_APLUSC, 489 /* BRA with Long branch. (680[2346]0, ISA A+ or B). */ 490 M68K_FEATURE_BRAL, 491 M68K_FEATURE_CF_FPU, 492 M68K_FEATURE_CF_MAC, 493 M68K_FEATURE_CF_EMAC, 494 /* Revision B EMAC (dual accumulate). */ 495 M68K_FEATURE_CF_EMAC_B, 496 /* User Stack Pointer. (680[012346]0, ISA A+, B or C). */ 497 M68K_FEATURE_USP, 498 /* Master Stack Pointer. (680[234]0) */ 499 M68K_FEATURE_MSP, 500 /* 68020+ full extension word. */ 501 M68K_FEATURE_EXT_FULL, 502 /* word sized address index registers. */ 503 M68K_FEATURE_WORD_INDEX, 504 /* scaled address index registers. */ 505 M68K_FEATURE_SCALED_INDEX, 506 /* 32 bit mul/div. (680[2346]0, and CPU32) */ 507 M68K_FEATURE_LONG_MULDIV, 508 /* 64 bit mul/div. (680[2346]0, and CPU32) */ 509 M68K_FEATURE_QUAD_MULDIV, 510 /* Bcc with Long branches. (680[2346]0, and CPU32) */ 511 M68K_FEATURE_BCCL, 512 /* BFxxx Bit field insns. (680[2346]0) */ 513 M68K_FEATURE_BITFIELD, 514 /* fpu insn. (680[46]0) */ 515 M68K_FEATURE_FPU, 516 /* CAS/CAS2[WL] insns. (680[2346]0) */ 517 M68K_FEATURE_CAS, 518 /* BKPT insn. (680[12346]0, and CPU32) */ 519 M68K_FEATURE_BKPT, 520 /* RTD insn. (680[12346]0, and CPU32) */ 521 M68K_FEATURE_RTD, 522 /* CHK2 insn. (680[2346]0, and CPU32) */ 523 M68K_FEATURE_CHK2, 524 /* MOVEP insn. (680[01234]0, and CPU32) */ 525 M68K_FEATURE_MOVEP, 526 /* MOVEC insn. (from 68010) */ 527 M68K_FEATURE_MOVEC, 528 /* Unaligned data accesses (680[2346]0) */ 529 M68K_FEATURE_UNALIGNED_DATA, 530}; 531 532static inline int m68k_feature(CPUM68KState *env, int feature) 533{ 534 return (env->features & (1u << feature)) != 0; 535} 536 537void m68k_cpu_list(void); 538 539void register_m68k_insns (CPUM68KState *env); 540 541enum { 542 /* 1 bit to define user level / supervisor access */ 543 ACCESS_SUPER = 0x01, 544 /* 1 bit to indicate direction */ 545 ACCESS_STORE = 0x02, 546 /* 1 bit to indicate debug access */ 547 ACCESS_DEBUG = 0x04, 548 /* PTEST instruction */ 549 ACCESS_PTEST = 0x08, 550 /* Type of instruction that generated the access */ 551 ACCESS_CODE = 0x10, /* Code fetch access */ 552 ACCESS_DATA = 0x20, /* Data load/store access */ 553}; 554 555#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU 556#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX 557#define CPU_RESOLVING_TYPE TYPE_M68K_CPU 558 559#define cpu_list m68k_cpu_list 560 561/* MMU modes definitions */ 562#define MMU_KERNEL_IDX 0 563#define MMU_USER_IDX 1 564static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) 565{ 566 return (env->sr & SR_S) == 0 ? 1 : 0; 567} 568 569bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 570 MMUAccessType access_type, int mmu_idx, 571 bool probe, uintptr_t retaddr); 572void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, 573 unsigned size, MMUAccessType access_type, 574 int mmu_idx, MemTxAttrs attrs, 575 MemTxResult response, uintptr_t retaddr); 576 577typedef CPUM68KState CPUArchState; 578typedef M68kCPU ArchCPU; 579 580#include "exec/cpu-all.h" 581 582/* TB flags */ 583#define TB_FLAGS_MACSR 0x0f 584#define TB_FLAGS_MSR_S_BIT 13 585#define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT) 586#define TB_FLAGS_SFC_S_BIT 14 587#define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT) 588#define TB_FLAGS_DFC_S_BIT 15 589#define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT) 590#define TB_FLAGS_TRACE 16 591#define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE) 592 593static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc, 594 target_ulong *cs_base, uint32_t *flags) 595{ 596 *pc = env->pc; 597 *cs_base = 0; 598 *flags = (env->macsr >> 4) & TB_FLAGS_MACSR; 599 if (env->sr & SR_S) { 600 *flags |= TB_FLAGS_MSR_S; 601 *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; 602 *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; 603 } 604 if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) { 605 *flags |= TB_FLAGS_TRACE; 606 } 607} 608 609void dump_mmu(CPUM68KState *env); 610 611#endif