cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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msa.decode (1165B)


      1# MIPS SIMD Architecture Module instruction set
      2#
      3# Copyright (C) 2020  Philippe Mathieu-Daudé
      4#
      5# SPDX-License-Identifier: LGPL-2.1-or-later
      6#
      7# Reference:
      8#       MIPS Architecture for Programmers Volume IV-j
      9#       - The MIPS32 SIMD Architecture Module, Revision 1.12
     10#         (Document Number: MD00866-2B-MSA32-AFP-01.12)
     11#       - The MIPS64 SIMD Architecture Module, Revision 1.12
     12#         (Document Number: MD00868-1D-MSA64-AFP-01.12)
     13
     14&r                  rs rt rd sa
     15
     16&msa_bz             df wt s16
     17
     18@lsa                ...... rs:5 rt:5 rd:5 ... sa:2 ......   &r
     19@bz                 ...... ... ..   wt:5 s16:16             &msa_bz df=3
     20@bz_df              ...... ... df:2 wt:5 s16:16             &msa_bz
     21
     22LSA                 000000 ..... ..... ..... 000 .. 000101  @lsa
     23DLSA                000000 ..... ..... ..... 000 .. 010101  @lsa
     24
     25BZ_V                010001 01011  ..... ................    @bz
     26BNZ_V               010001 01111  ..... ................    @bz
     27
     28BZ_x                010001 110 .. ..... ................    @bz_df
     29BNZ_x               010001 111 .. ..... ................    @bz_df
     30
     31MSA                 011110 --------------------------