cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

tlb_helper.c (1947B)

      1/*
      2 * MIPS TLB (Translation lookaside buffer) helpers.
      3 *
      4 *  Copyright (c) 2004-2005 Jocelyn Mayer
      5 *
      6 * This library is free software; you can redistribute it and/or
      7 * modify it under the terms of the GNU Lesser General Public
      8 * License as published by the Free Software Foundation; either
      9 * version 2.1 of the License, or (at your option) any later version.
     10 *
     11 * This library is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     14 * Lesser General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU Lesser General Public
     17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
     18 */
     19#include "qemu/osdep.h"
     20
     21#include "cpu.h"
     22#include "exec/exec-all.h"
     23#include "internal.h"
     24
     25static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
     26                                MMUAccessType access_type)
     27{
     28    CPUState *cs = env_cpu(env);
     29
     30    env->error_code = 0;
     31    if (access_type == MMU_INST_FETCH) {
     32        env->error_code |= EXCP_INST_NOTAVAIL;
     33    }
     34
     35    /* Reference to kernel address from user mode or supervisor mode */
     36    /* Reference to supervisor address from user mode */
     37    if (access_type == MMU_DATA_STORE) {
     38        cs->exception_index = EXCP_AdES;
     39    } else {
     40        cs->exception_index = EXCP_AdEL;
     41    }
     42
     43    /* Raise exception */
     44    if (!(env->hflags & MIPS_HFLAG_DM)) {
     45        env->CP0_BadVAddr = address;
     46    }
     47}
     48
     49bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     50                       MMUAccessType access_type, int mmu_idx,
     51                       bool probe, uintptr_t retaddr)
     52{
     53    MIPSCPU *cpu = MIPS_CPU(cs);
     54    CPUMIPSState *env = &cpu->env;
     55
     56    /* data access */
     57    raise_mmu_exception(env, address, access_type);
     58    do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr);
     59}