cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

cpu.h (112219B)

      1/*
      2 *  PowerPC emulation cpu definitions for qemu.
      3 *
      4 *  Copyright (c) 2003-2007 Jocelyn Mayer
      5 *
      6 * This library is free software; you can redistribute it and/or
      7 * modify it under the terms of the GNU Lesser General Public
      8 * License as published by the Free Software Foundation; either
      9 * version 2.1 of the License, or (at your option) any later version.
     10 *
     11 * This library is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     14 * Lesser General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU Lesser General Public
     17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
     18 */
     19
     20#ifndef PPC_CPU_H
     21#define PPC_CPU_H
     22
     23#include "qemu/int128.h"
     24#include "exec/cpu-defs.h"
     25#include "cpu-qom.h"
     26#include "qom/object.h"
     27
     28#define TCG_GUEST_DEFAULT_MO 0
     29
     30#define TARGET_PAGE_BITS_64K 16
     31#define TARGET_PAGE_BITS_16M 24
     32
     33#if defined(TARGET_PPC64)
     34#define PPC_ELF_MACHINE     EM_PPC64
     35#else
     36#define PPC_ELF_MACHINE     EM_PPC
     37#endif
     38
     39#define PPC_BIT(bit)            (0x8000000000000000ULL >> (bit))
     40#define PPC_BIT32(bit)          (0x80000000 >> (bit))
     41#define PPC_BIT8(bit)           (0x80 >> (bit))
     42#define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
     43#define PPC_BITMASK32(bs, be)   ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
     44                                 PPC_BIT32(bs))
     45#define PPC_BITMASK8(bs, be)    ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
     46
     47/*****************************************************************************/
     48/* Exception vectors definitions                                             */
     49enum {
     50    POWERPC_EXCP_NONE    = -1,
     51    /* The 64 first entries are used by the PowerPC embedded specification   */
     52    POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
     53    POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
     54    POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
     55    POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
     56    POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
     57    POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
     58    POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
     59    POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
     60    POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
     61    POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
     62    POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
     63    POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
     64    POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
     65    POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */
     66    POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */
     67    POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
     68    /* Vectors 16 to 31 are reserved                                         */
     69    POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
     70    POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
     71    POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
     72    POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
     73    POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
     74    POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
     75    POWERPC_EXCP_GDOORI   = 38, /* Embedded guest doorbell interrupt         */
     76    POWERPC_EXCP_GDOORCI  = 39, /* Embedded guest doorbell critical interrupt*/
     77    POWERPC_EXCP_HYPPRIV  = 41, /* Embedded hypervisor priv instruction      */
     78    /* Vectors 42 to 63 are reserved                                         */
     79    /* Exceptions defined in the PowerPC server specification                */
     80    POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
     81    POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
     82    POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
     83    POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
     84    POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
     85    POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
     86    POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
     87    POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
     88    POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
     89    POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
     90    /* 40x specific exceptions                                               */
     91    POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
     92    /* 601 specific exceptions                                               */
     93    POWERPC_EXCP_IO       = 75, /* IO error exception                        */
     94    POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
     95    /* 602 specific exceptions                                               */
     96    POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
     97    /* 602/603 specific exceptions                                           */
     98    POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */
     99    POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
    100    POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
    101    /* Exceptions available on most PowerPC                                  */
    102    POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
    103    POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */
    104    POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */
    105    POWERPC_EXCP_SMI      = 84, /* System management interrupt               */
    106    POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */
    107    /* 7xx/74xx specific exceptions                                          */
    108    POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */
    109    /* 74xx specific exceptions                                              */
    110    POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */
    111    /* 970FX specific exceptions                                             */
    112    POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */
    113    POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */
    114    /* Freescale embedded cores specific exceptions                          */
    115    POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */
    116    POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */
    117    POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */
    118    POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */
    119    /* VSX Unavailable (Power ISA 2.06 and later)                            */
    120    POWERPC_EXCP_VSXU     = 94, /* VSX Unavailable                           */
    121    POWERPC_EXCP_FU       = 95, /* Facility Unavailable                      */
    122    /* Additional ISA 2.06 and later server exceptions                       */
    123    POWERPC_EXCP_HV_EMU   = 96, /* HV emulation assistance                   */
    124    POWERPC_EXCP_HV_MAINT = 97, /* HMI                                       */
    125    POWERPC_EXCP_HV_FU    = 98, /* Hypervisor Facility unavailable           */
    126    /* Server doorbell variants */
    127    POWERPC_EXCP_SDOOR    = 99,
    128    POWERPC_EXCP_SDOOR_HV = 100,
    129    /* ISA 3.00 additions */
    130    POWERPC_EXCP_HVIRT    = 101,
    131    POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception                     */
    132    /* EOL                                                                   */
    133    POWERPC_EXCP_NB       = 103,
    134    /* QEMU exceptions: special cases we want to stop translation            */
    135    POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
    136};
    137
    138/* Exceptions error codes                                                    */
    139enum {
    140    /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
    141    POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
    142    POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
    143    POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
    144    POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
    145    POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
    146    POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
    147    POWERPC_EXCP_ALIGN_INSN    = 0x07,  /* Pref. insn x-ing 64-byte boundary */
    148    /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
    149    /* FP exceptions                                                         */
    150    POWERPC_EXCP_FP            = 0x10,
    151    POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
    152    POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
    153    POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
    154    POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
    155    POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
    156    POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
    157    POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
    158    POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
    159    POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
    160    POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
    161    POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
    162    POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
    163    POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
    164    /* Invalid instruction                                                   */
    165    POWERPC_EXCP_INVAL         = 0x20,
    166    POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
    167    POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
    168    POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
    169    POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
    170    /* Privileged instruction                                                */
    171    POWERPC_EXCP_PRIV          = 0x30,
    172    POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
    173    POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
    174    /* Trap                                                                  */
    175    POWERPC_EXCP_TRAP          = 0x40,
    176};
    177
    178#define PPC_INPUT(env) ((env)->bus_model)
    179
    180/*****************************************************************************/
    181typedef struct opc_handler_t opc_handler_t;
    182
    183/*****************************************************************************/
    184/* Types used to describe some PowerPC registers etc. */
    185typedef struct DisasContext DisasContext;
    186typedef struct ppc_spr_t ppc_spr_t;
    187typedef union ppc_tlb_t ppc_tlb_t;
    188typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
    189
    190/* SPR access micro-ops generations callbacks */
    191struct ppc_spr_t {
    192    const char *name;
    193    target_ulong default_value;
    194#ifndef CONFIG_USER_ONLY
    195    unsigned int gdb_id;
    196#endif
    197#ifdef CONFIG_TCG
    198    void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
    199    void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
    200# ifndef CONFIG_USER_ONLY
    201    void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
    202    void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
    203    void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
    204    void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
    205# endif
    206#endif
    207#ifdef CONFIG_KVM
    208    /*
    209     * We (ab)use the fact that all the SPRs will have ids for the
    210     * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
    211     * don't sync this
    212     */
    213    uint64_t one_reg_id;
    214#endif
    215};
    216
    217/* VSX/Altivec registers (128 bits) */
    218typedef union _ppc_vsr_t {
    219    uint8_t u8[16];
    220    uint16_t u16[8];
    221    uint32_t u32[4];
    222    uint64_t u64[2];
    223    int8_t s8[16];
    224    int16_t s16[8];
    225    int32_t s32[4];
    226    int64_t s64[2];
    227    float32 f32[4];
    228    float64 f64[2];
    229    float128 f128;
    230#ifdef CONFIG_INT128
    231    __uint128_t u128;
    232#endif
    233    Int128  s128;
    234} ppc_vsr_t;
    235
    236typedef ppc_vsr_t ppc_avr_t;
    237typedef ppc_vsr_t ppc_fprp_t;
    238
    239#if !defined(CONFIG_USER_ONLY)
    240/* Software TLB cache */
    241typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
    242struct ppc6xx_tlb_t {
    243    target_ulong pte0;
    244    target_ulong pte1;
    245    target_ulong EPN;
    246};
    247
    248typedef struct ppcemb_tlb_t ppcemb_tlb_t;
    249struct ppcemb_tlb_t {
    250    uint64_t RPN;
    251    target_ulong EPN;
    252    target_ulong PID;
    253    target_ulong size;
    254    uint32_t prot;
    255    uint32_t attr; /* Storage attributes */
    256};
    257
    258typedef struct ppcmas_tlb_t {
    259     uint32_t mas8;
    260     uint32_t mas1;
    261     uint64_t mas2;
    262     uint64_t mas7_3;
    263} ppcmas_tlb_t;
    264
    265union ppc_tlb_t {
    266    ppc6xx_tlb_t *tlb6;
    267    ppcemb_tlb_t *tlbe;
    268    ppcmas_tlb_t *tlbm;
    269};
    270
    271/* possible TLB variants */
    272#define TLB_NONE               0
    273#define TLB_6XX                1
    274#define TLB_EMB                2
    275#define TLB_MAS                3
    276#endif
    277
    278typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes;
    279
    280typedef struct ppc_slb_t ppc_slb_t;
    281struct ppc_slb_t {
    282    uint64_t esid;
    283    uint64_t vsid;
    284    const PPCHash64SegmentPageSizes *sps;
    285};
    286
    287#define MAX_SLB_ENTRIES         64
    288#define SEGMENT_SHIFT_256M      28
    289#define SEGMENT_MASK_256M       (~((1ULL << SEGMENT_SHIFT_256M) - 1))
    290
    291#define SEGMENT_SHIFT_1T        40
    292#define SEGMENT_MASK_1T         (~((1ULL << SEGMENT_SHIFT_1T) - 1))
    293
    294typedef struct ppc_v3_pate_t {
    295    uint64_t dw0;
    296    uint64_t dw1;
    297} ppc_v3_pate_t;
    298
    299/*****************************************************************************/
    300/* Machine state register bits definition                                    */
    301#define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
    302#define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            */
    303#define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
    304#define MSR_HV   60 /* hypervisor state                               hflags */
    305#define MSR_TS0  34 /* Transactional state, 2 bits (Book3s)                  */
    306#define MSR_TS1  33
    307#define MSR_TM   32 /* Transactional Memory Available (Book3s)               */
    308#define MSR_CM   31 /* Computation mode for BookE                     hflags */
    309#define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
    310#define MSR_GS   28 /* guest state for BookE                                 */
    311#define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
    312#define MSR_VR   25 /* altivec available                            x hflags */
    313#define MSR_SPE  25 /* SPE enable for BookE                         x hflags */
    314#define MSR_AP   23 /* Access privilege state on 602                  hflags */
    315#define MSR_VSX  23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
    316#define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
    317#define MSR_KEY  19 /* key bit on 603e                                       */
    318#define MSR_POW  18 /* Power management                                      */
    319#define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
    320#define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
    321#define MSR_ILE  16 /* Interrupt little-endian mode                          */
    322#define MSR_EE   15 /* External interrupt enable                             */
    323#define MSR_PR   14 /* Problem state                                  hflags */
    324#define MSR_FP   13 /* Floating point available                       hflags */
    325#define MSR_ME   12 /* Machine check interrupt enable                        */
    326#define MSR_FE0  11 /* Floating point exception mode 0                       */
    327#define MSR_SE   10 /* Single-step trace enable                     x hflags */
    328#define MSR_DWE  10 /* Debug wait enable on 405                     x        */
    329#define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */
    330#define MSR_BE   9  /* Branch trace enable                          x hflags */
    331#define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
    332#define MSR_FE1  8  /* Floating point exception mode 1                       */
    333#define MSR_AL   7  /* AL bit on POWER                                       */
    334#define MSR_EP   6  /* Exception prefix on 601                               */
    335#define MSR_IR   5  /* Instruction relocate                                  */
    336#define MSR_DR   4  /* Data relocate                                         */
    337#define MSR_IS   5  /* Instruction address space (BookE)                     */
    338#define MSR_DS   4  /* Data address space (BookE)                            */
    339#define MSR_PE   3  /* Protection enable on 403                              */
    340#define MSR_PX   2  /* Protection exclusive on 403                  x        */
    341#define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
    342#define MSR_RI   1  /* Recoverable interrupt                        1        */
    343#define MSR_LE   0  /* Little-endian mode                           1 hflags */
    344
    345/* LPCR bits */
    346#define LPCR_VPM0         PPC_BIT(0)
    347#define LPCR_VPM1         PPC_BIT(1)
    348#define LPCR_ISL          PPC_BIT(2)
    349#define LPCR_KBV          PPC_BIT(3)
    350#define LPCR_DPFD_SHIFT   (63 - 11)
    351#define LPCR_DPFD         (0x7ull << LPCR_DPFD_SHIFT)
    352#define LPCR_VRMASD_SHIFT (63 - 16)
    353#define LPCR_VRMASD       (0x1full << LPCR_VRMASD_SHIFT)
    354/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
    355#define LPCR_PECE_U_SHIFT (63 - 19)
    356#define LPCR_PECE_U_MASK  (0x7ull << LPCR_PECE_U_SHIFT)
    357#define LPCR_HVEE         PPC_BIT(17) /* Hypervisor Virt Exit Enable */
    358#define LPCR_RMLS_SHIFT   (63 - 37)   /* RMLS (removed in ISA v3.0) */
    359#define LPCR_RMLS         (0xfull << LPCR_RMLS_SHIFT)
    360#define LPCR_HAIL         PPC_BIT(37) /* ISA v3.1 HV AIL=3 equivalent */
    361#define LPCR_ILE          PPC_BIT(38)
    362#define LPCR_AIL_SHIFT    (63 - 40)   /* Alternate interrupt location */
    363#define LPCR_AIL          (3ull << LPCR_AIL_SHIFT)
    364#define LPCR_UPRT         PPC_BIT(41) /* Use Process Table */
    365#define LPCR_EVIRT        PPC_BIT(42) /* Enhanced Virtualisation */
    366#define LPCR_HR           PPC_BIT(43) /* Host Radix */
    367#define LPCR_ONL          PPC_BIT(45)
    368#define LPCR_LD           PPC_BIT(46) /* Large Decrementer */
    369#define LPCR_P7_PECE0     PPC_BIT(49)
    370#define LPCR_P7_PECE1     PPC_BIT(50)
    371#define LPCR_P7_PECE2     PPC_BIT(51)
    372#define LPCR_P8_PECE0     PPC_BIT(47)
    373#define LPCR_P8_PECE1     PPC_BIT(48)
    374#define LPCR_P8_PECE2     PPC_BIT(49)
    375#define LPCR_P8_PECE3     PPC_BIT(50)
    376#define LPCR_P8_PECE4     PPC_BIT(51)
    377/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
    378#define LPCR_PECE_L_SHIFT (63 - 51)
    379#define LPCR_PECE_L_MASK  (0x1full << LPCR_PECE_L_SHIFT)
    380#define LPCR_PDEE         PPC_BIT(47) /* Privileged Doorbell Exit EN */
    381#define LPCR_HDEE         PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
    382#define LPCR_EEE          PPC_BIT(49) /* External Exit Enable        */
    383#define LPCR_DEE          PPC_BIT(50) /* Decrementer Exit Enable     */
    384#define LPCR_OEE          PPC_BIT(51) /* Other Exit Enable           */
    385#define LPCR_MER          PPC_BIT(52)
    386#define LPCR_GTSE         PPC_BIT(53) /* Guest Translation Shootdown */
    387#define LPCR_TC           PPC_BIT(54)
    388#define LPCR_HEIC         PPC_BIT(59) /* HV Extern Interrupt Control */
    389#define LPCR_LPES0        PPC_BIT(60)
    390#define LPCR_LPES1        PPC_BIT(61)
    391#define LPCR_RMI          PPC_BIT(62)
    392#define LPCR_HVICE        PPC_BIT(62) /* HV Virtualisation Int Enable */
    393#define LPCR_HDICE        PPC_BIT(63)
    394
    395/* PSSCR bits */
    396#define PSSCR_ESL         PPC_BIT(42) /* Enable State Loss */
    397#define PSSCR_EC          PPC_BIT(43) /* Exit Criterion */
    398
    399/* HFSCR bits */
    400#define HFSCR_MSGP     PPC_BIT(53) /* Privileged Message Send Facilities */
    401#define HFSCR_IC_MSGP  0xA
    402
    403#define msr_sf   ((env->msr >> MSR_SF)   & 1)
    404#define msr_isf  ((env->msr >> MSR_ISF)  & 1)
    405#if defined(TARGET_PPC64)
    406#define msr_hv   ((env->msr >> MSR_HV)   & 1)
    407#else
    408#define msr_hv   (0)
    409#endif
    410#define msr_cm   ((env->msr >> MSR_CM)   & 1)
    411#define msr_icm  ((env->msr >> MSR_ICM)  & 1)
    412#define msr_gs   ((env->msr >> MSR_GS)   & 1)
    413#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
    414#define msr_vr   ((env->msr >> MSR_VR)   & 1)
    415#define msr_spe  ((env->msr >> MSR_SPE)  & 1)
    416#define msr_ap   ((env->msr >> MSR_AP)   & 1)
    417#define msr_vsx  ((env->msr >> MSR_VSX)  & 1)
    418#define msr_sa   ((env->msr >> MSR_SA)   & 1)
    419#define msr_key  ((env->msr >> MSR_KEY)  & 1)
    420#define msr_pow  ((env->msr >> MSR_POW)  & 1)
    421#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
    422#define msr_ce   ((env->msr >> MSR_CE)   & 1)
    423#define msr_ile  ((env->msr >> MSR_ILE)  & 1)
    424#define msr_ee   ((env->msr >> MSR_EE)   & 1)
    425#define msr_pr   ((env->msr >> MSR_PR)   & 1)
    426#define msr_fp   ((env->msr >> MSR_FP)   & 1)
    427#define msr_me   ((env->msr >> MSR_ME)   & 1)
    428#define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
    429#define msr_se   ((env->msr >> MSR_SE)   & 1)
    430#define msr_dwe  ((env->msr >> MSR_DWE)  & 1)
    431#define msr_uble ((env->msr >> MSR_UBLE) & 1)
    432#define msr_be   ((env->msr >> MSR_BE)   & 1)
    433#define msr_de   ((env->msr >> MSR_DE)   & 1)
    434#define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
    435#define msr_al   ((env->msr >> MSR_AL)   & 1)
    436#define msr_ep   ((env->msr >> MSR_EP)   & 1)
    437#define msr_ir   ((env->msr >> MSR_IR)   & 1)
    438#define msr_dr   ((env->msr >> MSR_DR)   & 1)
    439#define msr_is   ((env->msr >> MSR_IS)   & 1)
    440#define msr_ds   ((env->msr >> MSR_DS)   & 1)
    441#define msr_pe   ((env->msr >> MSR_PE)   & 1)
    442#define msr_px   ((env->msr >> MSR_PX)   & 1)
    443#define msr_pmm  ((env->msr >> MSR_PMM)  & 1)
    444#define msr_ri   ((env->msr >> MSR_RI)   & 1)
    445#define msr_le   ((env->msr >> MSR_LE)   & 1)
    446#define msr_ts   ((env->msr >> MSR_TS1)  & 3)
    447#define msr_tm   ((env->msr >> MSR_TM)   & 1)
    448
    449#define DBCR0_ICMP (1 << 27)
    450#define DBCR0_BRT (1 << 26)
    451#define DBSR_ICMP (1 << 27)
    452#define DBSR_BRT (1 << 26)
    453
    454/* Hypervisor bit is more specific */
    455#if defined(TARGET_PPC64)
    456#define MSR_HVB (1ULL << MSR_HV)
    457#else
    458#define MSR_HVB (0ULL)
    459#endif
    460
    461/* DSISR */
    462#define DSISR_NOPTE              0x40000000
    463/* Not permitted by access authority of encoded access authority */
    464#define DSISR_PROTFAULT          0x08000000
    465#define DSISR_ISSTORE            0x02000000
    466/* Not permitted by virtual page class key protection */
    467#define DSISR_AMR                0x00200000
    468/* Unsupported Radix Tree Configuration */
    469#define DSISR_R_BADCONFIG        0x00080000
    470#define DSISR_ATOMIC_RC          0x00040000
    471/* Unable to translate address of (guest) pde or process/page table entry */
    472#define DSISR_PRTABLE_FAULT      0x00020000
    473
    474/* SRR1 error code fields */
    475
    476#define SRR1_NOPTE               DSISR_NOPTE
    477/* Not permitted due to no-execute or guard bit set */
    478#define SRR1_NOEXEC_GUARD        0x10000000
    479#define SRR1_PROTFAULT           DSISR_PROTFAULT
    480#define SRR1_IAMR                DSISR_AMR
    481
    482/* SRR1[42:45] wakeup fields for System Reset Interrupt */
    483
    484#define SRR1_WAKEMASK           0x003c0000 /* reason for wakeup */
    485
    486#define SRR1_WAKEHMI            0x00280000 /* Hypervisor maintenance */
    487#define SRR1_WAKEHVI            0x00240000 /* Hypervisor Virt. Interrupt (P9) */
    488#define SRR1_WAKEEE             0x00200000 /* External interrupt */
    489#define SRR1_WAKEDEC            0x00180000 /* Decrementer interrupt */
    490#define SRR1_WAKEDBELL          0x00140000 /* Privileged doorbell */
    491#define SRR1_WAKERESET          0x00100000 /* System reset */
    492#define SRR1_WAKEHDBELL         0x000c0000 /* Hypervisor doorbell */
    493#define SRR1_WAKESCOM           0x00080000 /* SCOM not in power-saving mode */
    494
    495/* SRR1[46:47] power-saving exit mode */
    496
    497#define SRR1_WAKESTATE          0x00030000 /* Powersave exit mask */
    498
    499#define SRR1_WS_HVLOSS          0x00030000 /* HV resources not maintained */
    500#define SRR1_WS_GPRLOSS         0x00020000 /* GPRs not maintained */
    501#define SRR1_WS_NOLOSS          0x00010000 /* All resources maintained */
    502
    503/* Facility Status and Control (FSCR) bits */
    504#define FSCR_EBB        (63 - 56) /* Event-Based Branch Facility */
    505#define FSCR_TAR        (63 - 55) /* Target Address Register */
    506#define FSCR_SCV        (63 - 51) /* System call vectored */
    507/* Interrupt cause mask and position in FSCR. HFSCR has the same format */
    508#define FSCR_IC_MASK    (0xFFULL)
    509#define FSCR_IC_POS     (63 - 7)
    510#define FSCR_IC_DSCR_SPR3   2
    511#define FSCR_IC_PMU         3
    512#define FSCR_IC_BHRB        4
    513#define FSCR_IC_TM          5
    514#define FSCR_IC_EBB         7
    515#define FSCR_IC_TAR         8
    516#define FSCR_IC_SCV        12
    517
    518/* Exception state register bits definition                                  */
    519#define ESR_PIL   PPC_BIT(36) /* Illegal Instruction                    */
    520#define ESR_PPR   PPC_BIT(37) /* Privileged Instruction                 */
    521#define ESR_PTR   PPC_BIT(38) /* Trap                                   */
    522#define ESR_FP    PPC_BIT(39) /* Floating-Point Operation               */
    523#define ESR_ST    PPC_BIT(40) /* Store Operation                        */
    524#define ESR_AP    PPC_BIT(44) /* Auxiliary Processor Operation          */
    525#define ESR_PUO   PPC_BIT(45) /* Unimplemented Operation                */
    526#define ESR_BO    PPC_BIT(46) /* Byte Ordering                          */
    527#define ESR_PIE   PPC_BIT(47) /* Imprecise exception                    */
    528#define ESR_DATA  PPC_BIT(53) /* Data Access (Embedded page table)      */
    529#define ESR_TLBI  PPC_BIT(54) /* TLB Ineligible (Embedded page table)   */
    530#define ESR_PT    PPC_BIT(55) /* Page Table (Embedded page table)       */
    531#define ESR_SPV   PPC_BIT(56) /* SPE/VMX operation                      */
    532#define ESR_EPID  PPC_BIT(57) /* External Process ID operation          */
    533#define ESR_VLEMI PPC_BIT(58) /* VLE operation                          */
    534#define ESR_MIF   PPC_BIT(62) /* Misaligned instruction (VLE)           */
    535
    536/* Transaction EXception And Summary Register bits                           */
    537#define TEXASR_FAILURE_PERSISTENT                (63 - 7)
    538#define TEXASR_DISALLOWED                        (63 - 8)
    539#define TEXASR_NESTING_OVERFLOW                  (63 - 9)
    540#define TEXASR_FOOTPRINT_OVERFLOW                (63 - 10)
    541#define TEXASR_SELF_INDUCED_CONFLICT             (63 - 11)
    542#define TEXASR_NON_TRANSACTIONAL_CONFLICT        (63 - 12)
    543#define TEXASR_TRANSACTION_CONFLICT              (63 - 13)
    544#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
    545#define TEXASR_IMPLEMENTATION_SPECIFIC           (63 - 15)
    546#define TEXASR_INSTRUCTION_FETCH_CONFLICT        (63 - 16)
    547#define TEXASR_ABORT                             (63 - 31)
    548#define TEXASR_SUSPENDED                         (63 - 32)
    549#define TEXASR_PRIVILEGE_HV                      (63 - 34)
    550#define TEXASR_PRIVILEGE_PR                      (63 - 35)
    551#define TEXASR_FAILURE_SUMMARY                   (63 - 36)
    552#define TEXASR_TFIAR_EXACT                       (63 - 37)
    553#define TEXASR_ROT                               (63 - 38)
    554#define TEXASR_TRANSACTION_LEVEL                 (63 - 52) /* 12 bits */
    555
    556enum {
    557    POWERPC_FLAG_NONE     = 0x00000000,
    558    /* Flag for MSR bit 25 signification (VRE/SPE)                           */
    559    POWERPC_FLAG_SPE      = 0x00000001,
    560    POWERPC_FLAG_VRE      = 0x00000002,
    561    /* Flag for MSR bit 17 signification (TGPR/CE)                           */
    562    POWERPC_FLAG_TGPR     = 0x00000004,
    563    POWERPC_FLAG_CE       = 0x00000008,
    564    /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
    565    POWERPC_FLAG_SE       = 0x00000010,
    566    POWERPC_FLAG_DWE      = 0x00000020,
    567    POWERPC_FLAG_UBLE     = 0x00000040,
    568    /* Flag for MSR bit 9 signification (BE/DE)                              */
    569    POWERPC_FLAG_BE       = 0x00000080,
    570    POWERPC_FLAG_DE       = 0x00000100,
    571    /* Flag for MSR bit 2 signification (PX/PMM)                             */
    572    POWERPC_FLAG_PX       = 0x00000200,
    573    POWERPC_FLAG_PMM      = 0x00000400,
    574    /* Flag for special features                                             */
    575    /* Decrementer clock: RTC clock (POWER, 601) or bus clock                */
    576    POWERPC_FLAG_RTC_CLK  = 0x00010000,
    577    POWERPC_FLAG_BUS_CLK  = 0x00020000,
    578    /* Has CFAR                                                              */
    579    POWERPC_FLAG_CFAR     = 0x00040000,
    580    /* Has VSX                                                               */
    581    POWERPC_FLAG_VSX      = 0x00080000,
    582    /* Has Transaction Memory (ISA 2.07)                                     */
    583    POWERPC_FLAG_TM       = 0x00100000,
    584    /* Has SCV (ISA 3.00)                                                    */
    585    POWERPC_FLAG_SCV      = 0x00200000,
    586    /* Has HID0 for LE bit (601)                                             */
    587    POWERPC_FLAG_HID0_LE  = 0x00400000,
    588};
    589
    590/*
    591 * Bits for env->hflags.
    592 *
    593 * Most of these bits overlap with corresponding bits in MSR,
    594 * but some come from other sources.  Those that do come from
    595 * the MSR are validated in hreg_compute_hflags.
    596 */
    597enum {
    598    HFLAGS_LE = 0,   /* MSR_LE -- comes from elsewhere on 601 */
    599    HFLAGS_HV = 1,   /* computed from MSR_HV and other state */
    600    HFLAGS_64 = 2,   /* computed from MSR_CE and MSR_SF */
    601    HFLAGS_GTSE = 3, /* computed from SPR_LPCR[GTSE] */
    602    HFLAGS_DR = 4,   /* MSR_DR */
    603    HFLAGS_HR = 5,   /* computed from SPR_LPCR[HR] */
    604    HFLAGS_SPE = 6,  /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */
    605    HFLAGS_TM = 8,   /* computed from MSR_TM */
    606    HFLAGS_BE = 9,   /* MSR_BE -- from elsewhere on embedded ppc */
    607    HFLAGS_SE = 10,  /* MSR_SE -- from elsewhere on embedded ppc */
    608    HFLAGS_FP = 13,  /* MSR_FP */
    609    HFLAGS_PR = 14,  /* MSR_PR */
    610    HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */
    611    HFLAGS_VR = 25,  /* MSR_VR if cpu has VRE */
    612
    613    HFLAGS_IMMU_IDX = 26, /* 26..28 -- the composite immu_idx */
    614    HFLAGS_DMMU_IDX = 29, /* 29..31 -- the composite dmmu_idx */
    615};
    616
    617/*****************************************************************************/
    618/* Floating point status and control register                                */
    619#define FPSCR_DRN2   34 /* Decimal Floating-Point rounding control           */
    620#define FPSCR_DRN1   33 /* Decimal Floating-Point rounding control           */
    621#define FPSCR_DRN0   32 /* Decimal Floating-Point rounding control           */
    622#define FPSCR_FX     31 /* Floating-point exception summary                  */
    623#define FPSCR_FEX    30 /* Floating-point enabled exception summary          */
    624#define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */
    625#define FPSCR_OX     28 /* Floating-point overflow exception                 */
    626#define FPSCR_UX     27 /* Floating-point underflow exception                */
    627#define FPSCR_ZX     26 /* Floating-point zero divide exception              */
    628#define FPSCR_XX     25 /* Floating-point inexact exception                  */
    629#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
    630#define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */
    631#define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */
    632#define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */
    633#define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */
    634#define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */
    635#define FPSCR_FR     18 /* Floating-point fraction rounded                   */
    636#define FPSCR_FI     17 /* Floating-point fraction inexact                   */
    637#define FPSCR_C      16 /* Floating-point result class descriptor            */
    638#define FPSCR_FL     15 /* Floating-point less than or negative              */
    639#define FPSCR_FG     14 /* Floating-point greater than or negative           */
    640#define FPSCR_FE     13 /* Floating-point equal or zero                      */
    641#define FPSCR_FU     12 /* Floating-point unordered or NaN                   */
    642#define FPSCR_FPCC   12 /* Floating-point condition code                     */
    643#define FPSCR_FPRF   12 /* Floating-point result flags                       */
    644#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
    645#define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */
    646#define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
    647#define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
    648#define FPSCR_OE     6  /* Floating-point overflow exception enable          */
    649#define FPSCR_UE     5  /* Floating-point underflow exception enable          */
    650#define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
    651#define FPSCR_XE     3  /* Floating-point inexact exception enable           */
    652#define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
    653#define FPSCR_RN1    1
    654#define FPSCR_RN0    0  /* Floating-point rounding control                   */
    655#define fpscr_drn    (((env->fpscr) & FP_DRN) >> FPSCR_DRN0)
    656#define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)
    657#define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)
    658#define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)
    659#define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)
    660#define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)
    661#define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)
    662#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
    663#define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)
    664#define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)
    665#define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)
    666#define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)
    667#define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)
    668#define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)
    669#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
    670#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
    671#define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)
    672#define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)
    673#define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)
    674#define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)
    675#define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)
    676#define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)
    677#define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)
    678#define fpscr_rn     (((env->fpscr) >> FPSCR_RN0)    & 0x3)
    679/* Invalid operation exception summary */
    680#define FPSCR_IX     ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
    681                      (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
    682                      (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
    683                      (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
    684                      (1 << FPSCR_VXCVI))
    685/* exception summary */
    686#define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)
    687/* enabled exception summary */
    688#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
    689                   0x1F)
    690
    691#define FP_DRN2         (1ull << FPSCR_DRN2)
    692#define FP_DRN1         (1ull << FPSCR_DRN1)
    693#define FP_DRN0         (1ull << FPSCR_DRN0)
    694#define FP_DRN          (FP_DRN2 | FP_DRN1 | FP_DRN0)
    695#define FP_FX           (1ull << FPSCR_FX)
    696#define FP_FEX          (1ull << FPSCR_FEX)
    697#define FP_VX           (1ull << FPSCR_VX)
    698#define FP_OX           (1ull << FPSCR_OX)
    699#define FP_UX           (1ull << FPSCR_UX)
    700#define FP_ZX           (1ull << FPSCR_ZX)
    701#define FP_XX           (1ull << FPSCR_XX)
    702#define FP_VXSNAN       (1ull << FPSCR_VXSNAN)
    703#define FP_VXISI        (1ull << FPSCR_VXISI)
    704#define FP_VXIDI        (1ull << FPSCR_VXIDI)
    705#define FP_VXZDZ        (1ull << FPSCR_VXZDZ)
    706#define FP_VXIMZ        (1ull << FPSCR_VXIMZ)
    707#define FP_VXVC         (1ull << FPSCR_VXVC)
    708#define FP_FR           (1ull << FPSCR_FR)
    709#define FP_FI           (1ull << FPSCR_FI)
    710#define FP_C            (1ull << FPSCR_C)
    711#define FP_FL           (1ull << FPSCR_FL)
    712#define FP_FG           (1ull << FPSCR_FG)
    713#define FP_FE           (1ull << FPSCR_FE)
    714#define FP_FU           (1ull << FPSCR_FU)
    715#define FP_FPCC         (FP_FL | FP_FG | FP_FE | FP_FU)
    716#define FP_FPRF         (FP_C | FP_FPCC)
    717#define FP_VXSOFT       (1ull << FPSCR_VXSOFT)
    718#define FP_VXSQRT       (1ull << FPSCR_VXSQRT)
    719#define FP_VXCVI        (1ull << FPSCR_VXCVI)
    720#define FP_VE           (1ull << FPSCR_VE)
    721#define FP_OE           (1ull << FPSCR_OE)
    722#define FP_UE           (1ull << FPSCR_UE)
    723#define FP_ZE           (1ull << FPSCR_ZE)
    724#define FP_XE           (1ull << FPSCR_XE)
    725#define FP_NI           (1ull << FPSCR_NI)
    726#define FP_RN1          (1ull << FPSCR_RN1)
    727#define FP_RN0          (1ull << FPSCR_RN0)
    728#define FP_RN           (FP_RN1 | FP_RN0)
    729
    730#define FP_ENABLES      (FP_VE | FP_OE | FP_UE | FP_ZE | FP_XE)
    731#define FP_STATUS       (FP_FR | FP_FI | FP_FPRF)
    732
    733/* the exception bits which can be cleared by mcrfs - includes FX */
    734#define FP_EX_CLEAR_BITS (FP_FX     | FP_OX     | FP_UX     | FP_ZX     | \
    735                          FP_XX     | FP_VXSNAN | FP_VXISI  | FP_VXIDI  | \
    736                          FP_VXZDZ  | FP_VXIMZ  | FP_VXVC   | FP_VXSOFT | \
    737                          FP_VXSQRT | FP_VXCVI)
    738
    739/*****************************************************************************/
    740/* Vector status and control register */
    741#define VSCR_NJ         16 /* Vector non-java */
    742#define VSCR_SAT        0 /* Vector saturation */
    743
    744/*****************************************************************************/
    745/* BookE e500 MMU registers */
    746
    747#define MAS0_NV_SHIFT      0
    748#define MAS0_NV_MASK       (0xfff << MAS0_NV_SHIFT)
    749
    750#define MAS0_WQ_SHIFT      12
    751#define MAS0_WQ_MASK       (3 << MAS0_WQ_SHIFT)
    752/* Write TLB entry regardless of reservation */
    753#define MAS0_WQ_ALWAYS     (0 << MAS0_WQ_SHIFT)
    754/* Write TLB entry only already in use */
    755#define MAS0_WQ_COND       (1 << MAS0_WQ_SHIFT)
    756/* Clear TLB entry */
    757#define MAS0_WQ_CLR_RSRV   (2 << MAS0_WQ_SHIFT)
    758
    759#define MAS0_HES_SHIFT     14
    760#define MAS0_HES           (1 << MAS0_HES_SHIFT)
    761
    762#define MAS0_ESEL_SHIFT    16
    763#define MAS0_ESEL_MASK     (0xfff << MAS0_ESEL_SHIFT)
    764
    765#define MAS0_TLBSEL_SHIFT  28
    766#define MAS0_TLBSEL_MASK   (3 << MAS0_TLBSEL_SHIFT)
    767#define MAS0_TLBSEL_TLB0   (0 << MAS0_TLBSEL_SHIFT)
    768#define MAS0_TLBSEL_TLB1   (1 << MAS0_TLBSEL_SHIFT)
    769#define MAS0_TLBSEL_TLB2   (2 << MAS0_TLBSEL_SHIFT)
    770#define MAS0_TLBSEL_TLB3   (3 << MAS0_TLBSEL_SHIFT)
    771
    772#define MAS0_ATSEL_SHIFT   31
    773#define MAS0_ATSEL         (1 << MAS0_ATSEL_SHIFT)
    774#define MAS0_ATSEL_TLB     0
    775#define MAS0_ATSEL_LRAT    MAS0_ATSEL
    776
    777#define MAS1_TSIZE_SHIFT   7
    778#define MAS1_TSIZE_MASK    (0x1f << MAS1_TSIZE_SHIFT)
    779
    780#define MAS1_TS_SHIFT      12
    781#define MAS1_TS            (1 << MAS1_TS_SHIFT)
    782
    783#define MAS1_IND_SHIFT     13
    784#define MAS1_IND           (1 << MAS1_IND_SHIFT)
    785
    786#define MAS1_TID_SHIFT     16
    787#define MAS1_TID_MASK      (0x3fff << MAS1_TID_SHIFT)
    788
    789#define MAS1_IPROT_SHIFT   30
    790#define MAS1_IPROT         (1 << MAS1_IPROT_SHIFT)
    791
    792#define MAS1_VALID_SHIFT   31
    793#define MAS1_VALID         0x80000000
    794
    795#define MAS2_EPN_SHIFT     12
    796#define MAS2_EPN_MASK      (~0ULL << MAS2_EPN_SHIFT)
    797
    798#define MAS2_ACM_SHIFT     6
    799#define MAS2_ACM           (1 << MAS2_ACM_SHIFT)
    800
    801#define MAS2_VLE_SHIFT     5
    802#define MAS2_VLE           (1 << MAS2_VLE_SHIFT)
    803
    804#define MAS2_W_SHIFT       4
    805#define MAS2_W             (1 << MAS2_W_SHIFT)
    806
    807#define MAS2_I_SHIFT       3
    808#define MAS2_I             (1 << MAS2_I_SHIFT)
    809
    810#define MAS2_M_SHIFT       2
    811#define MAS2_M             (1 << MAS2_M_SHIFT)
    812
    813#define MAS2_G_SHIFT       1
    814#define MAS2_G             (1 << MAS2_G_SHIFT)
    815
    816#define MAS2_E_SHIFT       0
    817#define MAS2_E             (1 << MAS2_E_SHIFT)
    818
    819#define MAS3_RPN_SHIFT     12
    820#define MAS3_RPN_MASK      (0xfffff << MAS3_RPN_SHIFT)
    821
    822#define MAS3_U0                 0x00000200
    823#define MAS3_U1                 0x00000100
    824#define MAS3_U2                 0x00000080
    825#define MAS3_U3                 0x00000040
    826#define MAS3_UX                 0x00000020
    827#define MAS3_SX                 0x00000010
    828#define MAS3_UW                 0x00000008
    829#define MAS3_SW                 0x00000004
    830#define MAS3_UR                 0x00000002
    831#define MAS3_SR                 0x00000001
    832#define MAS3_SPSIZE_SHIFT       1
    833#define MAS3_SPSIZE_MASK        (0x3e << MAS3_SPSIZE_SHIFT)
    834
    835#define MAS4_TLBSELD_SHIFT      MAS0_TLBSEL_SHIFT
    836#define MAS4_TLBSELD_MASK       MAS0_TLBSEL_MASK
    837#define MAS4_TIDSELD_MASK       0x00030000
    838#define MAS4_TIDSELD_PID0       0x00000000
    839#define MAS4_TIDSELD_PID1       0x00010000
    840#define MAS4_TIDSELD_PID2       0x00020000
    841#define MAS4_TIDSELD_PIDZ       0x00030000
    842#define MAS4_INDD               0x00008000      /* Default IND */
    843#define MAS4_TSIZED_SHIFT       MAS1_TSIZE_SHIFT
    844#define MAS4_TSIZED_MASK        MAS1_TSIZE_MASK
    845#define MAS4_ACMD               0x00000040
    846#define MAS4_VLED               0x00000020
    847#define MAS4_WD                 0x00000010
    848#define MAS4_ID                 0x00000008
    849#define MAS4_MD                 0x00000004
    850#define MAS4_GD                 0x00000002
    851#define MAS4_ED                 0x00000001
    852#define MAS4_WIMGED_MASK        0x0000001f      /* Default WIMGE */
    853#define MAS4_WIMGED_SHIFT       0
    854
    855#define MAS5_SGS                0x80000000
    856#define MAS5_SLPID_MASK         0x00000fff
    857
    858#define MAS6_SPID0              0x3fff0000
    859#define MAS6_SPID1              0x00007ffe
    860#define MAS6_ISIZE(x)           MAS1_TSIZE(x)
    861#define MAS6_SAS                0x00000001
    862#define MAS6_SPID               MAS6_SPID0
    863#define MAS6_SIND               0x00000002      /* Indirect page */
    864#define MAS6_SIND_SHIFT         1
    865#define MAS6_SPID_MASK          0x3fff0000
    866#define MAS6_SPID_SHIFT         16
    867#define MAS6_ISIZE_MASK         0x00000f80
    868#define MAS6_ISIZE_SHIFT        7
    869
    870#define MAS7_RPN                0xffffffff
    871
    872#define MAS8_TGS                0x80000000
    873#define MAS8_VF                 0x40000000
    874#define MAS8_TLBPID             0x00000fff
    875
    876/* Bit definitions for MMUCFG */
    877#define MMUCFG_MAVN     0x00000003      /* MMU Architecture Version Number */
    878#define MMUCFG_MAVN_V1  0x00000000      /* v1.0 */
    879#define MMUCFG_MAVN_V2  0x00000001      /* v2.0 */
    880#define MMUCFG_NTLBS    0x0000000c      /* Number of TLBs */
    881#define MMUCFG_PIDSIZE  0x000007c0      /* PID Reg Size */
    882#define MMUCFG_TWC      0x00008000      /* TLB Write Conditional (v2.0) */
    883#define MMUCFG_LRAT     0x00010000      /* LRAT Supported (v2.0) */
    884#define MMUCFG_RASIZE   0x00fe0000      /* Real Addr Size */
    885#define MMUCFG_LPIDSIZE 0x0f000000      /* LPID Reg Size */
    886
    887/* Bit definitions for MMUCSR0 */
    888#define MMUCSR0_TLB1FI  0x00000002      /* TLB1 Flash invalidate */
    889#define MMUCSR0_TLB0FI  0x00000004      /* TLB0 Flash invalidate */
    890#define MMUCSR0_TLB2FI  0x00000040      /* TLB2 Flash invalidate */
    891#define MMUCSR0_TLB3FI  0x00000020      /* TLB3 Flash invalidate */
    892#define MMUCSR0_TLBFI   (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
    893                         MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
    894#define MMUCSR0_TLB0PS  0x00000780      /* TLB0 Page Size */
    895#define MMUCSR0_TLB1PS  0x00007800      /* TLB1 Page Size */
    896#define MMUCSR0_TLB2PS  0x00078000      /* TLB2 Page Size */
    897#define MMUCSR0_TLB3PS  0x00780000      /* TLB3 Page Size */
    898
    899/* TLBnCFG encoding */
    900#define TLBnCFG_N_ENTRY         0x00000fff      /* number of entries */
    901#define TLBnCFG_HES             0x00002000      /* HW select supported */
    902#define TLBnCFG_AVAIL           0x00004000      /* variable page size */
    903#define TLBnCFG_IPROT           0x00008000      /* IPROT supported */
    904#define TLBnCFG_GTWE            0x00010000      /* Guest can write */
    905#define TLBnCFG_IND             0x00020000      /* IND entries supported */
    906#define TLBnCFG_PT              0x00040000      /* Can load from page table */
    907#define TLBnCFG_MINSIZE         0x00f00000      /* Minimum Page Size (v1.0) */
    908#define TLBnCFG_MINSIZE_SHIFT   20
    909#define TLBnCFG_MAXSIZE         0x000f0000      /* Maximum Page Size (v1.0) */
    910#define TLBnCFG_MAXSIZE_SHIFT   16
    911#define TLBnCFG_ASSOC           0xff000000      /* Associativity */
    912#define TLBnCFG_ASSOC_SHIFT     24
    913
    914/* TLBnPS encoding */
    915#define TLBnPS_4K               0x00000004
    916#define TLBnPS_8K               0x00000008
    917#define TLBnPS_16K              0x00000010
    918#define TLBnPS_32K              0x00000020
    919#define TLBnPS_64K              0x00000040
    920#define TLBnPS_128K             0x00000080
    921#define TLBnPS_256K             0x00000100
    922#define TLBnPS_512K             0x00000200
    923#define TLBnPS_1M               0x00000400
    924#define TLBnPS_2M               0x00000800
    925#define TLBnPS_4M               0x00001000
    926#define TLBnPS_8M               0x00002000
    927#define TLBnPS_16M              0x00004000
    928#define TLBnPS_32M              0x00008000
    929#define TLBnPS_64M              0x00010000
    930#define TLBnPS_128M             0x00020000
    931#define TLBnPS_256M             0x00040000
    932#define TLBnPS_512M             0x00080000
    933#define TLBnPS_1G               0x00100000
    934#define TLBnPS_2G               0x00200000
    935#define TLBnPS_4G               0x00400000
    936#define TLBnPS_8G               0x00800000
    937#define TLBnPS_16G              0x01000000
    938#define TLBnPS_32G              0x02000000
    939#define TLBnPS_64G              0x04000000
    940#define TLBnPS_128G             0x08000000
    941#define TLBnPS_256G             0x10000000
    942
    943/* tlbilx action encoding */
    944#define TLBILX_T_ALL                    0
    945#define TLBILX_T_TID                    1
    946#define TLBILX_T_FULLMATCH              3
    947#define TLBILX_T_CLASS0                 4
    948#define TLBILX_T_CLASS1                 5
    949#define TLBILX_T_CLASS2                 6
    950#define TLBILX_T_CLASS3                 7
    951
    952/* BookE 2.06 helper defines */
    953
    954#define BOOKE206_FLUSH_TLB0    (1 << 0)
    955#define BOOKE206_FLUSH_TLB1    (1 << 1)
    956#define BOOKE206_FLUSH_TLB2    (1 << 2)
    957#define BOOKE206_FLUSH_TLB3    (1 << 3)
    958
    959/* number of possible TLBs */
    960#define BOOKE206_MAX_TLBN      4
    961
    962#define EPID_EPID_SHIFT 0x0
    963#define EPID_EPID 0xFF
    964#define EPID_ELPID_SHIFT 0x10
    965#define EPID_ELPID 0x3F0000
    966#define EPID_EGS 0x20000000
    967#define EPID_EGS_SHIFT 29
    968#define EPID_EAS 0x40000000
    969#define EPID_EAS_SHIFT 30
    970#define EPID_EPR 0x80000000
    971#define EPID_EPR_SHIFT 31
    972/* We don't support EGS and ELPID */
    973#define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR)
    974
    975/*****************************************************************************/
    976/* Server and Embedded Processor Control */
    977
    978#define DBELL_TYPE_SHIFT               27
    979#define DBELL_TYPE_MASK                (0x1f << DBELL_TYPE_SHIFT)
    980#define DBELL_TYPE_DBELL               (0x00 << DBELL_TYPE_SHIFT)
    981#define DBELL_TYPE_DBELL_CRIT          (0x01 << DBELL_TYPE_SHIFT)
    982#define DBELL_TYPE_G_DBELL             (0x02 << DBELL_TYPE_SHIFT)
    983#define DBELL_TYPE_G_DBELL_CRIT        (0x03 << DBELL_TYPE_SHIFT)
    984#define DBELL_TYPE_G_DBELL_MC          (0x04 << DBELL_TYPE_SHIFT)
    985
    986#define DBELL_TYPE_DBELL_SERVER        (0x05 << DBELL_TYPE_SHIFT)
    987
    988#define DBELL_BRDCAST                  PPC_BIT(37)
    989#define DBELL_LPIDTAG_SHIFT            14
    990#define DBELL_LPIDTAG_MASK             (0xfff << DBELL_LPIDTAG_SHIFT)
    991#define DBELL_PIRTAG_MASK              0x3fff
    992
    993#define DBELL_PROCIDTAG_MASK           PPC_BITMASK(44, 63)
    994
    995#define PPC_PAGE_SIZES_MAX_SZ   8
    996
    997struct ppc_radix_page_info {
    998    uint32_t count;
    999    uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
   1000};
   1001
   1002/*****************************************************************************/
   1003/* The whole PowerPC CPU context */
   1004
   1005/*
   1006 * PowerPC needs eight modes for different hypervisor/supervisor/guest
   1007 * + real/paged mode combinations. The other two modes are for
   1008 * external PID load/store.
   1009 */
   1010#define PPC_TLB_EPID_LOAD 8
   1011#define PPC_TLB_EPID_STORE 9
   1012
   1013#define PPC_CPU_OPCODES_LEN          0x40
   1014#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
   1015
   1016struct CPUPPCState {
   1017    /* Most commonly used resources during translated code execution first */
   1018    target_ulong gpr[32];  /* general purpose registers */
   1019    target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */
   1020    target_ulong lr;
   1021    target_ulong ctr;
   1022    uint32_t crf[8];       /* condition register */
   1023#if defined(TARGET_PPC64)
   1024    target_ulong cfar;
   1025#endif
   1026    target_ulong xer;      /* XER (with SO, OV, CA split out) */
   1027    target_ulong so;
   1028    target_ulong ov;
   1029    target_ulong ca;
   1030    target_ulong ov32;
   1031    target_ulong ca32;
   1032
   1033    target_ulong reserve_addr; /* Reservation address */
   1034    target_ulong reserve_val;  /* Reservation value */
   1035    target_ulong reserve_val2;
   1036
   1037    /* These are used in supervisor mode only */
   1038    target_ulong msr;      /* machine state register */
   1039    target_ulong tgpr[4];  /* temporary general purpose registers, */
   1040                           /* used to speed-up TLB assist handlers */
   1041
   1042    target_ulong nip;      /* next instruction pointer */
   1043    uint64_t retxh;        /* high part of 128-bit helper return */
   1044
   1045    /* when a memory exception occurs, the access type is stored here */
   1046    int access_type;
   1047
   1048#if !defined(CONFIG_USER_ONLY)
   1049    /* MMU context, only relevant for full system emulation */
   1050#if defined(TARGET_PPC64)
   1051    ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */
   1052#endif
   1053    target_ulong sr[32];   /* segment registers */
   1054    uint32_t nb_BATs;      /* number of BATs */
   1055    target_ulong DBAT[2][8];
   1056    target_ulong IBAT[2][8];
   1057    /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
   1058    int32_t nb_tlb;  /* Total number of TLB */
   1059    int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
   1060    int nb_ways;     /* Number of ways in the TLB set */
   1061    int last_way;    /* Last used way used to allocate TLB in a LRU way */
   1062    int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
   1063    int nb_pids;     /* Number of available PID registers */
   1064    int tlb_type;    /* Type of TLB we're dealing with */
   1065    ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed */
   1066    target_ulong pb[4]; /* 403 dedicated access protection registers */
   1067    bool tlb_dirty;  /* Set to non-zero when modifying TLB */
   1068    bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
   1069    uint32_t tlb_need_flush; /* Delayed flush needed */
   1070#define TLB_NEED_LOCAL_FLUSH   0x1
   1071#define TLB_NEED_GLOBAL_FLUSH  0x2
   1072#endif
   1073
   1074    /* Other registers */
   1075    target_ulong spr[1024]; /* special purpose registers */
   1076    ppc_spr_t spr_cb[1024];
   1077    /* Vector status and control register, minus VSCR_SAT */
   1078    uint32_t vscr;
   1079    /* VSX registers (including FP and AVR) */
   1080    ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
   1081    /* Non-zero if and only if VSCR_SAT should be set */
   1082    ppc_vsr_t vscr_sat QEMU_ALIGNED(16);
   1083    /* SPE registers */
   1084    uint64_t spe_acc;
   1085    uint32_t spe_fscr;
   1086    /* SPE and Altivec share status as they'll never be used simultaneously */
   1087    float_status vec_status;
   1088    float_status fp_status; /* Floating point execution context */
   1089    target_ulong fpscr;     /* Floating point status and control register */
   1090
   1091    /* Internal devices resources */
   1092    ppc_tb_t *tb_env;      /* Time base and decrementer */
   1093    ppc_dcr_t *dcr_env;    /* Device control registers */
   1094
   1095    int dcache_line_size;
   1096    int icache_line_size;
   1097
   1098    /* These resources are used during exception processing */
   1099    /* CPU model definition */
   1100    target_ulong msr_mask;
   1101    powerpc_mmu_t mmu_model;
   1102    powerpc_excp_t excp_model;
   1103    powerpc_input_t bus_model;
   1104    int bfd_mach;
   1105    uint32_t flags;
   1106    uint64_t insns_flags;
   1107    uint64_t insns_flags2;
   1108
   1109    int error_code;
   1110    uint32_t pending_interrupts;
   1111#if !defined(CONFIG_USER_ONLY)
   1112    /*
   1113     * This is the IRQ controller, which is implementation dependent and only
   1114     * relevant when emulating a complete machine. Note that this isn't used
   1115     * by recent Book3s compatible CPUs (POWER7 and newer).
   1116     */
   1117    uint32_t irq_input_state;
   1118    void **irq_inputs;
   1119
   1120    target_ulong excp_vectors[POWERPC_EXCP_NB]; /* Exception vectors */
   1121    target_ulong excp_prefix;
   1122    target_ulong ivor_mask;
   1123    target_ulong ivpr_mask;
   1124    target_ulong hreset_vector;
   1125    hwaddr mpic_iack;
   1126    bool mpic_proxy;  /* true if the external proxy facility mode is enabled */
   1127    bool has_hv_mode; /* set when the processor has an HV mode, thus HV priv */
   1128                      /* instructions and SPRs are diallowed if MSR:HV is 0 */
   1129    /*
   1130     * On P7/P8/P9, set when in PM state so we need to handle resume in a
   1131     * special way (such as routing some resume causes to 0x100, i.e. sreset).
   1132     */
   1133    bool resume_as_sreset;
   1134#endif
   1135
   1136    /* These resources are used only in TCG */
   1137    uint32_t hflags;
   1138    target_ulong hflags_compat_nmsr; /* for migration compatibility */
   1139
   1140    /* Power management */
   1141    int (*check_pow)(CPUPPCState *env);
   1142
   1143#if !defined(CONFIG_USER_ONLY)
   1144    void *load_info;  /* holds boot loading state */
   1145#endif
   1146
   1147    /* booke timers */
   1148
   1149    /*
   1150     * Specifies bit locations of the Time Base used to signal a fixed timer
   1151     * exception on a transition from 0 to 1 (watchdog or fixed-interval timer)
   1152     *
   1153     * 0 selects the least significant bit, 63 selects the most significant bit
   1154     */
   1155    uint8_t fit_period[4];
   1156    uint8_t wdt_period[4];
   1157
   1158    /* Transactional memory state */
   1159    target_ulong tm_gpr[32];
   1160    ppc_avr_t tm_vsr[64];
   1161    uint64_t tm_cr;
   1162    uint64_t tm_lr;
   1163    uint64_t tm_ctr;
   1164    uint64_t tm_fpscr;
   1165    uint64_t tm_amr;
   1166    uint64_t tm_ppr;
   1167    uint64_t tm_vrsave;
   1168    uint32_t tm_vscr;
   1169    uint64_t tm_dscr;
   1170    uint64_t tm_tar;
   1171};
   1172
   1173#define SET_FIT_PERIOD(a_, b_, c_, d_)          \
   1174do {                                            \
   1175    env->fit_period[0] = (a_);                  \
   1176    env->fit_period[1] = (b_);                  \
   1177    env->fit_period[2] = (c_);                  \
   1178    env->fit_period[3] = (d_);                  \
   1179 } while (0)
   1180
   1181#define SET_WDT_PERIOD(a_, b_, c_, d_)          \
   1182do {                                            \
   1183    env->wdt_period[0] = (a_);                  \
   1184    env->wdt_period[1] = (b_);                  \
   1185    env->wdt_period[2] = (c_);                  \
   1186    env->wdt_period[3] = (d_);                  \
   1187 } while (0)
   1188
   1189typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
   1190typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
   1191
   1192/**
   1193 * PowerPCCPU:
   1194 * @env: #CPUPPCState
   1195 * @vcpu_id: vCPU identifier given to KVM
   1196 * @compat_pvr: Current logical PVR, zero if in "raw" mode
   1197 *
   1198 * A PowerPC CPU.
   1199 */
   1200struct PowerPCCPU {
   1201    /*< private >*/
   1202    CPUState parent_obj;
   1203    /*< public >*/
   1204
   1205    CPUNegativeOffsetState neg;
   1206    CPUPPCState env;
   1207
   1208    int vcpu_id;
   1209    uint32_t compat_pvr;
   1210    PPCVirtualHypervisor *vhyp;
   1211    void *machine_data;
   1212    int32_t node_id; /* NUMA node this CPU belongs to */
   1213    PPCHash64Options *hash64_opts;
   1214
   1215    /* Those resources are used only during code translation */
   1216    /* opcode handlers */
   1217    opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
   1218
   1219    /* Fields related to migration compatibility hacks */
   1220    bool pre_2_8_migration;
   1221    target_ulong mig_msr_mask;
   1222    uint64_t mig_insns_flags;
   1223    uint64_t mig_insns_flags2;
   1224    uint32_t mig_nb_BATs;
   1225    bool pre_2_10_migration;
   1226    bool pre_3_0_migration;
   1227    int32_t mig_slb_nr;
   1228};
   1229
   1230
   1231PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
   1232PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
   1233PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
   1234
   1235#ifndef CONFIG_USER_ONLY
   1236struct PPCVirtualHypervisorClass {
   1237    InterfaceClass parent;
   1238    void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
   1239    hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
   1240    const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
   1241                                         hwaddr ptex, int n);
   1242    void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
   1243                        const ppc_hash_pte64_t *hptes,
   1244                        hwaddr ptex, int n);
   1245    void (*hpte_set_c)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
   1246    void (*hpte_set_r)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
   1247    void (*get_pate)(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry);
   1248    target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
   1249    void (*cpu_exec_enter)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
   1250    void (*cpu_exec_exit)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
   1251};
   1252
   1253#define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
   1254DECLARE_OBJ_CHECKERS(PPCVirtualHypervisor, PPCVirtualHypervisorClass,
   1255                     PPC_VIRTUAL_HYPERVISOR, TYPE_PPC_VIRTUAL_HYPERVISOR)
   1256#endif /* CONFIG_USER_ONLY */
   1257
   1258void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
   1259hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
   1260int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
   1261int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg);
   1262int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
   1263int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
   1264#ifndef CONFIG_USER_ONLY
   1265void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu);
   1266const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name);
   1267#endif
   1268int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
   1269                               int cpuid, void *opaque);
   1270int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
   1271                               int cpuid, void *opaque);
   1272#ifndef CONFIG_USER_ONLY
   1273void ppc_cpu_do_interrupt(CPUState *cpu);
   1274bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
   1275void ppc_cpu_do_system_reset(CPUState *cs);
   1276void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector);
   1277extern const VMStateDescription vmstate_ppc_cpu;
   1278#endif
   1279
   1280/*****************************************************************************/
   1281void ppc_translate_init(void);
   1282bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
   1283                      MMUAccessType access_type, int mmu_idx,
   1284                      bool probe, uintptr_t retaddr);
   1285
   1286#if !defined(CONFIG_USER_ONLY)
   1287void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
   1288#endif /* !defined(CONFIG_USER_ONLY) */
   1289void ppc_store_msr(CPUPPCState *env, target_ulong value);
   1290void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
   1291
   1292void ppc_cpu_list(void);
   1293
   1294/* Time-base and decrementer management */
   1295#ifndef NO_CPU_IO_DEFS
   1296uint64_t cpu_ppc_load_tbl(CPUPPCState *env);
   1297uint32_t cpu_ppc_load_tbu(CPUPPCState *env);
   1298void cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value);
   1299void cpu_ppc_store_tbl(CPUPPCState *env, uint32_t value);
   1300uint64_t cpu_ppc_load_atbl(CPUPPCState *env);
   1301uint32_t cpu_ppc_load_atbu(CPUPPCState *env);
   1302void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value);
   1303void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value);
   1304uint64_t cpu_ppc_load_vtb(CPUPPCState *env);
   1305void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value);
   1306bool ppc_decr_clear_on_delivery(CPUPPCState *env);
   1307target_ulong cpu_ppc_load_decr(CPUPPCState *env);
   1308void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
   1309target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
   1310void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
   1311void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value);
   1312uint64_t cpu_ppc_load_purr(CPUPPCState *env);
   1313void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
   1314uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env);
   1315uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env);
   1316#if !defined(CONFIG_USER_ONLY)
   1317void cpu_ppc601_store_rtcl(CPUPPCState *env, uint32_t value);
   1318void cpu_ppc601_store_rtcu(CPUPPCState *env, uint32_t value);
   1319target_ulong load_40x_pit(CPUPPCState *env);
   1320void store_40x_pit(CPUPPCState *env, target_ulong val);
   1321void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
   1322void store_40x_sler(CPUPPCState *env, uint32_t val);
   1323void store_booke_tcr(CPUPPCState *env, target_ulong val);
   1324void store_booke_tsr(CPUPPCState *env, target_ulong val);
   1325void ppc_tlb_invalidate_all(CPUPPCState *env);
   1326void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr);
   1327void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
   1328int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
   1329                            hwaddr *raddrp, target_ulong address,
   1330                            uint32_t pid);
   1331int ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb,
   1332                            hwaddr *raddrp,
   1333                            target_ulong address, uint32_t pid, int ext,
   1334                            int i);
   1335hwaddr booke206_tlb_to_page_size(CPUPPCState *env,
   1336                                        ppcmas_tlb_t *tlb);
   1337#endif
   1338#endif
   1339
   1340void ppc_store_fpscr(CPUPPCState *env, target_ulong val);
   1341void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
   1342                                 const char *caller, uint32_t cause);
   1343
   1344static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
   1345{
   1346    uint64_t gprv;
   1347
   1348    gprv = env->gpr[gprn];
   1349    if (env->flags & POWERPC_FLAG_SPE) {
   1350        /*
   1351         * If the CPU implements the SPE extension, we have to get the
   1352         * high bits of the GPR from the gprh storage area
   1353         */
   1354        gprv &= 0xFFFFFFFFULL;
   1355        gprv |= (uint64_t)env->gprh[gprn] << 32;
   1356    }
   1357
   1358    return gprv;
   1359}
   1360
   1361/* Device control registers */
   1362int ppc_dcr_read(ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
   1363int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
   1364
   1365#define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
   1366#define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
   1367#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
   1368
   1369#define cpu_list ppc_cpu_list
   1370
   1371/* MMU modes definitions */
   1372#define MMU_USER_IDX 0
   1373static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch)
   1374{
   1375#ifdef CONFIG_USER_ONLY
   1376    return MMU_USER_IDX;
   1377#else
   1378    return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7;
   1379#endif
   1380}
   1381
   1382/* Compatibility modes */
   1383#if defined(TARGET_PPC64)
   1384bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
   1385                      uint32_t min_compat_pvr, uint32_t max_compat_pvr);
   1386bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr,
   1387                           uint32_t min_compat_pvr, uint32_t max_compat_pvr);
   1388
   1389int ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
   1390
   1391#if !defined(CONFIG_USER_ONLY)
   1392int ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
   1393#endif
   1394int ppc_compat_max_vthreads(PowerPCCPU *cpu);
   1395void ppc_compat_add_property(Object *obj, const char *name,
   1396                             uint32_t *compat_pvr, const char *basedesc);
   1397#endif /* defined(TARGET_PPC64) */
   1398
   1399typedef CPUPPCState CPUArchState;
   1400typedef PowerPCCPU ArchCPU;
   1401
   1402#include "exec/cpu-all.h"
   1403
   1404/*****************************************************************************/
   1405/* CRF definitions */
   1406#define CRF_LT_BIT    3
   1407#define CRF_GT_BIT    2
   1408#define CRF_EQ_BIT    1
   1409#define CRF_SO_BIT    0
   1410#define CRF_LT        (1 << CRF_LT_BIT)
   1411#define CRF_GT        (1 << CRF_GT_BIT)
   1412#define CRF_EQ        (1 << CRF_EQ_BIT)
   1413#define CRF_SO        (1 << CRF_SO_BIT)
   1414/* For SPE extensions */
   1415#define CRF_CH        (1 << CRF_LT_BIT)
   1416#define CRF_CL        (1 << CRF_GT_BIT)
   1417#define CRF_CH_OR_CL  (1 << CRF_EQ_BIT)
   1418#define CRF_CH_AND_CL (1 << CRF_SO_BIT)
   1419
   1420/* XER definitions */
   1421#define XER_SO  31
   1422#define XER_OV  30
   1423#define XER_CA  29
   1424#define XER_OV32  19
   1425#define XER_CA32  18
   1426#define XER_CMP  8
   1427#define XER_BC   0
   1428#define xer_so  (env->so)
   1429#define xer_ov  (env->ov)
   1430#define xer_ca  (env->ca)
   1431#define xer_ov32  (env->ov)
   1432#define xer_ca32  (env->ca)
   1433#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
   1434#define xer_bc  ((env->xer >> XER_BC)  & 0x7F)
   1435
   1436/* SPR definitions */
   1437#define SPR_MQ                (0x000)
   1438#define SPR_XER               (0x001)
   1439#define SPR_601_VRTCU         (0x004)
   1440#define SPR_601_VRTCL         (0x005)
   1441#define SPR_601_UDECR         (0x006)
   1442#define SPR_LR                (0x008)
   1443#define SPR_CTR               (0x009)
   1444#define SPR_UAMR              (0x00D)
   1445#define SPR_DSCR              (0x011)
   1446#define SPR_DSISR             (0x012)
   1447#define SPR_DAR               (0x013) /* DAE for PowerPC 601 */
   1448#define SPR_601_RTCU          (0x014)
   1449#define SPR_601_RTCL          (0x015)
   1450#define SPR_DECR              (0x016)
   1451#define SPR_SDR1              (0x019)
   1452#define SPR_SRR0              (0x01A)
   1453#define SPR_SRR1              (0x01B)
   1454#define SPR_CFAR              (0x01C)
   1455#define SPR_AMR               (0x01D)
   1456#define SPR_ACOP              (0x01F)
   1457#define SPR_BOOKE_PID         (0x030)
   1458#define SPR_BOOKS_PID         (0x030)
   1459#define SPR_BOOKE_DECAR       (0x036)
   1460#define SPR_BOOKE_CSRR0       (0x03A)
   1461#define SPR_BOOKE_CSRR1       (0x03B)
   1462#define SPR_BOOKE_DEAR        (0x03D)
   1463#define SPR_IAMR              (0x03D)
   1464#define SPR_BOOKE_ESR         (0x03E)
   1465#define SPR_BOOKE_IVPR        (0x03F)
   1466#define SPR_MPC_EIE           (0x050)
   1467#define SPR_MPC_EID           (0x051)
   1468#define SPR_MPC_NRI           (0x052)
   1469#define SPR_TFHAR             (0x080)
   1470#define SPR_TFIAR             (0x081)
   1471#define SPR_TEXASR            (0x082)
   1472#define SPR_TEXASRU           (0x083)
   1473#define SPR_UCTRL             (0x088)
   1474#define SPR_TIDR              (0x090)
   1475#define SPR_MPC_CMPA          (0x090)
   1476#define SPR_MPC_CMPB          (0x091)
   1477#define SPR_MPC_CMPC          (0x092)
   1478#define SPR_MPC_CMPD          (0x093)
   1479#define SPR_MPC_ECR           (0x094)
   1480#define SPR_MPC_DER           (0x095)
   1481#define SPR_MPC_COUNTA        (0x096)
   1482#define SPR_MPC_COUNTB        (0x097)
   1483#define SPR_CTRL              (0x098)
   1484#define SPR_MPC_CMPE          (0x098)
   1485#define SPR_MPC_CMPF          (0x099)
   1486#define SPR_FSCR              (0x099)
   1487#define SPR_MPC_CMPG          (0x09A)
   1488#define SPR_MPC_CMPH          (0x09B)
   1489#define SPR_MPC_LCTRL1        (0x09C)
   1490#define SPR_MPC_LCTRL2        (0x09D)
   1491#define SPR_UAMOR             (0x09D)
   1492#define SPR_MPC_ICTRL         (0x09E)
   1493#define SPR_MPC_BAR           (0x09F)
   1494#define SPR_PSPB              (0x09F)
   1495#define SPR_DPDES             (0x0B0)
   1496#define SPR_DAWR0             (0x0B4)
   1497#define SPR_RPR               (0x0BA)
   1498#define SPR_CIABR             (0x0BB)
   1499#define SPR_DAWRX0            (0x0BC)
   1500#define SPR_HFSCR             (0x0BE)
   1501#define SPR_VRSAVE            (0x100)
   1502#define SPR_USPRG0            (0x100)
   1503#define SPR_USPRG1            (0x101)
   1504#define SPR_USPRG2            (0x102)
   1505#define SPR_USPRG3            (0x103)
   1506#define SPR_USPRG4            (0x104)
   1507#define SPR_USPRG5            (0x105)
   1508#define SPR_USPRG6            (0x106)
   1509#define SPR_USPRG7            (0x107)
   1510#define SPR_VTBL              (0x10C)
   1511#define SPR_VTBU              (0x10D)
   1512#define SPR_SPRG0             (0x110)
   1513#define SPR_SPRG1             (0x111)
   1514#define SPR_SPRG2             (0x112)
   1515#define SPR_SPRG3             (0x113)
   1516#define SPR_SPRG4             (0x114)
   1517#define SPR_SCOMC             (0x114)
   1518#define SPR_SPRG5             (0x115)
   1519#define SPR_SCOMD             (0x115)
   1520#define SPR_SPRG6             (0x116)
   1521#define SPR_SPRG7             (0x117)
   1522#define SPR_ASR               (0x118)
   1523#define SPR_EAR               (0x11A)
   1524#define SPR_TBL               (0x11C)
   1525#define SPR_TBU               (0x11D)
   1526#define SPR_TBU40             (0x11E)
   1527#define SPR_SVR               (0x11E)
   1528#define SPR_BOOKE_PIR         (0x11E)
   1529#define SPR_PVR               (0x11F)
   1530#define SPR_HSPRG0            (0x130)
   1531#define SPR_BOOKE_DBSR        (0x130)
   1532#define SPR_HSPRG1            (0x131)
   1533#define SPR_HDSISR            (0x132)
   1534#define SPR_HDAR              (0x133)
   1535#define SPR_BOOKE_EPCR        (0x133)
   1536#define SPR_SPURR             (0x134)
   1537#define SPR_BOOKE_DBCR0       (0x134)
   1538#define SPR_IBCR              (0x135)
   1539#define SPR_PURR              (0x135)
   1540#define SPR_BOOKE_DBCR1       (0x135)
   1541#define SPR_DBCR              (0x136)
   1542#define SPR_HDEC              (0x136)
   1543#define SPR_BOOKE_DBCR2       (0x136)
   1544#define SPR_HIOR              (0x137)
   1545#define SPR_MBAR              (0x137)
   1546#define SPR_RMOR              (0x138)
   1547#define SPR_BOOKE_IAC1        (0x138)
   1548#define SPR_HRMOR             (0x139)
   1549#define SPR_BOOKE_IAC2        (0x139)
   1550#define SPR_HSRR0             (0x13A)
   1551#define SPR_BOOKE_IAC3        (0x13A)
   1552#define SPR_HSRR1             (0x13B)
   1553#define SPR_BOOKE_IAC4        (0x13B)
   1554#define SPR_BOOKE_DAC1        (0x13C)
   1555#define SPR_MMCRH             (0x13C)
   1556#define SPR_DABR2             (0x13D)
   1557#define SPR_BOOKE_DAC2        (0x13D)
   1558#define SPR_TFMR              (0x13D)
   1559#define SPR_BOOKE_DVC1        (0x13E)
   1560#define SPR_LPCR              (0x13E)
   1561#define SPR_BOOKE_DVC2        (0x13F)
   1562#define SPR_LPIDR             (0x13F)
   1563#define SPR_BOOKE_TSR         (0x150)
   1564#define SPR_HMER              (0x150)
   1565#define SPR_HMEER             (0x151)
   1566#define SPR_PCR               (0x152)
   1567#define SPR_BOOKE_LPIDR       (0x152)
   1568#define SPR_BOOKE_TCR         (0x154)
   1569#define SPR_BOOKE_TLB0PS      (0x158)
   1570#define SPR_BOOKE_TLB1PS      (0x159)
   1571#define SPR_BOOKE_TLB2PS      (0x15A)
   1572#define SPR_BOOKE_TLB3PS      (0x15B)
   1573#define SPR_AMOR              (0x15D)
   1574#define SPR_BOOKE_MAS7_MAS3   (0x174)
   1575#define SPR_BOOKE_IVOR0       (0x190)
   1576#define SPR_BOOKE_IVOR1       (0x191)
   1577#define SPR_BOOKE_IVOR2       (0x192)
   1578#define SPR_BOOKE_IVOR3       (0x193)
   1579#define SPR_BOOKE_IVOR4       (0x194)
   1580#define SPR_BOOKE_IVOR5       (0x195)
   1581#define SPR_BOOKE_IVOR6       (0x196)
   1582#define SPR_BOOKE_IVOR7       (0x197)
   1583#define SPR_BOOKE_IVOR8       (0x198)
   1584#define SPR_BOOKE_IVOR9       (0x199)
   1585#define SPR_BOOKE_IVOR10      (0x19A)
   1586#define SPR_BOOKE_IVOR11      (0x19B)
   1587#define SPR_BOOKE_IVOR12      (0x19C)
   1588#define SPR_BOOKE_IVOR13      (0x19D)
   1589#define SPR_BOOKE_IVOR14      (0x19E)
   1590#define SPR_BOOKE_IVOR15      (0x19F)
   1591#define SPR_BOOKE_IVOR38      (0x1B0)
   1592#define SPR_BOOKE_IVOR39      (0x1B1)
   1593#define SPR_BOOKE_IVOR40      (0x1B2)
   1594#define SPR_BOOKE_IVOR41      (0x1B3)
   1595#define SPR_BOOKE_IVOR42      (0x1B4)
   1596#define SPR_BOOKE_GIVOR2      (0x1B8)
   1597#define SPR_BOOKE_GIVOR3      (0x1B9)
   1598#define SPR_BOOKE_GIVOR4      (0x1BA)
   1599#define SPR_BOOKE_GIVOR8      (0x1BB)
   1600#define SPR_BOOKE_GIVOR13     (0x1BC)
   1601#define SPR_BOOKE_GIVOR14     (0x1BD)
   1602#define SPR_TIR               (0x1BE)
   1603#define SPR_PTCR              (0x1D0)
   1604#define SPR_BOOKE_SPEFSCR     (0x200)
   1605#define SPR_Exxx_BBEAR        (0x201)
   1606#define SPR_Exxx_BBTAR        (0x202)
   1607#define SPR_Exxx_L1CFG0       (0x203)
   1608#define SPR_Exxx_L1CFG1       (0x204)
   1609#define SPR_Exxx_NPIDR        (0x205)
   1610#define SPR_ATBL              (0x20E)
   1611#define SPR_ATBU              (0x20F)
   1612#define SPR_IBAT0U            (0x210)
   1613#define SPR_BOOKE_IVOR32      (0x210)
   1614#define SPR_RCPU_MI_GRA       (0x210)
   1615#define SPR_IBAT0L            (0x211)
   1616#define SPR_BOOKE_IVOR33      (0x211)
   1617#define SPR_IBAT1U            (0x212)
   1618#define SPR_BOOKE_IVOR34      (0x212)
   1619#define SPR_IBAT1L            (0x213)
   1620#define SPR_BOOKE_IVOR35      (0x213)
   1621#define SPR_IBAT2U            (0x214)
   1622#define SPR_BOOKE_IVOR36      (0x214)
   1623#define SPR_IBAT2L            (0x215)
   1624#define SPR_BOOKE_IVOR37      (0x215)
   1625#define SPR_IBAT3U            (0x216)
   1626#define SPR_IBAT3L            (0x217)
   1627#define SPR_DBAT0U            (0x218)
   1628#define SPR_RCPU_L2U_GRA      (0x218)
   1629#define SPR_DBAT0L            (0x219)
   1630#define SPR_DBAT1U            (0x21A)
   1631#define SPR_DBAT1L            (0x21B)
   1632#define SPR_DBAT2U            (0x21C)
   1633#define SPR_DBAT2L            (0x21D)
   1634#define SPR_DBAT3U            (0x21E)
   1635#define SPR_DBAT3L            (0x21F)
   1636#define SPR_IBAT4U            (0x230)
   1637#define SPR_RPCU_BBCMCR       (0x230)
   1638#define SPR_MPC_IC_CST        (0x230)
   1639#define SPR_Exxx_CTXCR        (0x230)
   1640#define SPR_IBAT4L            (0x231)
   1641#define SPR_MPC_IC_ADR        (0x231)
   1642#define SPR_Exxx_DBCR3        (0x231)
   1643#define SPR_IBAT5U            (0x232)
   1644#define SPR_MPC_IC_DAT        (0x232)
   1645#define SPR_Exxx_DBCNT        (0x232)
   1646#define SPR_IBAT5L            (0x233)
   1647#define SPR_IBAT6U            (0x234)
   1648#define SPR_IBAT6L            (0x235)
   1649#define SPR_IBAT7U            (0x236)
   1650#define SPR_IBAT7L            (0x237)
   1651#define SPR_DBAT4U            (0x238)
   1652#define SPR_RCPU_L2U_MCR      (0x238)
   1653#define SPR_MPC_DC_CST        (0x238)
   1654#define SPR_Exxx_ALTCTXCR     (0x238)
   1655#define SPR_DBAT4L            (0x239)
   1656#define SPR_MPC_DC_ADR        (0x239)
   1657#define SPR_DBAT5U            (0x23A)
   1658#define SPR_BOOKE_MCSRR0      (0x23A)
   1659#define SPR_MPC_DC_DAT        (0x23A)
   1660#define SPR_DBAT5L            (0x23B)
   1661#define SPR_BOOKE_MCSRR1      (0x23B)
   1662#define SPR_DBAT6U            (0x23C)
   1663#define SPR_BOOKE_MCSR        (0x23C)
   1664#define SPR_DBAT6L            (0x23D)
   1665#define SPR_Exxx_MCAR         (0x23D)
   1666#define SPR_DBAT7U            (0x23E)
   1667#define SPR_BOOKE_DSRR0       (0x23E)
   1668#define SPR_DBAT7L            (0x23F)
   1669#define SPR_BOOKE_DSRR1       (0x23F)
   1670#define SPR_BOOKE_SPRG8       (0x25C)
   1671#define SPR_BOOKE_SPRG9       (0x25D)
   1672#define SPR_BOOKE_MAS0        (0x270)
   1673#define SPR_BOOKE_MAS1        (0x271)
   1674#define SPR_BOOKE_MAS2        (0x272)
   1675#define SPR_BOOKE_MAS3        (0x273)
   1676#define SPR_BOOKE_MAS4        (0x274)
   1677#define SPR_BOOKE_MAS5        (0x275)
   1678#define SPR_BOOKE_MAS6        (0x276)
   1679#define SPR_BOOKE_PID1        (0x279)
   1680#define SPR_BOOKE_PID2        (0x27A)
   1681#define SPR_MPC_DPDR          (0x280)
   1682#define SPR_MPC_IMMR          (0x288)
   1683#define SPR_BOOKE_TLB0CFG     (0x2B0)
   1684#define SPR_BOOKE_TLB1CFG     (0x2B1)
   1685#define SPR_BOOKE_TLB2CFG     (0x2B2)
   1686#define SPR_BOOKE_TLB3CFG     (0x2B3)
   1687#define SPR_BOOKE_EPR         (0x2BE)
   1688#define SPR_PERF0             (0x300)
   1689#define SPR_RCPU_MI_RBA0      (0x300)
   1690#define SPR_MPC_MI_CTR        (0x300)
   1691#define SPR_POWER_USIER       (0x300)
   1692#define SPR_PERF1             (0x301)
   1693#define SPR_RCPU_MI_RBA1      (0x301)
   1694#define SPR_POWER_UMMCR2      (0x301)
   1695#define SPR_PERF2             (0x302)
   1696#define SPR_RCPU_MI_RBA2      (0x302)
   1697#define SPR_MPC_MI_AP         (0x302)
   1698#define SPR_POWER_UMMCRA      (0x302)
   1699#define SPR_PERF3             (0x303)
   1700#define SPR_RCPU_MI_RBA3      (0x303)
   1701#define SPR_MPC_MI_EPN        (0x303)
   1702#define SPR_POWER_UPMC1       (0x303)
   1703#define SPR_PERF4             (0x304)
   1704#define SPR_POWER_UPMC2       (0x304)
   1705#define SPR_PERF5             (0x305)
   1706#define SPR_MPC_MI_TWC        (0x305)
   1707#define SPR_POWER_UPMC3       (0x305)
   1708#define SPR_PERF6             (0x306)
   1709#define SPR_MPC_MI_RPN        (0x306)
   1710#define SPR_POWER_UPMC4       (0x306)
   1711#define SPR_PERF7             (0x307)
   1712#define SPR_POWER_UPMC5       (0x307)
   1713#define SPR_PERF8             (0x308)
   1714#define SPR_RCPU_L2U_RBA0     (0x308)
   1715#define SPR_MPC_MD_CTR        (0x308)
   1716#define SPR_POWER_UPMC6       (0x308)
   1717#define SPR_PERF9             (0x309)
   1718#define SPR_RCPU_L2U_RBA1     (0x309)
   1719#define SPR_MPC_MD_CASID      (0x309)
   1720#define SPR_970_UPMC7         (0X309)
   1721#define SPR_PERFA             (0x30A)
   1722#define SPR_RCPU_L2U_RBA2     (0x30A)
   1723#define SPR_MPC_MD_AP         (0x30A)
   1724#define SPR_970_UPMC8         (0X30A)
   1725#define SPR_PERFB             (0x30B)
   1726#define SPR_RCPU_L2U_RBA3     (0x30B)
   1727#define SPR_MPC_MD_EPN        (0x30B)
   1728#define SPR_POWER_UMMCR0      (0X30B)
   1729#define SPR_PERFC             (0x30C)
   1730#define SPR_MPC_MD_TWB        (0x30C)
   1731#define SPR_POWER_USIAR       (0X30C)
   1732#define SPR_PERFD             (0x30D)
   1733#define SPR_MPC_MD_TWC        (0x30D)
   1734#define SPR_POWER_USDAR       (0X30D)
   1735#define SPR_PERFE             (0x30E)
   1736#define SPR_MPC_MD_RPN        (0x30E)
   1737#define SPR_POWER_UMMCR1      (0X30E)
   1738#define SPR_PERFF             (0x30F)
   1739#define SPR_MPC_MD_TW         (0x30F)
   1740#define SPR_UPERF0            (0x310)
   1741#define SPR_POWER_SIER        (0x310)
   1742#define SPR_UPERF1            (0x311)
   1743#define SPR_POWER_MMCR2       (0x311)
   1744#define SPR_UPERF2            (0x312)
   1745#define SPR_POWER_MMCRA       (0X312)
   1746#define SPR_UPERF3            (0x313)
   1747#define SPR_POWER_PMC1        (0X313)
   1748#define SPR_UPERF4            (0x314)
   1749#define SPR_POWER_PMC2        (0X314)
   1750#define SPR_UPERF5            (0x315)
   1751#define SPR_POWER_PMC3        (0X315)
   1752#define SPR_UPERF6            (0x316)
   1753#define SPR_POWER_PMC4        (0X316)
   1754#define SPR_UPERF7            (0x317)
   1755#define SPR_POWER_PMC5        (0X317)
   1756#define SPR_UPERF8            (0x318)
   1757#define SPR_POWER_PMC6        (0X318)
   1758#define SPR_UPERF9            (0x319)
   1759#define SPR_970_PMC7          (0X319)
   1760#define SPR_UPERFA            (0x31A)
   1761#define SPR_970_PMC8          (0X31A)
   1762#define SPR_UPERFB            (0x31B)
   1763#define SPR_POWER_MMCR0       (0X31B)
   1764#define SPR_UPERFC            (0x31C)
   1765#define SPR_POWER_SIAR        (0X31C)
   1766#define SPR_UPERFD            (0x31D)
   1767#define SPR_POWER_SDAR        (0X31D)
   1768#define SPR_UPERFE            (0x31E)
   1769#define SPR_POWER_MMCR1       (0X31E)
   1770#define SPR_UPERFF            (0x31F)
   1771#define SPR_RCPU_MI_RA0       (0x320)
   1772#define SPR_MPC_MI_DBCAM      (0x320)
   1773#define SPR_BESCRS            (0x320)
   1774#define SPR_RCPU_MI_RA1       (0x321)
   1775#define SPR_MPC_MI_DBRAM0     (0x321)
   1776#define SPR_BESCRSU           (0x321)
   1777#define SPR_RCPU_MI_RA2       (0x322)
   1778#define SPR_MPC_MI_DBRAM1     (0x322)
   1779#define SPR_BESCRR            (0x322)
   1780#define SPR_RCPU_MI_RA3       (0x323)
   1781#define SPR_BESCRRU           (0x323)
   1782#define SPR_EBBHR             (0x324)
   1783#define SPR_EBBRR             (0x325)
   1784#define SPR_BESCR             (0x326)
   1785#define SPR_RCPU_L2U_RA0      (0x328)
   1786#define SPR_MPC_MD_DBCAM      (0x328)
   1787#define SPR_RCPU_L2U_RA1      (0x329)
   1788#define SPR_MPC_MD_DBRAM0     (0x329)
   1789#define SPR_RCPU_L2U_RA2      (0x32A)
   1790#define SPR_MPC_MD_DBRAM1     (0x32A)
   1791#define SPR_RCPU_L2U_RA3      (0x32B)
   1792#define SPR_TAR               (0x32F)
   1793#define SPR_ASDR              (0x330)
   1794#define SPR_IC                (0x350)
   1795#define SPR_VTB               (0x351)
   1796#define SPR_MMCRC             (0x353)
   1797#define SPR_PSSCR             (0x357)
   1798#define SPR_440_INV0          (0x370)
   1799#define SPR_440_INV1          (0x371)
   1800#define SPR_440_INV2          (0x372)
   1801#define SPR_440_INV3          (0x373)
   1802#define SPR_440_ITV0          (0x374)
   1803#define SPR_440_ITV1          (0x375)
   1804#define SPR_440_ITV2          (0x376)
   1805#define SPR_440_ITV3          (0x377)
   1806#define SPR_440_CCR1          (0x378)
   1807#define SPR_TACR              (0x378)
   1808#define SPR_TCSCR             (0x379)
   1809#define SPR_CSIGR             (0x37a)
   1810#define SPR_DCRIPR            (0x37B)
   1811#define SPR_POWER_SPMC1       (0x37C)
   1812#define SPR_POWER_SPMC2       (0x37D)
   1813#define SPR_POWER_MMCRS       (0x37E)
   1814#define SPR_WORT              (0x37F)
   1815#define SPR_PPR               (0x380)
   1816#define SPR_750_GQR0          (0x390)
   1817#define SPR_440_DNV0          (0x390)
   1818#define SPR_750_GQR1          (0x391)
   1819#define SPR_440_DNV1          (0x391)
   1820#define SPR_750_GQR2          (0x392)
   1821#define SPR_440_DNV2          (0x392)
   1822#define SPR_750_GQR3          (0x393)
   1823#define SPR_440_DNV3          (0x393)
   1824#define SPR_750_GQR4          (0x394)
   1825#define SPR_440_DTV0          (0x394)
   1826#define SPR_750_GQR5          (0x395)
   1827#define SPR_440_DTV1          (0x395)
   1828#define SPR_750_GQR6          (0x396)
   1829#define SPR_440_DTV2          (0x396)
   1830#define SPR_750_GQR7          (0x397)
   1831#define SPR_440_DTV3          (0x397)
   1832#define SPR_750_THRM4         (0x398)
   1833#define SPR_750CL_HID2        (0x398)
   1834#define SPR_440_DVLIM         (0x398)
   1835#define SPR_750_WPAR          (0x399)
   1836#define SPR_440_IVLIM         (0x399)
   1837#define SPR_TSCR              (0x399)
   1838#define SPR_750_DMAU          (0x39A)
   1839#define SPR_750_DMAL          (0x39B)
   1840#define SPR_440_RSTCFG        (0x39B)
   1841#define SPR_BOOKE_DCDBTRL     (0x39C)
   1842#define SPR_BOOKE_DCDBTRH     (0x39D)
   1843#define SPR_BOOKE_ICDBTRL     (0x39E)
   1844#define SPR_BOOKE_ICDBTRH     (0x39F)
   1845#define SPR_74XX_UMMCR2       (0x3A0)
   1846#define SPR_7XX_UPMC5         (0x3A1)
   1847#define SPR_7XX_UPMC6         (0x3A2)
   1848#define SPR_UBAMR             (0x3A7)
   1849#define SPR_7XX_UMMCR0        (0x3A8)
   1850#define SPR_7XX_UPMC1         (0x3A9)
   1851#define SPR_7XX_UPMC2         (0x3AA)
   1852#define SPR_7XX_USIAR         (0x3AB)
   1853#define SPR_7XX_UMMCR1        (0x3AC)
   1854#define SPR_7XX_UPMC3         (0x3AD)
   1855#define SPR_7XX_UPMC4         (0x3AE)
   1856#define SPR_USDA              (0x3AF)
   1857#define SPR_40x_ZPR           (0x3B0)
   1858#define SPR_BOOKE_MAS7        (0x3B0)
   1859#define SPR_74XX_MMCR2        (0x3B0)
   1860#define SPR_7XX_PMC5          (0x3B1)
   1861#define SPR_40x_PID           (0x3B1)
   1862#define SPR_7XX_PMC6          (0x3B2)
   1863#define SPR_440_MMUCR         (0x3B2)
   1864#define SPR_4xx_CCR0          (0x3B3)
   1865#define SPR_BOOKE_EPLC        (0x3B3)
   1866#define SPR_405_IAC3          (0x3B4)
   1867#define SPR_BOOKE_EPSC        (0x3B4)
   1868#define SPR_405_IAC4          (0x3B5)
   1869#define SPR_405_DVC1          (0x3B6)
   1870#define SPR_405_DVC2          (0x3B7)
   1871#define SPR_BAMR              (0x3B7)
   1872#define SPR_7XX_MMCR0         (0x3B8)
   1873#define SPR_7XX_PMC1          (0x3B9)
   1874#define SPR_40x_SGR           (0x3B9)
   1875#define SPR_7XX_PMC2          (0x3BA)
   1876#define SPR_40x_DCWR          (0x3BA)
   1877#define SPR_7XX_SIAR          (0x3BB)
   1878#define SPR_405_SLER          (0x3BB)
   1879#define SPR_7XX_MMCR1         (0x3BC)
   1880#define SPR_405_SU0R          (0x3BC)
   1881#define SPR_401_SKR           (0x3BC)
   1882#define SPR_7XX_PMC3          (0x3BD)
   1883#define SPR_405_DBCR1         (0x3BD)
   1884#define SPR_7XX_PMC4          (0x3BE)
   1885#define SPR_SDA               (0x3BF)
   1886#define SPR_403_VTBL          (0x3CC)
   1887#define SPR_403_VTBU          (0x3CD)
   1888#define SPR_DMISS             (0x3D0)
   1889#define SPR_DCMP              (0x3D1)
   1890#define SPR_HASH1             (0x3D2)
   1891#define SPR_HASH2             (0x3D3)
   1892#define SPR_BOOKE_ICDBDR      (0x3D3)
   1893#define SPR_TLBMISS           (0x3D4)
   1894#define SPR_IMISS             (0x3D4)
   1895#define SPR_40x_ESR           (0x3D4)
   1896#define SPR_PTEHI             (0x3D5)
   1897#define SPR_ICMP              (0x3D5)
   1898#define SPR_40x_DEAR          (0x3D5)
   1899#define SPR_PTELO             (0x3D6)
   1900#define SPR_RPA               (0x3D6)
   1901#define SPR_40x_EVPR          (0x3D6)
   1902#define SPR_L3PM              (0x3D7)
   1903#define SPR_403_CDBCR         (0x3D7)
   1904#define SPR_L3ITCR0           (0x3D8)
   1905#define SPR_TCR               (0x3D8)
   1906#define SPR_40x_TSR           (0x3D8)
   1907#define SPR_IBR               (0x3DA)
   1908#define SPR_40x_TCR           (0x3DA)
   1909#define SPR_ESASRR            (0x3DB)
   1910#define SPR_40x_PIT           (0x3DB)
   1911#define SPR_403_TBL           (0x3DC)
   1912#define SPR_403_TBU           (0x3DD)
   1913#define SPR_SEBR              (0x3DE)
   1914#define SPR_40x_SRR2          (0x3DE)
   1915#define SPR_SER               (0x3DF)
   1916#define SPR_40x_SRR3          (0x3DF)
   1917#define SPR_L3OHCR            (0x3E8)
   1918#define SPR_L3ITCR1           (0x3E9)
   1919#define SPR_L3ITCR2           (0x3EA)
   1920#define SPR_L3ITCR3           (0x3EB)
   1921#define SPR_HID0              (0x3F0)
   1922#define SPR_40x_DBSR          (0x3F0)
   1923#define SPR_HID1              (0x3F1)
   1924#define SPR_IABR              (0x3F2)
   1925#define SPR_40x_DBCR0         (0x3F2)
   1926#define SPR_601_HID2          (0x3F2)
   1927#define SPR_Exxx_L1CSR0       (0x3F2)
   1928#define SPR_ICTRL             (0x3F3)
   1929#define SPR_HID2              (0x3F3)
   1930#define SPR_750CL_HID4        (0x3F3)
   1931#define SPR_Exxx_L1CSR1       (0x3F3)
   1932#define SPR_440_DBDR          (0x3F3)
   1933#define SPR_LDSTDB            (0x3F4)
   1934#define SPR_750_TDCL          (0x3F4)
   1935#define SPR_40x_IAC1          (0x3F4)
   1936#define SPR_MMUCSR0           (0x3F4)
   1937#define SPR_970_HID4          (0x3F4)
   1938#define SPR_DABR              (0x3F5)
   1939#define DABR_MASK (~(target_ulong)0x7)
   1940#define SPR_Exxx_BUCSR        (0x3F5)
   1941#define SPR_40x_IAC2          (0x3F5)
   1942#define SPR_601_HID5          (0x3F5)
   1943#define SPR_40x_DAC1          (0x3F6)
   1944#define SPR_MSSCR0            (0x3F6)
   1945#define SPR_970_HID5          (0x3F6)
   1946#define SPR_MSSSR0            (0x3F7)
   1947#define SPR_MSSCR1            (0x3F7)
   1948#define SPR_DABRX             (0x3F7)
   1949#define SPR_40x_DAC2          (0x3F7)
   1950#define SPR_MMUCFG            (0x3F7)
   1951#define SPR_LDSTCR            (0x3F8)
   1952#define SPR_L2PMCR            (0x3F8)
   1953#define SPR_750FX_HID2        (0x3F8)
   1954#define SPR_Exxx_L1FINV0      (0x3F8)
   1955#define SPR_L2CR              (0x3F9)
   1956#define SPR_Exxx_L2CSR0       (0x3F9)
   1957#define SPR_L3CR              (0x3FA)
   1958#define SPR_750_TDCH          (0x3FA)
   1959#define SPR_IABR2             (0x3FA)
   1960#define SPR_40x_DCCR          (0x3FA)
   1961#define SPR_ICTC              (0x3FB)
   1962#define SPR_40x_ICCR          (0x3FB)
   1963#define SPR_THRM1             (0x3FC)
   1964#define SPR_403_PBL1          (0x3FC)
   1965#define SPR_SP                (0x3FD)
   1966#define SPR_THRM2             (0x3FD)
   1967#define SPR_403_PBU1          (0x3FD)
   1968#define SPR_604_HID13         (0x3FD)
   1969#define SPR_LT                (0x3FE)
   1970#define SPR_THRM3             (0x3FE)
   1971#define SPR_RCPU_FPECR        (0x3FE)
   1972#define SPR_403_PBL2          (0x3FE)
   1973#define SPR_PIR               (0x3FF)
   1974#define SPR_403_PBU2          (0x3FF)
   1975#define SPR_601_HID15         (0x3FF)
   1976#define SPR_604_HID15         (0x3FF)
   1977#define SPR_E500_SVR          (0x3FF)
   1978
   1979/* Disable MAS Interrupt Updates for Hypervisor */
   1980#define EPCR_DMIUH            (1 << 22)
   1981/* Disable Guest TLB Management Instructions */
   1982#define EPCR_DGTMI            (1 << 23)
   1983/* Guest Interrupt Computation Mode */
   1984#define EPCR_GICM             (1 << 24)
   1985/* Interrupt Computation Mode */
   1986#define EPCR_ICM              (1 << 25)
   1987/* Disable Embedded Hypervisor Debug */
   1988#define EPCR_DUVD             (1 << 26)
   1989/* Instruction Storage Interrupt Directed to Guest State */
   1990#define EPCR_ISIGS            (1 << 27)
   1991/* Data Storage Interrupt Directed to Guest State */
   1992#define EPCR_DSIGS            (1 << 28)
   1993/* Instruction TLB Error Interrupt Directed to Guest State */
   1994#define EPCR_ITLBGS           (1 << 29)
   1995/* Data TLB Error Interrupt Directed to Guest State */
   1996#define EPCR_DTLBGS           (1 << 30)
   1997/* External Input Interrupt Directed to Guest State */
   1998#define EPCR_EXTGS            (1 << 31)
   1999
   2000#define   L1CSR0_CPE    0x00010000  /* Data Cache Parity Enable */
   2001#define   L1CSR0_CUL    0x00000400  /* (D-)Cache Unable to Lock */
   2002#define   L1CSR0_DCLFR  0x00000100  /* D-Cache Lock Flash Reset */
   2003#define   L1CSR0_DCFI   0x00000002  /* Data Cache Flash Invalidate */
   2004#define   L1CSR0_DCE    0x00000001  /* Data Cache Enable */
   2005
   2006#define   L1CSR1_CPE    0x00010000  /* Instruction Cache Parity Enable */
   2007#define   L1CSR1_ICUL   0x00000400  /* I-Cache Unable to Lock */
   2008#define   L1CSR1_ICLFR  0x00000100  /* I-Cache Lock Flash Reset */
   2009#define   L1CSR1_ICFI   0x00000002  /* Instruction Cache Flash Invalidate */
   2010#define   L1CSR1_ICE    0x00000001  /* Instruction Cache Enable */
   2011
   2012/* E500 L2CSR0 */
   2013#define E500_L2CSR0_L2FI    (1 << 21)   /* L2 cache flash invalidate */
   2014#define E500_L2CSR0_L2FL    (1 << 11)   /* L2 cache flush */
   2015#define E500_L2CSR0_L2LFC   (1 << 10)   /* L2 cache lock flash clear */
   2016
   2017/* HID0 bits */
   2018#define HID0_DEEPNAP        (1 << 24)           /* pre-2.06 */
   2019#define HID0_DOZE           (1 << 23)           /* pre-2.06 */
   2020#define HID0_NAP            (1 << 22)           /* pre-2.06 */
   2021#define HID0_HILE           PPC_BIT(19) /* POWER8 */
   2022#define HID0_POWER9_HILE    PPC_BIT(4)
   2023
   2024/*****************************************************************************/
   2025/* PowerPC Instructions types definitions                                    */
   2026enum {
   2027    PPC_NONE           = 0x0000000000000000ULL,
   2028    /* PowerPC base instructions set                                         */
   2029    PPC_INSNS_BASE     = 0x0000000000000001ULL,
   2030    /*   integer operations instructions                                     */
   2031#define PPC_INTEGER PPC_INSNS_BASE
   2032    /*   flow control instructions                                           */
   2033#define PPC_FLOW    PPC_INSNS_BASE
   2034    /*   virtual memory instructions                                         */
   2035#define PPC_MEM     PPC_INSNS_BASE
   2036    /*   ld/st with reservation instructions                                 */
   2037#define PPC_RES     PPC_INSNS_BASE
   2038    /*   spr/msr access instructions                                         */
   2039#define PPC_MISC    PPC_INSNS_BASE
   2040    /* Deprecated instruction sets                                           */
   2041    /*   Original POWER instruction set                                      */
   2042    PPC_POWER          = 0x0000000000000002ULL,
   2043    /*   POWER2 instruction set extension                                    */
   2044    PPC_POWER2         = 0x0000000000000004ULL,
   2045    /*   Power RTC support                                                   */
   2046    PPC_POWER_RTC      = 0x0000000000000008ULL,
   2047    /*   Power-to-PowerPC bridge (601)                                       */
   2048    PPC_POWER_BR       = 0x0000000000000010ULL,
   2049    /* 64 bits PowerPC instruction set                                       */
   2050    PPC_64B            = 0x0000000000000020ULL,
   2051    /*   New 64 bits extensions (PowerPC 2.0x)                               */
   2052    PPC_64BX           = 0x0000000000000040ULL,
   2053    /*   64 bits hypervisor extensions                                       */
   2054    PPC_64H            = 0x0000000000000080ULL,
   2055    /*   New wait instruction (PowerPC 2.0x)                                 */
   2056    PPC_WAIT           = 0x0000000000000100ULL,
   2057    /*   Time base mftb instruction                                          */
   2058    PPC_MFTB           = 0x0000000000000200ULL,
   2059
   2060    /* Fixed-point unit extensions                                           */
   2061    /*   PowerPC 602 specific                                                */
   2062    PPC_602_SPEC       = 0x0000000000000400ULL,
   2063    /*   isel instruction                                                    */
   2064    PPC_ISEL           = 0x0000000000000800ULL,
   2065    /*   popcntb instruction                                                 */
   2066    PPC_POPCNTB        = 0x0000000000001000ULL,
   2067    /*   string load / store                                                 */
   2068    PPC_STRING         = 0x0000000000002000ULL,
   2069    /*   real mode cache inhibited load / store                              */
   2070    PPC_CILDST         = 0x0000000000004000ULL,
   2071
   2072    /* Floating-point unit extensions                                        */
   2073    /*   Optional floating point instructions                                */
   2074    PPC_FLOAT          = 0x0000000000010000ULL,
   2075    /* New floating-point extensions (PowerPC 2.0x)                          */
   2076    PPC_FLOAT_EXT      = 0x0000000000020000ULL,
   2077    PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
   2078    PPC_FLOAT_FRES     = 0x0000000000080000ULL,
   2079    PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
   2080    PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
   2081    PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
   2082    PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
   2083
   2084    /* Vector/SIMD extensions                                                */
   2085    /*   Altivec support                                                     */
   2086    PPC_ALTIVEC        = 0x0000000001000000ULL,
   2087    /*   PowerPC 2.03 SPE extension                                          */
   2088    PPC_SPE            = 0x0000000002000000ULL,
   2089    /*   PowerPC 2.03 SPE single-precision floating-point extension          */
   2090    PPC_SPE_SINGLE     = 0x0000000004000000ULL,
   2091    /*   PowerPC 2.03 SPE double-precision floating-point extension          */
   2092    PPC_SPE_DOUBLE     = 0x0000000008000000ULL,
   2093
   2094    /* Optional memory control instructions                                  */
   2095    PPC_MEM_TLBIA      = 0x0000000010000000ULL,
   2096    PPC_MEM_TLBIE      = 0x0000000020000000ULL,
   2097    PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
   2098    /*   sync instruction                                                    */
   2099    PPC_MEM_SYNC       = 0x0000000080000000ULL,
   2100    /*   eieio instruction                                                   */
   2101    PPC_MEM_EIEIO      = 0x0000000100000000ULL,
   2102
   2103    /* Cache control instructions                                            */
   2104    PPC_CACHE          = 0x0000000200000000ULL,
   2105    /*   icbi instruction                                                    */
   2106    PPC_CACHE_ICBI     = 0x0000000400000000ULL,
   2107    /*   dcbz instruction                                                    */
   2108    PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
   2109    /*   dcba instruction                                                    */
   2110    PPC_CACHE_DCBA     = 0x0000002000000000ULL,
   2111    /*   Freescale cache locking instructions                                */
   2112    PPC_CACHE_LOCK     = 0x0000004000000000ULL,
   2113
   2114    /* MMU related extensions                                                */
   2115    /*   external control instructions                                       */
   2116    PPC_EXTERN         = 0x0000010000000000ULL,
   2117    /*   segment register access instructions                                */
   2118    PPC_SEGMENT        = 0x0000020000000000ULL,
   2119    /*   PowerPC 6xx TLB management instructions                             */
   2120    PPC_6xx_TLB        = 0x0000040000000000ULL,
   2121    /* PowerPC 74xx TLB management instructions                              */
   2122    PPC_74xx_TLB       = 0x0000080000000000ULL,
   2123    /*   PowerPC 40x TLB management instructions                             */
   2124    PPC_40x_TLB        = 0x0000100000000000ULL,
   2125    /*   segment register access instructions for PowerPC 64 "bridge"        */
   2126    PPC_SEGMENT_64B    = 0x0000200000000000ULL,
   2127    /*   SLB management                                                      */
   2128    PPC_SLBI           = 0x0000400000000000ULL,
   2129
   2130    /* Embedded PowerPC dedicated instructions                               */
   2131    PPC_WRTEE          = 0x0001000000000000ULL,
   2132    /* PowerPC 40x exception model                                           */
   2133    PPC_40x_EXCP       = 0x0002000000000000ULL,
   2134    /* PowerPC 405 Mac instructions                                          */
   2135    PPC_405_MAC        = 0x0004000000000000ULL,
   2136    /* PowerPC 440 specific instructions                                     */
   2137    PPC_440_SPEC       = 0x0008000000000000ULL,
   2138    /* BookE (embedded) PowerPC specification                                */
   2139    PPC_BOOKE          = 0x0010000000000000ULL,
   2140    /* mfapidi instruction                                                   */
   2141    PPC_MFAPIDI        = 0x0020000000000000ULL,
   2142    /* tlbiva instruction                                                    */
   2143    PPC_TLBIVA         = 0x0040000000000000ULL,
   2144    /* tlbivax instruction                                                   */
   2145    PPC_TLBIVAX        = 0x0080000000000000ULL,
   2146    /* PowerPC 4xx dedicated instructions                                    */
   2147    PPC_4xx_COMMON     = 0x0100000000000000ULL,
   2148    /* PowerPC 40x ibct instructions                                         */
   2149    PPC_40x_ICBT       = 0x0200000000000000ULL,
   2150    /* rfmci is not implemented in all BookE PowerPC                         */
   2151    PPC_RFMCI          = 0x0400000000000000ULL,
   2152    /* rfdi instruction                                                      */
   2153    PPC_RFDI           = 0x0800000000000000ULL,
   2154    /* DCR accesses                                                          */
   2155    PPC_DCR            = 0x1000000000000000ULL,
   2156    /* DCR extended accesse                                                  */
   2157    PPC_DCRX           = 0x2000000000000000ULL,
   2158    /* user-mode DCR access, implemented in PowerPC 460                      */
   2159    PPC_DCRUX          = 0x4000000000000000ULL,
   2160    /* popcntw and popcntd instructions                                      */
   2161    PPC_POPCNTWD       = 0x8000000000000000ULL,
   2162
   2163#define PPC_TCG_INSNS  (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
   2164                        | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
   2165                        | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
   2166                        | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
   2167                        | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
   2168                        | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
   2169                        | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
   2170                        | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
   2171                        | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
   2172                        | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
   2173                        | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
   2174                        | PPC_MEM_SYNC | PPC_MEM_EIEIO \
   2175                        | PPC_CACHE | PPC_CACHE_ICBI \
   2176                        | PPC_CACHE_DCBZ \
   2177                        | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
   2178                        | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
   2179                        | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
   2180                        | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
   2181                        | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
   2182                        | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
   2183                        | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
   2184                        | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
   2185                        | PPC_POPCNTWD | PPC_CILDST)
   2186
   2187    /* extended type values */
   2188
   2189    /* BookE 2.06 PowerPC specification                                      */
   2190    PPC2_BOOKE206      = 0x0000000000000001ULL,
   2191    /* VSX (extensions to Altivec / VMX)                                     */
   2192    PPC2_VSX           = 0x0000000000000002ULL,
   2193    /* Decimal Floating Point (DFP)                                          */
   2194    PPC2_DFP           = 0x0000000000000004ULL,
   2195    /* Embedded.Processor Control                                            */
   2196    PPC2_PRCNTL        = 0x0000000000000008ULL,
   2197    /* Byte-reversed, indexed, double-word load and store                    */
   2198    PPC2_DBRX          = 0x0000000000000010ULL,
   2199    /* Book I 2.05 PowerPC specification                                     */
   2200    PPC2_ISA205        = 0x0000000000000020ULL,
   2201    /* VSX additions in ISA 2.07                                             */
   2202    PPC2_VSX207        = 0x0000000000000040ULL,
   2203    /* ISA 2.06B bpermd                                                      */
   2204    PPC2_PERM_ISA206   = 0x0000000000000080ULL,
   2205    /* ISA 2.06B divide extended variants                                    */
   2206    PPC2_DIVE_ISA206   = 0x0000000000000100ULL,
   2207    /* ISA 2.06B larx/stcx. instructions                                     */
   2208    PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
   2209    /* ISA 2.06B floating point integer conversion                           */
   2210    PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
   2211    /* ISA 2.06B floating point test instructions                            */
   2212    PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
   2213    /* ISA 2.07 bctar instruction                                            */
   2214    PPC2_BCTAR_ISA207  = 0x0000000000001000ULL,
   2215    /* ISA 2.07 load/store quadword                                          */
   2216    PPC2_LSQ_ISA207    = 0x0000000000002000ULL,
   2217    /* ISA 2.07 Altivec                                                      */
   2218    PPC2_ALTIVEC_207   = 0x0000000000004000ULL,
   2219    /* PowerISA 2.07 Book3s specification                                    */
   2220    PPC2_ISA207S       = 0x0000000000008000ULL,
   2221    /* Double precision floating point conversion for signed integer 64      */
   2222    PPC2_FP_CVT_S64    = 0x0000000000010000ULL,
   2223    /* Transactional Memory (ISA 2.07, Book II)                              */
   2224    PPC2_TM            = 0x0000000000020000ULL,
   2225    /* Server PM instructgions (ISA 2.06, Book III)                          */
   2226    PPC2_PM_ISA206     = 0x0000000000040000ULL,
   2227    /* POWER ISA 3.0                                                         */
   2228    PPC2_ISA300        = 0x0000000000080000ULL,
   2229    /* POWER ISA 3.1                                                         */
   2230    PPC2_ISA310        = 0x0000000000100000ULL,
   2231
   2232#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
   2233                        PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
   2234                        PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
   2235                        PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
   2236                        PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
   2237                        PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
   2238                        PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
   2239                        PPC2_ISA300 | PPC2_ISA310)
   2240};
   2241
   2242/*****************************************************************************/
   2243/*
   2244 * Memory access type :
   2245 * may be needed for precise access rights control and precise exceptions.
   2246 */
   2247enum {
   2248    /* Type of instruction that generated the access */
   2249    ACCESS_CODE  = 0x10, /* Code fetch access                */
   2250    ACCESS_INT   = 0x20, /* Integer load/store access        */
   2251    ACCESS_FLOAT = 0x30, /* floating point load/store access */
   2252    ACCESS_RES   = 0x40, /* load/store with reservation      */
   2253    ACCESS_EXT   = 0x50, /* external access                  */
   2254    ACCESS_CACHE = 0x60, /* Cache manipulation               */
   2255};
   2256
   2257/*
   2258 * Hardware interrupt sources:
   2259 *   all those exception can be raised simulteaneously
   2260 */
   2261/* Input pins definitions */
   2262enum {
   2263    /* 6xx bus input pins */
   2264    PPC6xx_INPUT_HRESET     = 0,
   2265    PPC6xx_INPUT_SRESET     = 1,
   2266    PPC6xx_INPUT_CKSTP_IN   = 2,
   2267    PPC6xx_INPUT_MCP        = 3,
   2268    PPC6xx_INPUT_SMI        = 4,
   2269    PPC6xx_INPUT_INT        = 5,
   2270    PPC6xx_INPUT_TBEN       = 6,
   2271    PPC6xx_INPUT_WAKEUP     = 7,
   2272    PPC6xx_INPUT_NB,
   2273};
   2274
   2275enum {
   2276    /* Embedded PowerPC input pins */
   2277    PPCBookE_INPUT_HRESET     = 0,
   2278    PPCBookE_INPUT_SRESET     = 1,
   2279    PPCBookE_INPUT_CKSTP_IN   = 2,
   2280    PPCBookE_INPUT_MCP        = 3,
   2281    PPCBookE_INPUT_SMI        = 4,
   2282    PPCBookE_INPUT_INT        = 5,
   2283    PPCBookE_INPUT_CINT       = 6,
   2284    PPCBookE_INPUT_NB,
   2285};
   2286
   2287enum {
   2288    /* PowerPC E500 input pins */
   2289    PPCE500_INPUT_RESET_CORE = 0,
   2290    PPCE500_INPUT_MCK        = 1,
   2291    PPCE500_INPUT_CINT       = 3,
   2292    PPCE500_INPUT_INT        = 4,
   2293    PPCE500_INPUT_DEBUG      = 6,
   2294    PPCE500_INPUT_NB,
   2295};
   2296
   2297enum {
   2298    /* PowerPC 40x input pins */
   2299    PPC40x_INPUT_RESET_CORE = 0,
   2300    PPC40x_INPUT_RESET_CHIP = 1,
   2301    PPC40x_INPUT_RESET_SYS  = 2,
   2302    PPC40x_INPUT_CINT       = 3,
   2303    PPC40x_INPUT_INT        = 4,
   2304    PPC40x_INPUT_HALT       = 5,
   2305    PPC40x_INPUT_DEBUG      = 6,
   2306    PPC40x_INPUT_NB,
   2307};
   2308
   2309enum {
   2310    /* RCPU input pins */
   2311    PPCRCPU_INPUT_PORESET   = 0,
   2312    PPCRCPU_INPUT_HRESET    = 1,
   2313    PPCRCPU_INPUT_SRESET    = 2,
   2314    PPCRCPU_INPUT_IRQ0      = 3,
   2315    PPCRCPU_INPUT_IRQ1      = 4,
   2316    PPCRCPU_INPUT_IRQ2      = 5,
   2317    PPCRCPU_INPUT_IRQ3      = 6,
   2318    PPCRCPU_INPUT_IRQ4      = 7,
   2319    PPCRCPU_INPUT_IRQ5      = 8,
   2320    PPCRCPU_INPUT_IRQ6      = 9,
   2321    PPCRCPU_INPUT_IRQ7      = 10,
   2322    PPCRCPU_INPUT_NB,
   2323};
   2324
   2325#if defined(TARGET_PPC64)
   2326enum {
   2327    /* PowerPC 970 input pins */
   2328    PPC970_INPUT_HRESET     = 0,
   2329    PPC970_INPUT_SRESET     = 1,
   2330    PPC970_INPUT_CKSTP      = 2,
   2331    PPC970_INPUT_TBEN       = 3,
   2332    PPC970_INPUT_MCP        = 4,
   2333    PPC970_INPUT_INT        = 5,
   2334    PPC970_INPUT_THINT      = 6,
   2335    PPC970_INPUT_NB,
   2336};
   2337
   2338enum {
   2339    /* POWER7 input pins */
   2340    POWER7_INPUT_INT        = 0,
   2341    /*
   2342     * POWER7 probably has other inputs, but we don't care about them
   2343     * for any existing machine.  We can wire these up when we need
   2344     * them
   2345     */
   2346    POWER7_INPUT_NB,
   2347};
   2348
   2349enum {
   2350    /* POWER9 input pins */
   2351    POWER9_INPUT_INT        = 0,
   2352    POWER9_INPUT_HINT       = 1,
   2353    POWER9_INPUT_NB,
   2354};
   2355#endif
   2356
   2357/* Hardware exceptions definitions */
   2358enum {
   2359    /* External hardware exception sources */
   2360    PPC_INTERRUPT_RESET     = 0,  /* Reset exception                      */
   2361    PPC_INTERRUPT_WAKEUP,         /* Wakeup exception                     */
   2362    PPC_INTERRUPT_MCK,            /* Machine check exception              */
   2363    PPC_INTERRUPT_EXT,            /* External interrupt                   */
   2364    PPC_INTERRUPT_SMI,            /* System management interrupt          */
   2365    PPC_INTERRUPT_CEXT,           /* Critical external interrupt          */
   2366    PPC_INTERRUPT_DEBUG,          /* External debug exception             */
   2367    PPC_INTERRUPT_THERM,          /* Thermal exception                    */
   2368    /* Internal hardware exception sources */
   2369    PPC_INTERRUPT_DECR,           /* Decrementer exception                */
   2370    PPC_INTERRUPT_HDECR,          /* Hypervisor decrementer exception     */
   2371    PPC_INTERRUPT_PIT,            /* Programmable interval timer interrupt */
   2372    PPC_INTERRUPT_FIT,            /* Fixed interval timer interrupt       */
   2373    PPC_INTERRUPT_WDT,            /* Watchdog timer interrupt             */
   2374    PPC_INTERRUPT_CDOORBELL,      /* Critical doorbell interrupt          */
   2375    PPC_INTERRUPT_DOORBELL,       /* Doorbell interrupt                   */
   2376    PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */
   2377    PPC_INTERRUPT_HMI,            /* Hypervisor Maintenance interrupt    */
   2378    PPC_INTERRUPT_HDOORBELL,      /* Hypervisor Doorbell interrupt        */
   2379    PPC_INTERRUPT_HVIRT,          /* Hypervisor virtualization interrupt  */
   2380};
   2381
   2382/* Processor Compatibility mask (PCR) */
   2383enum {
   2384    PCR_COMPAT_2_05     = PPC_BIT(62),
   2385    PCR_COMPAT_2_06     = PPC_BIT(61),
   2386    PCR_COMPAT_2_07     = PPC_BIT(60),
   2387    PCR_COMPAT_3_00     = PPC_BIT(59),
   2388    PCR_COMPAT_3_10     = PPC_BIT(58),
   2389    PCR_VEC_DIS         = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
   2390    PCR_VSX_DIS         = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
   2391    PCR_TM_DIS          = PPC_BIT(2), /* Trans. memory disable (POWER8) */
   2392};
   2393
   2394/* HMER/HMEER */
   2395enum {
   2396    HMER_MALFUNCTION_ALERT      = PPC_BIT(0),
   2397    HMER_PROC_RECV_DONE         = PPC_BIT(2),
   2398    HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
   2399    HMER_TFAC_ERROR             = PPC_BIT(4),
   2400    HMER_TFMR_PARITY_ERROR      = PPC_BIT(5),
   2401    HMER_XSCOM_FAIL             = PPC_BIT(8),
   2402    HMER_XSCOM_DONE             = PPC_BIT(9),
   2403    HMER_PROC_RECV_AGAIN        = PPC_BIT(11),
   2404    HMER_WARN_RISE              = PPC_BIT(14),
   2405    HMER_WARN_FALL              = PPC_BIT(15),
   2406    HMER_SCOM_FIR_HMI           = PPC_BIT(16),
   2407    HMER_TRIG_FIR_HMI           = PPC_BIT(17),
   2408    HMER_HYP_RESOURCE_ERR       = PPC_BIT(20),
   2409    HMER_XSCOM_STATUS_MASK      = PPC_BITMASK(21, 23),
   2410};
   2411
   2412/*****************************************************************************/
   2413
   2414#define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
   2415target_ulong cpu_read_xer(CPUPPCState *env);
   2416void cpu_write_xer(CPUPPCState *env, target_ulong xer);
   2417
   2418/*
   2419 * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
   2420 * have PPC_SEGMENT_64B.
   2421 */
   2422#define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
   2423
   2424#ifdef CONFIG_DEBUG_TCG
   2425void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
   2426                          target_ulong *cs_base, uint32_t *flags);
   2427#else
   2428static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
   2429                                        target_ulong *cs_base, uint32_t *flags)
   2430{
   2431    *pc = env->nip;
   2432    *cs_base = 0;
   2433    *flags = env->hflags;
   2434}
   2435#endif
   2436
   2437void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception);
   2438void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception,
   2439                                      uintptr_t raddr);
   2440void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
   2441                                       uint32_t error_code);
   2442void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
   2443                                          uint32_t error_code, uintptr_t raddr);
   2444
   2445#if !defined(CONFIG_USER_ONLY)
   2446static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
   2447{
   2448    uintptr_t tlbml = (uintptr_t)tlbm;
   2449    uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
   2450
   2451    return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
   2452}
   2453
   2454static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
   2455{
   2456    uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
   2457    int r = tlbncfg & TLBnCFG_N_ENTRY;
   2458    return r;
   2459}
   2460
   2461static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
   2462{
   2463    uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
   2464    int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
   2465    return r;
   2466}
   2467
   2468static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
   2469{
   2470    int id = booke206_tlbm_id(env, tlbm);
   2471    int end = 0;
   2472    int i;
   2473
   2474    for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
   2475        end += booke206_tlb_size(env, i);
   2476        if (id < end) {
   2477            return i;
   2478        }
   2479    }
   2480
   2481    cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id);
   2482    return 0;
   2483}
   2484
   2485static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
   2486{
   2487    int tlbn = booke206_tlbm_to_tlbn(env, tlb);
   2488    int tlbid = booke206_tlbm_id(env, tlb);
   2489    return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
   2490}
   2491
   2492static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
   2493                                              target_ulong ea, int way)
   2494{
   2495    int r;
   2496    uint32_t ways = booke206_tlb_ways(env, tlbn);
   2497    int ways_bits = ctz32(ways);
   2498    int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
   2499    int i;
   2500
   2501    way &= ways - 1;
   2502    ea >>= MAS2_EPN_SHIFT;
   2503    ea &= (1 << (tlb_bits - ways_bits)) - 1;
   2504    r = (ea << ways_bits) | way;
   2505
   2506    if (r >= booke206_tlb_size(env, tlbn)) {
   2507        return NULL;
   2508    }
   2509
   2510    /* bump up to tlbn index */
   2511    for (i = 0; i < tlbn; i++) {
   2512        r += booke206_tlb_size(env, i);
   2513    }
   2514
   2515    return &env->tlb.tlbm[r];
   2516}
   2517
   2518/* returns bitmap of supported page sizes for a given TLB */
   2519static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
   2520{
   2521    uint32_t ret = 0;
   2522
   2523    if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
   2524        /* MAV2 */
   2525        ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
   2526    } else {
   2527        uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
   2528        uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
   2529        uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
   2530        int i;
   2531        for (i = min; i <= max; i++) {
   2532            ret |= (1 << (i << 1));
   2533        }
   2534    }
   2535
   2536    return ret;
   2537}
   2538
   2539static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
   2540                                            ppcmas_tlb_t *tlb)
   2541{
   2542    uint8_t i;
   2543    int32_t tsize = -1;
   2544
   2545    for (i = 0; i < 32; i++) {
   2546        if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
   2547            if (tsize == -1) {
   2548                tsize = i;
   2549            } else {
   2550                return;
   2551            }
   2552        }
   2553    }
   2554
   2555    /* TLBnPS unimplemented? Odd.. */
   2556    assert(tsize != -1);
   2557    tlb->mas1 &= ~MAS1_TSIZE_MASK;
   2558    tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
   2559}
   2560
   2561#endif
   2562
   2563static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
   2564{
   2565    if (env->mmu_model == POWERPC_MMU_BOOKE206) {
   2566        return msr & (1ULL << MSR_CM);
   2567    }
   2568
   2569    return msr & (1ULL << MSR_SF);
   2570}
   2571
   2572/**
   2573 * Check whether register rx is in the range between start and
   2574 * start + nregs (as needed by the LSWX and LSWI instructions)
   2575 */
   2576static inline bool lsw_reg_in_range(int start, int nregs, int rx)
   2577{
   2578    return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
   2579           (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
   2580}
   2581
   2582/* Accessors for FP, VMX and VSX registers */
   2583#if defined(HOST_WORDS_BIGENDIAN)
   2584#define VsrB(i) u8[i]
   2585#define VsrSB(i) s8[i]
   2586#define VsrH(i) u16[i]
   2587#define VsrSH(i) s16[i]
   2588#define VsrW(i) u32[i]
   2589#define VsrSW(i) s32[i]
   2590#define VsrD(i) u64[i]
   2591#define VsrSD(i) s64[i]
   2592#else
   2593#define VsrB(i) u8[15 - (i)]
   2594#define VsrSB(i) s8[15 - (i)]
   2595#define VsrH(i) u16[7 - (i)]
   2596#define VsrSH(i) s16[7 - (i)]
   2597#define VsrW(i) u32[3 - (i)]
   2598#define VsrSW(i) s32[3 - (i)]
   2599#define VsrD(i) u64[1 - (i)]
   2600#define VsrSD(i) s64[1 - (i)]
   2601#endif
   2602
   2603static inline int vsr64_offset(int i, bool high)
   2604{
   2605    return offsetof(CPUPPCState, vsr[i].VsrD(high ? 0 : 1));
   2606}
   2607
   2608static inline int vsr_full_offset(int i)
   2609{
   2610    return offsetof(CPUPPCState, vsr[i].u64[0]);
   2611}
   2612
   2613static inline int fpr_offset(int i)
   2614{
   2615    return vsr64_offset(i, true);
   2616}
   2617
   2618static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
   2619{
   2620    return (uint64_t *)((uintptr_t)env + fpr_offset(i));
   2621}
   2622
   2623static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
   2624{
   2625    return (uint64_t *)((uintptr_t)env + vsr64_offset(i, false));
   2626}
   2627
   2628static inline long avr64_offset(int i, bool high)
   2629{
   2630    return vsr64_offset(i + 32, high);
   2631}
   2632
   2633static inline int avr_full_offset(int i)
   2634{
   2635    return vsr_full_offset(i + 32);
   2636}
   2637
   2638static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
   2639{
   2640    return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i));
   2641}
   2642
   2643static inline bool ppc_has_spr(PowerPCCPU *cpu, int spr)
   2644{
   2645    /* We can test whether the SPR is defined by checking for a valid name */
   2646    return cpu->env.spr_cb[spr].name != NULL;
   2647}
   2648
   2649static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu)
   2650{
   2651    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
   2652
   2653    /*
   2654     * Only models that have an LPCR and know about LPCR_ILE can do little
   2655     * endian.
   2656     */
   2657    if (pcc->lpcr_mask & LPCR_ILE) {
   2658        return !!(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
   2659    }
   2660
   2661    return false;
   2662}
   2663
   2664void dump_mmu(CPUPPCState *env);
   2665
   2666void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
   2667void ppc_store_vscr(CPUPPCState *env, uint32_t vscr);
   2668uint32_t ppc_get_vscr(CPUPPCState *env);
   2669#endif /* PPC_CPU_H */