cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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insn64.decode (5059B)


      1#
      2# Power ISA decode for 64-bit prefixed insns (opcode space 0 and 1)
      3#
      4# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
      5#
      6# This library is free software; you can redistribute it and/or
      7# modify it under the terms of the GNU Lesser General Public
      8# License as published by the Free Software Foundation; either
      9# version 2.1 of the License, or (at your option) any later version.
     10#
     11# This library is distributed in the hope that it will be useful,
     12# but WITHOUT ANY WARRANTY; without even the implied warranty of
     13# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     14# Lesser General Public License for more details.
     15#
     16# You should have received a copy of the GNU Lesser General Public
     17# License along with this library; if not, see <http://www.gnu.org/licenses/>.
     18#
     19
     20# Format MLS:D and 8LS:D
     21&PLS_D          rt ra si:int64_t r:bool
     22%pls_si         32:s18 0:16
     23@PLS_D          ...... .. ... r:1 .. .................. \
     24                ...... rt:5 ra:5 ................       \
     25                &PLS_D si=%pls_si
     26
     27### Fixed-Point Load Instructions
     28
     29PLBZ            000001 10 0--.-- .................. \
     30                100010 ..... ..... ................     @PLS_D
     31PLHZ            000001 10 0--.-- .................. \
     32                101000 ..... ..... ................     @PLS_D
     33PLHA            000001 10 0--.-- .................. \
     34                101010 ..... ..... ................     @PLS_D
     35PLWZ            000001 10 0--.-- .................. \
     36                100000 ..... ..... ................     @PLS_D
     37PLWA            000001 00 0--.-- .................. \
     38                101001 ..... ..... ................     @PLS_D
     39PLD             000001 00 0--.-- .................. \
     40                111001 ..... ..... ................     @PLS_D
     41
     42### Fixed-Point Store Instructions
     43
     44PSTW            000001 10 0--.-- .................. \
     45                100100 ..... ..... ................     @PLS_D
     46PSTB            000001 10 0--.-- .................. \
     47                100110 ..... ..... ................     @PLS_D
     48PSTH            000001 10 0--.-- .................. \
     49                101100 ..... ..... ................     @PLS_D
     50
     51PSTD            000001 00 0--.-- .................. \
     52                111101 ..... ..... ................     @PLS_D
     53
     54### Fixed-Point Arithmetic Instructions
     55
     56PADDI           000001 10 0--.-- ..................     \
     57                001110 ..... ..... ................     @PLS_D
     58
     59### Prefixed No-operation Instruction
     60
     61@PNOP           000001 11 0000-- 000000000000000000     \
     62                ................................
     63
     64{
     65  [
     66    ## Invalid suffixes: Branch instruction
     67    # bc[l][a]
     68    INVALID     ................................        \
     69                010000--------------------------        @PNOP
     70    # b[l][a]
     71    INVALID     ................................        \
     72                010010--------------------------        @PNOP
     73    # bclr[l]
     74    INVALID     ................................        \
     75                010011---------------0000010000-        @PNOP
     76    # bcctr[l]
     77    INVALID     ................................        \
     78                010011---------------1000010000-        @PNOP
     79    # bctar[l]
     80    INVALID     ................................        \
     81                010011---------------1000110000-        @PNOP
     82
     83    ## Invalid suffixes: rfebb
     84    INVALID     ................................        \
     85                010011---------------0010010010-        @PNOP
     86
     87    ## Invalid suffixes: context synchronizing other than isync
     88    # sc
     89    INVALID     ................................        \
     90                010001------------------------1-        @PNOP
     91    # scv
     92    INVALID     ................................        \
     93                010001------------------------01        @PNOP
     94    # rfscv
     95    INVALID     ................................        \
     96                010011---------------0001010010-        @PNOP
     97    # rfid
     98    INVALID     ................................        \
     99                010011---------------0000010010-        @PNOP
    100    # hrfid
    101    INVALID     ................................        \
    102                010011---------------0100010010-        @PNOP
    103    # urfid
    104    INVALID     ................................        \
    105                010011---------------0100110010-        @PNOP
    106    # stop
    107    INVALID     ................................        \
    108                010011---------------0101110010-        @PNOP
    109    # mtmsr w/ L=0
    110    INVALID     ................................        \
    111                011111---------0-----0010010010-        @PNOP
    112    # mtmsrd w/ L=0
    113    INVALID     ................................        \
    114                011111---------0-----0010110010-        @PNOP
    115
    116    ## Invalid suffixes: Service Processor Attention
    117    INVALID     ................................        \
    118                000000----------------100000000-        @PNOP
    119  ]
    120
    121  ## Valid suffixes
    122  PNOP          ................................        \
    123                --------------------------------        @PNOP
    124}