cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

monitor.c (4497B)

      1/*
      2 * QEMU monitor
      3 *
      4 * Copyright (c) 2003-2004 Fabrice Bellard
      5 *
      6 * Permission is hereby granted, free of charge, to any person obtaining a copy
      7 * of this software and associated documentation files (the "Software"), to deal
      8 * in the Software without restriction, including without limitation the rights
      9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     10 * copies of the Software, and to permit persons to whom the Software is
     11 * furnished to do so, subject to the following conditions:
     12 *
     13 * The above copyright notice and this permission notice shall be included in
     14 * all copies or substantial portions of the Software.
     15 *
     16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
     19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     22 * THE SOFTWARE.
     23 */
     24
     25#include "qemu/osdep.h"
     26#include "cpu.h"
     27#include "monitor/monitor.h"
     28#include "qemu/ctype.h"
     29#include "monitor/hmp-target.h"
     30#include "monitor/hmp.h"
     31
     32static target_long monitor_get_ccr(Monitor *mon, const struct MonitorDef *md,
     33                                   int val)
     34{
     35    CPUArchState *env = mon_get_cpu_env(mon);
     36    unsigned int u;
     37    int i;
     38
     39    u = 0;
     40    for (i = 0; i < 8; i++) {
     41        u |= env->crf[i] << (32 - (4 * (i + 1)));
     42    }
     43
     44    return u;
     45}
     46
     47static target_long monitor_get_decr(Monitor *mon, const struct MonitorDef *md,
     48                                    int val)
     49{
     50    CPUArchState *env = mon_get_cpu_env(mon);
     51    return cpu_ppc_load_decr(env);
     52}
     53
     54static target_long monitor_get_tbu(Monitor *mon, const struct MonitorDef *md,
     55                                   int val)
     56{
     57    CPUArchState *env = mon_get_cpu_env(mon);
     58    return cpu_ppc_load_tbu(env);
     59}
     60
     61static target_long monitor_get_tbl(Monitor *mon, const struct MonitorDef *md,
     62                                   int val)
     63{
     64    CPUArchState *env = mon_get_cpu_env(mon);
     65    return cpu_ppc_load_tbl(env);
     66}
     67
     68void hmp_info_tlb(Monitor *mon, const QDict *qdict)
     69{
     70    CPUArchState *env1 = mon_get_cpu_env(mon);
     71
     72    if (!env1) {
     73        monitor_printf(mon, "No CPU available\n");
     74        return;
     75    }
     76    dump_mmu(env1);
     77}
     78
     79const MonitorDef monitor_defs[] = {
     80    { "fpscr", offsetof(CPUPPCState, fpscr) },
     81    /* Next instruction pointer */
     82    { "nip|pc", offsetof(CPUPPCState, nip) },
     83    { "lr", offsetof(CPUPPCState, lr) },
     84    { "ctr", offsetof(CPUPPCState, ctr) },
     85    { "decr", 0, &monitor_get_decr, },
     86    { "ccr|cr", 0, &monitor_get_ccr, },
     87    /* Machine state register */
     88    { "xer", offsetof(CPUPPCState, xer) },
     89    { "msr", offsetof(CPUPPCState, msr) },
     90    { "tbu", 0, &monitor_get_tbu, },
     91    { "tbl", 0, &monitor_get_tbl, },
     92    { NULL },
     93};
     94
     95const MonitorDef *target_monitor_defs(void)
     96{
     97    return monitor_defs;
     98}
     99
    100static int ppc_cpu_get_reg_num(const char *numstr, int maxnum, int *pregnum)
    101{
    102    int regnum;
    103    char *endptr = NULL;
    104
    105    if (!*numstr) {
    106        return false;
    107    }
    108
    109    regnum = strtoul(numstr, &endptr, 10);
    110    if (*endptr || (regnum >= maxnum)) {
    111        return false;
    112    }
    113    *pregnum = regnum;
    114
    115    return true;
    116}
    117
    118int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
    119{
    120    int i, regnum;
    121    PowerPCCPU *cpu = POWERPC_CPU(cs);
    122    CPUPPCState *env = &cpu->env;
    123
    124    /* General purpose registers */
    125    if ((qemu_tolower(name[0]) == 'r') &&
    126        ppc_cpu_get_reg_num(name + 1, ARRAY_SIZE(env->gpr), &regnum)) {
    127        *pval = env->gpr[regnum];
    128        return 0;
    129    }
    130
    131    /* Floating point registers */
    132    if ((qemu_tolower(name[0]) == 'f') &&
    133        ppc_cpu_get_reg_num(name + 1, 32, &regnum)) {
    134        *pval = *cpu_fpr_ptr(env, regnum);
    135        return 0;
    136    }
    137
    138    /* Special purpose registers */
    139    for (i = 0; i < ARRAY_SIZE(env->spr_cb); ++i) {
    140        ppc_spr_t *spr = &env->spr_cb[i];
    141
    142        if (spr->name && (strcasecmp(name, spr->name) == 0)) {
    143            *pval = env->spr[i];
    144            return 0;
    145        }
    146    }
    147
    148    /* Segment registers */
    149#if !defined(CONFIG_USER_ONLY)
    150    if ((strncasecmp(name, "sr", 2) == 0) &&
    151        ppc_cpu_get_reg_num(name + 2, ARRAY_SIZE(env->sr), &regnum)) {
    152        *pval = env->sr[regnum];
    153        return 0;
    154    }
    155#endif
    156
    157    return -EINVAL;
    158}