spe-impl.c.inc (56013B)
1/* 2 * translate-spe.c 3 * 4 * Freescale SPE extension translation 5 */ 6 7/*** SPE extension ***/ 8/* Register moves */ 9 10static inline void gen_evmra(DisasContext *ctx) 11{ 12 13 if (unlikely(!ctx->spe_enabled)) { 14 gen_exception(ctx, POWERPC_EXCP_SPEU); 15 return; 16 } 17 18 TCGv_i64 tmp = tcg_temp_new_i64(); 19 20 /* tmp := rA_lo + rA_hi << 32 */ 21 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], 22 cpu_gprh[rA(ctx->opcode)]); 23 24 /* spe_acc := tmp */ 25 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); 26 tcg_temp_free_i64(tmp); 27 28 /* rD := rA */ 29 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 30 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); 31} 32 33static inline void gen_load_gpr64(TCGv_i64 t, int reg) 34{ 35 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]); 36} 37 38static inline void gen_store_gpr64(int reg, TCGv_i64 t) 39{ 40 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t); 41} 42 43#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ 44static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ 45{ \ 46 if (Rc(ctx->opcode)) \ 47 gen_##name1(ctx); \ 48 else \ 49 gen_##name0(ctx); \ 50} 51 52/* Handler for undefined SPE opcodes */ 53static inline void gen_speundef(DisasContext *ctx) 54{ 55 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); 56} 57 58/* SPE logic */ 59#define GEN_SPEOP_LOGIC2(name, tcg_op) \ 60static inline void gen_##name(DisasContext *ctx) \ 61{ \ 62 if (unlikely(!ctx->spe_enabled)) { \ 63 gen_exception(ctx, POWERPC_EXCP_SPEU); \ 64 return; \ 65 } \ 66 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ 67 cpu_gpr[rB(ctx->opcode)]); \ 68 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ 69 cpu_gprh[rB(ctx->opcode)]); \ 70} 71 72GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl); 73GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl); 74GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl); 75GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl); 76GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl); 77GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl); 78GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl); 79GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl); 80 81/* SPE logic immediate */ 82#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ 83static inline void gen_##name(DisasContext *ctx) \ 84{ \ 85 TCGv_i32 t0; \ 86 if (unlikely(!ctx->spe_enabled)) { \ 87 gen_exception(ctx, POWERPC_EXCP_SPEU); \ 88 return; \ 89 } \ 90 t0 = tcg_temp_new_i32(); \ 91 \ 92 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ 93 tcg_opi(t0, t0, rB(ctx->opcode)); \ 94 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ 95 \ 96 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \ 97 tcg_opi(t0, t0, rB(ctx->opcode)); \ 98 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ 99 \ 100 tcg_temp_free_i32(t0); \ 101} 102GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32); 103GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32); 104GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32); 105GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32); 106 107/* SPE arithmetic */ 108#define GEN_SPEOP_ARITH1(name, tcg_op) \ 109static inline void gen_##name(DisasContext *ctx) \ 110{ \ 111 TCGv_i32 t0; \ 112 if (unlikely(!ctx->spe_enabled)) { \ 113 gen_exception(ctx, POWERPC_EXCP_SPEU); \ 114 return; \ 115 } \ 116 t0 = tcg_temp_new_i32(); \ 117 \ 118 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ 119 tcg_op(t0, t0); \ 120 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ 121 \ 122 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \ 123 tcg_op(t0, t0); \ 124 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ 125 \ 126 tcg_temp_free_i32(t0); \ 127} 128 129GEN_SPEOP_ARITH1(evabs, tcg_gen_abs_i32); 130GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); 131GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); 132GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); 133static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1) 134{ 135 tcg_gen_addi_i32(ret, arg1, 0x8000); 136 tcg_gen_ext16u_i32(ret, ret); 137} 138GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw); 139GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32); 140GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32); 141 142#define GEN_SPEOP_ARITH2(name, tcg_op) \ 143static inline void gen_##name(DisasContext *ctx) \ 144{ \ 145 TCGv_i32 t0, t1; \ 146 if (unlikely(!ctx->spe_enabled)) { \ 147 gen_exception(ctx, POWERPC_EXCP_SPEU); \ 148 return; \ 149 } \ 150 t0 = tcg_temp_new_i32(); \ 151 t1 = tcg_temp_new_i32(); \ 152 \ 153 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ 154 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ 155 tcg_op(t0, t0, t1); \ 156 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ 157 \ 158 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \ 159 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \ 160 tcg_op(t0, t0, t1); \ 161 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ 162 \ 163 tcg_temp_free_i32(t0); \ 164 tcg_temp_free_i32(t1); \ 165} 166 167static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 168{ 169 TCGLabel *l1 = gen_new_label(); 170 TCGLabel *l2 = gen_new_label(); 171 TCGv_i32 t0 = tcg_temp_local_new_i32(); 172 173 /* No error here: 6 bits are used */ 174 tcg_gen_andi_i32(t0, arg2, 0x3F); 175 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); 176 tcg_gen_shr_i32(ret, arg1, t0); 177 tcg_gen_br(l2); 178 gen_set_label(l1); 179 tcg_gen_movi_i32(ret, 0); 180 gen_set_label(l2); 181 tcg_temp_free_i32(t0); 182} 183GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); 184static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 185{ 186 TCGLabel *l1 = gen_new_label(); 187 TCGLabel *l2 = gen_new_label(); 188 TCGv_i32 t0 = tcg_temp_local_new_i32(); 189 190 /* No error here: 6 bits are used */ 191 tcg_gen_andi_i32(t0, arg2, 0x3F); 192 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); 193 tcg_gen_sar_i32(ret, arg1, t0); 194 tcg_gen_br(l2); 195 gen_set_label(l1); 196 tcg_gen_movi_i32(ret, 0); 197 gen_set_label(l2); 198 tcg_temp_free_i32(t0); 199} 200GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); 201static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 202{ 203 TCGLabel *l1 = gen_new_label(); 204 TCGLabel *l2 = gen_new_label(); 205 TCGv_i32 t0 = tcg_temp_local_new_i32(); 206 207 /* No error here: 6 bits are used */ 208 tcg_gen_andi_i32(t0, arg2, 0x3F); 209 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); 210 tcg_gen_shl_i32(ret, arg1, t0); 211 tcg_gen_br(l2); 212 gen_set_label(l1); 213 tcg_gen_movi_i32(ret, 0); 214 gen_set_label(l2); 215 tcg_temp_free_i32(t0); 216} 217GEN_SPEOP_ARITH2(evslw, gen_op_evslw); 218static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 219{ 220 TCGv_i32 t0 = tcg_temp_new_i32(); 221 tcg_gen_andi_i32(t0, arg2, 0x1F); 222 tcg_gen_rotl_i32(ret, arg1, t0); 223 tcg_temp_free_i32(t0); 224} 225GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); 226static inline void gen_evmergehi(DisasContext *ctx) 227{ 228 if (unlikely(!ctx->spe_enabled)) { 229 gen_exception(ctx, POWERPC_EXCP_SPEU); 230 return; 231 } 232 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); 233 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); 234} 235GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32); 236static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) 237{ 238 tcg_gen_sub_i32(ret, arg2, arg1); 239} 240GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf); 241 242/* SPE arithmetic immediate */ 243#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ 244static inline void gen_##name(DisasContext *ctx) \ 245{ \ 246 TCGv_i32 t0; \ 247 if (unlikely(!ctx->spe_enabled)) { \ 248 gen_exception(ctx, POWERPC_EXCP_SPEU); \ 249 return; \ 250 } \ 251 t0 = tcg_temp_new_i32(); \ 252 \ 253 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ 254 tcg_op(t0, t0, rA(ctx->opcode)); \ 255 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ 256 \ 257 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \ 258 tcg_op(t0, t0, rA(ctx->opcode)); \ 259 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ 260 \ 261 tcg_temp_free_i32(t0); \ 262} 263GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32); 264GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); 265 266/* SPE comparison */ 267#define GEN_SPEOP_COMP(name, tcg_cond) \ 268static inline void gen_##name(DisasContext *ctx) \ 269{ \ 270 if (unlikely(!ctx->spe_enabled)) { \ 271 gen_exception(ctx, POWERPC_EXCP_SPEU); \ 272 return; \ 273 } \ 274 TCGLabel *l1 = gen_new_label(); \ 275 TCGLabel *l2 = gen_new_label(); \ 276 TCGLabel *l3 = gen_new_label(); \ 277 TCGLabel *l4 = gen_new_label(); \ 278 \ 279 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \ 280 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ 281 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \ 282 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \ 283 \ 284 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \ 285 cpu_gpr[rB(ctx->opcode)], l1); \ 286 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \ 287 tcg_gen_br(l2); \ 288 gen_set_label(l1); \ 289 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ 290 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ 291 gen_set_label(l2); \ 292 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \ 293 cpu_gprh[rB(ctx->opcode)], l3); \ 294 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ 295 ~(CRF_CH | CRF_CH_AND_CL)); \ 296 tcg_gen_br(l4); \ 297 gen_set_label(l3); \ 298 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ 299 CRF_CH | CRF_CH_OR_CL); \ 300 gen_set_label(l4); \ 301} 302GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU); 303GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT); 304GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU); 305GEN_SPEOP_COMP(evcmplts, TCG_COND_LT); 306GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ); 307 308/* SPE misc */ 309static inline void gen_brinc(DisasContext *ctx) 310{ 311 /* Note: brinc is usable even if SPE is disabled */ 312 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)], 313 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 314} 315static inline void gen_evmergelo(DisasContext *ctx) 316{ 317 if (unlikely(!ctx->spe_enabled)) { 318 gen_exception(ctx, POWERPC_EXCP_SPEU); 319 return; 320 } 321 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 322 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 323} 324static inline void gen_evmergehilo(DisasContext *ctx) 325{ 326 if (unlikely(!ctx->spe_enabled)) { 327 gen_exception(ctx, POWERPC_EXCP_SPEU); 328 return; 329 } 330 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 331 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); 332} 333static inline void gen_evmergelohi(DisasContext *ctx) 334{ 335 if (unlikely(!ctx->spe_enabled)) { 336 gen_exception(ctx, POWERPC_EXCP_SPEU); 337 return; 338 } 339 if (rD(ctx->opcode) == rA(ctx->opcode)) { 340 TCGv tmp = tcg_temp_new(); 341 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]); 342 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); 343 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp); 344 tcg_temp_free(tmp); 345 } else { 346 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); 347 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 348 } 349} 350static inline void gen_evsplati(DisasContext *ctx) 351{ 352 uint64_t imm; 353 if (unlikely(!ctx->spe_enabled)) { 354 gen_exception(ctx, POWERPC_EXCP_SPEU); 355 return; 356 } 357 imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27; 358 359 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm); 360 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm); 361} 362static inline void gen_evsplatfi(DisasContext *ctx) 363{ 364 uint64_t imm; 365 if (unlikely(!ctx->spe_enabled)) { 366 gen_exception(ctx, POWERPC_EXCP_SPEU); 367 return; 368 } 369 imm = rA(ctx->opcode) << 27; 370 371 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm); 372 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm); 373} 374 375static inline void gen_evsel(DisasContext *ctx) 376{ 377 TCGLabel *l1 = gen_new_label(); 378 TCGLabel *l2 = gen_new_label(); 379 TCGLabel *l3 = gen_new_label(); 380 TCGLabel *l4 = gen_new_label(); 381 TCGv_i32 t0 = tcg_temp_local_new_i32(); 382 383 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3); 384 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); 385 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); 386 tcg_gen_br(l2); 387 gen_set_label(l1); 388 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); 389 gen_set_label(l2); 390 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2); 391 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3); 392 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 393 tcg_gen_br(l4); 394 gen_set_label(l3); 395 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); 396 gen_set_label(l4); 397 tcg_temp_free_i32(t0); 398} 399 400static void gen_evsel0(DisasContext *ctx) 401{ 402 if (unlikely(!ctx->spe_enabled)) { 403 gen_exception(ctx, POWERPC_EXCP_SPEU); 404 return; 405 } 406 gen_evsel(ctx); 407} 408 409static void gen_evsel1(DisasContext *ctx) 410{ 411 if (unlikely(!ctx->spe_enabled)) { 412 gen_exception(ctx, POWERPC_EXCP_SPEU); 413 return; 414 } 415 gen_evsel(ctx); 416} 417 418static void gen_evsel2(DisasContext *ctx) 419{ 420 if (unlikely(!ctx->spe_enabled)) { 421 gen_exception(ctx, POWERPC_EXCP_SPEU); 422 return; 423 } 424 gen_evsel(ctx); 425} 426 427static void gen_evsel3(DisasContext *ctx) 428{ 429 if (unlikely(!ctx->spe_enabled)) { 430 gen_exception(ctx, POWERPC_EXCP_SPEU); 431 return; 432 } 433 gen_evsel(ctx); 434} 435 436/* Multiply */ 437 438static inline void gen_evmwumi(DisasContext *ctx) 439{ 440 TCGv_i64 t0, t1; 441 442 if (unlikely(!ctx->spe_enabled)) { 443 gen_exception(ctx, POWERPC_EXCP_SPEU); 444 return; 445 } 446 447 t0 = tcg_temp_new_i64(); 448 t1 = tcg_temp_new_i64(); 449 450 /* t0 := rA; t1 := rB */ 451 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 452 tcg_gen_ext32u_i64(t0, t0); 453 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 454 tcg_gen_ext32u_i64(t1, t1); 455 456 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ 457 458 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ 459 460 tcg_temp_free_i64(t0); 461 tcg_temp_free_i64(t1); 462} 463 464static inline void gen_evmwumia(DisasContext *ctx) 465{ 466 TCGv_i64 tmp; 467 468 if (unlikely(!ctx->spe_enabled)) { 469 gen_exception(ctx, POWERPC_EXCP_SPEU); 470 return; 471 } 472 473 gen_evmwumi(ctx); /* rD := rA * rB */ 474 475 tmp = tcg_temp_new_i64(); 476 477 /* acc := rD */ 478 gen_load_gpr64(tmp, rD(ctx->opcode)); 479 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); 480 tcg_temp_free_i64(tmp); 481} 482 483static inline void gen_evmwumiaa(DisasContext *ctx) 484{ 485 TCGv_i64 acc; 486 TCGv_i64 tmp; 487 488 if (unlikely(!ctx->spe_enabled)) { 489 gen_exception(ctx, POWERPC_EXCP_SPEU); 490 return; 491 } 492 493 gen_evmwumi(ctx); /* rD := rA * rB */ 494 495 acc = tcg_temp_new_i64(); 496 tmp = tcg_temp_new_i64(); 497 498 /* tmp := rD */ 499 gen_load_gpr64(tmp, rD(ctx->opcode)); 500 501 /* Load acc */ 502 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); 503 504 /* acc := tmp + acc */ 505 tcg_gen_add_i64(acc, acc, tmp); 506 507 /* Store acc */ 508 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); 509 510 /* rD := acc */ 511 gen_store_gpr64(rD(ctx->opcode), acc); 512 513 tcg_temp_free_i64(acc); 514 tcg_temp_free_i64(tmp); 515} 516 517static inline void gen_evmwsmi(DisasContext *ctx) 518{ 519 TCGv_i64 t0, t1; 520 521 if (unlikely(!ctx->spe_enabled)) { 522 gen_exception(ctx, POWERPC_EXCP_SPEU); 523 return; 524 } 525 526 t0 = tcg_temp_new_i64(); 527 t1 = tcg_temp_new_i64(); 528 529 /* t0 := rA; t1 := rB */ 530 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); 531 tcg_gen_ext32s_i64(t0, t0); 532 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); 533 tcg_gen_ext32s_i64(t1, t1); 534 535 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ 536 537 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ 538 539 tcg_temp_free_i64(t0); 540 tcg_temp_free_i64(t1); 541} 542 543static inline void gen_evmwsmia(DisasContext *ctx) 544{ 545 TCGv_i64 tmp; 546 547 if (unlikely(!ctx->spe_enabled)) { 548 gen_exception(ctx, POWERPC_EXCP_SPEU); 549 return; 550 } 551 552 gen_evmwsmi(ctx); /* rD := rA * rB */ 553 554 tmp = tcg_temp_new_i64(); 555 556 /* acc := rD */ 557 gen_load_gpr64(tmp, rD(ctx->opcode)); 558 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); 559 560 tcg_temp_free_i64(tmp); 561} 562 563static inline void gen_evmwsmiaa(DisasContext *ctx) 564{ 565 TCGv_i64 acc; 566 TCGv_i64 tmp; 567 568 if (unlikely(!ctx->spe_enabled)) { 569 gen_exception(ctx, POWERPC_EXCP_SPEU); 570 return; 571 } 572 573 gen_evmwsmi(ctx); /* rD := rA * rB */ 574 575 acc = tcg_temp_new_i64(); 576 tmp = tcg_temp_new_i64(); 577 578 /* tmp := rD */ 579 gen_load_gpr64(tmp, rD(ctx->opcode)); 580 581 /* Load acc */ 582 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); 583 584 /* acc := tmp + acc */ 585 tcg_gen_add_i64(acc, acc, tmp); 586 587 /* Store acc */ 588 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); 589 590 /* rD := acc */ 591 gen_store_gpr64(rD(ctx->opcode), acc); 592 593 tcg_temp_free_i64(acc); 594 tcg_temp_free_i64(tmp); 595} 596 597GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// 598GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); 599GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// 600GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); 601GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// 602GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// 603GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// 604GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); // 605GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE); 606GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// 607GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// 608GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// 609GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// 610GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE); 611GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE); 612GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE); 613GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// 614GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// 615GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// 616GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE); 617GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// 618GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); 619GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); // 620GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE); 621GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// 622GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// 623GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// 624GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// 625GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); //// 626 627/* SPE load and stores */ 628static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh) 629{ 630 target_ulong uimm = rB(ctx->opcode); 631 632 if (rA(ctx->opcode) == 0) { 633 tcg_gen_movi_tl(EA, uimm << sh); 634 } else { 635 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh); 636 if (NARROW_MODE(ctx)) { 637 tcg_gen_ext32u_tl(EA, EA); 638 } 639 } 640} 641 642static inline void gen_op_evldd(DisasContext *ctx, TCGv addr) 643{ 644 TCGv_i64 t0 = tcg_temp_new_i64(); 645 gen_qemu_ld64_i64(ctx, t0, addr); 646 gen_store_gpr64(rD(ctx->opcode), t0); 647 tcg_temp_free_i64(t0); 648} 649 650static inline void gen_op_evldw(DisasContext *ctx, TCGv addr) 651{ 652 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr); 653 gen_addr_add(ctx, addr, addr, 4); 654 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr); 655} 656 657static inline void gen_op_evldh(DisasContext *ctx, TCGv addr) 658{ 659 TCGv t0 = tcg_temp_new(); 660 gen_qemu_ld16u(ctx, t0, addr); 661 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); 662 gen_addr_add(ctx, addr, addr, 2); 663 gen_qemu_ld16u(ctx, t0, addr); 664 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); 665 gen_addr_add(ctx, addr, addr, 2); 666 gen_qemu_ld16u(ctx, t0, addr); 667 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); 668 gen_addr_add(ctx, addr, addr, 2); 669 gen_qemu_ld16u(ctx, t0, addr); 670 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); 671 tcg_temp_free(t0); 672} 673 674static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) 675{ 676 TCGv t0 = tcg_temp_new(); 677 gen_qemu_ld16u(ctx, t0, addr); 678 tcg_gen_shli_tl(t0, t0, 16); 679 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); 680 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 681 tcg_temp_free(t0); 682} 683 684static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) 685{ 686 TCGv t0 = tcg_temp_new(); 687 gen_qemu_ld16u(ctx, t0, addr); 688 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); 689 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 690 tcg_temp_free(t0); 691} 692 693static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) 694{ 695 TCGv t0 = tcg_temp_new(); 696 gen_qemu_ld16s(ctx, t0, addr); 697 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); 698 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 699 tcg_temp_free(t0); 700} 701 702static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) 703{ 704 TCGv t0 = tcg_temp_new(); 705 gen_qemu_ld16u(ctx, t0, addr); 706 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); 707 gen_addr_add(ctx, addr, addr, 2); 708 gen_qemu_ld16u(ctx, t0, addr); 709 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); 710 tcg_temp_free(t0); 711} 712 713static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) 714{ 715 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr); 716 gen_addr_add(ctx, addr, addr, 2); 717 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); 718} 719 720static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) 721{ 722 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr); 723 gen_addr_add(ctx, addr, addr, 2); 724 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr); 725} 726 727static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) 728{ 729 TCGv t0 = tcg_temp_new(); 730 gen_qemu_ld32u(ctx, t0, addr); 731 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); 732 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); 733 tcg_temp_free(t0); 734} 735 736static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) 737{ 738 TCGv t0 = tcg_temp_new(); 739 gen_qemu_ld16u(ctx, t0, addr); 740 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); 741 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); 742 gen_addr_add(ctx, addr, addr, 2); 743 gen_qemu_ld16u(ctx, t0, addr); 744 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); 745 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); 746 tcg_temp_free(t0); 747} 748 749static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) 750{ 751 TCGv_i64 t0 = tcg_temp_new_i64(); 752 gen_load_gpr64(t0, rS(ctx->opcode)); 753 gen_qemu_st64_i64(ctx, t0, addr); 754 tcg_temp_free_i64(t0); 755} 756 757static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) 758{ 759 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); 760 gen_addr_add(ctx, addr, addr, 4); 761 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); 762} 763 764static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) 765{ 766 TCGv t0 = tcg_temp_new(); 767 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); 768 gen_qemu_st16(ctx, t0, addr); 769 gen_addr_add(ctx, addr, addr, 2); 770 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); 771 gen_addr_add(ctx, addr, addr, 2); 772 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); 773 gen_qemu_st16(ctx, t0, addr); 774 tcg_temp_free(t0); 775 gen_addr_add(ctx, addr, addr, 2); 776 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); 777} 778 779static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) 780{ 781 TCGv t0 = tcg_temp_new(); 782 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); 783 gen_qemu_st16(ctx, t0, addr); 784 gen_addr_add(ctx, addr, addr, 2); 785 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); 786 gen_qemu_st16(ctx, t0, addr); 787 tcg_temp_free(t0); 788} 789 790static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) 791{ 792 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); 793 gen_addr_add(ctx, addr, addr, 2); 794 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); 795} 796 797static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) 798{ 799 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); 800} 801 802static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) 803{ 804 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); 805} 806 807#define GEN_SPEOP_LDST(name, opc2, sh) \ 808static void glue(gen_, name)(DisasContext *ctx) \ 809{ \ 810 TCGv t0; \ 811 if (unlikely(!ctx->spe_enabled)) { \ 812 gen_exception(ctx, POWERPC_EXCP_SPEU); \ 813 return; \ 814 } \ 815 gen_set_access_type(ctx, ACCESS_INT); \ 816 t0 = tcg_temp_new(); \ 817 if (Rc(ctx->opcode)) { \ 818 gen_addr_spe_imm_index(ctx, t0, sh); \ 819 } else { \ 820 gen_addr_reg_index(ctx, t0); \ 821 } \ 822 gen_op_##name(ctx, t0); \ 823 tcg_temp_free(t0); \ 824} 825 826GEN_SPEOP_LDST(evldd, 0x00, 3); 827GEN_SPEOP_LDST(evldw, 0x01, 3); 828GEN_SPEOP_LDST(evldh, 0x02, 3); 829GEN_SPEOP_LDST(evlhhesplat, 0x04, 1); 830GEN_SPEOP_LDST(evlhhousplat, 0x06, 1); 831GEN_SPEOP_LDST(evlhhossplat, 0x07, 1); 832GEN_SPEOP_LDST(evlwhe, 0x08, 2); 833GEN_SPEOP_LDST(evlwhou, 0x0A, 2); 834GEN_SPEOP_LDST(evlwhos, 0x0B, 2); 835GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2); 836GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2); 837 838GEN_SPEOP_LDST(evstdd, 0x10, 3); 839GEN_SPEOP_LDST(evstdw, 0x11, 3); 840GEN_SPEOP_LDST(evstdh, 0x12, 3); 841GEN_SPEOP_LDST(evstwhe, 0x18, 2); 842GEN_SPEOP_LDST(evstwho, 0x1A, 2); 843GEN_SPEOP_LDST(evstwwe, 0x1C, 2); 844GEN_SPEOP_LDST(evstwwo, 0x1E, 2); 845 846/* Multiply and add - TODO */ 847#if 0 848GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);// 849GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); 850GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE); 851GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); 852GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE); 853GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); 854GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); 855GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); 856GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE); 857GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); 858GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE); 859GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); 860 861GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); 862GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); 863GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE); 864GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); 865GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); 866GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); 867GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); 868GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); 869GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE); 870GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); 871GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); 872GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); 873 874GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); 875GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); 876GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); 877GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); 878GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE); 879 880GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE); 881GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); 882GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE); 883GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); 884GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE); 885GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); 886GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE); 887GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); 888GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE); 889GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); 890GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE); 891GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); 892 893GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE); 894GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE); 895GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); 896GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); 897 898GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE); 899GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); 900GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE); 901GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); 902GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE); 903GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); 904GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE); 905GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); 906GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE); 907GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); 908GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE); 909GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); 910 911GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE); 912GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE); 913GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); 914GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE); 915GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); 916#endif 917 918/*** SPE floating-point extension ***/ 919#define GEN_SPEFPUOP_CONV_32_32(name) \ 920static inline void gen_##name(DisasContext *ctx) \ 921{ \ 922 TCGv_i32 t0 = tcg_temp_new_i32(); \ 923 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ 924 gen_helper_##name(t0, cpu_env, t0); \ 925 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ 926 tcg_temp_free_i32(t0); \ 927} 928#define GEN_SPEFPUOP_CONV_32_64(name) \ 929static inline void gen_##name(DisasContext *ctx) \ 930{ \ 931 TCGv_i64 t0; \ 932 TCGv_i32 t1; \ 933 if (unlikely(!ctx->spe_enabled)) { \ 934 gen_exception(ctx, POWERPC_EXCP_SPEU); \ 935 return; \ 936 } \ 937 t0 = tcg_temp_new_i64(); \ 938 t1 = tcg_temp_new_i32(); \ 939 gen_load_gpr64(t0, rB(ctx->opcode)); \ 940 gen_helper_##name(t1, cpu_env, t0); \ 941 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \ 942 tcg_temp_free_i64(t0); \ 943 tcg_temp_free_i32(t1); \ 944} 945#define GEN_SPEFPUOP_CONV_64_32(name) \ 946static inline void gen_##name(DisasContext *ctx) \ 947{ \ 948 TCGv_i64 t0; \ 949 TCGv_i32 t1; \ 950 if (unlikely(!ctx->spe_enabled)) { \ 951 gen_exception(ctx, POWERPC_EXCP_SPEU); \ 952 return; \ 953 } \ 954 t0 = tcg_temp_new_i64(); \ 955 t1 = tcg_temp_new_i32(); \ 956 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ 957 gen_helper_##name(t0, cpu_env, t1); \ 958 gen_store_gpr64(rD(ctx->opcode), t0); \ 959 tcg_temp_free_i64(t0); \ 960 tcg_temp_free_i32(t1); \ 961} 962#define GEN_SPEFPUOP_CONV_64_64(name) \ 963static inline void gen_##name(DisasContext *ctx) \ 964{ \ 965 TCGv_i64 t0; \ 966 if (unlikely(!ctx->spe_enabled)) { \ 967 gen_exception(ctx, POWERPC_EXCP_SPEU); \ 968 return; \ 969 } \ 970 t0 = tcg_temp_new_i64(); \ 971 gen_load_gpr64(t0, rB(ctx->opcode)); \ 972 gen_helper_##name(t0, cpu_env, t0); \ 973 gen_store_gpr64(rD(ctx->opcode), t0); \ 974 tcg_temp_free_i64(t0); \ 975} 976#define GEN_SPEFPUOP_ARITH2_32_32(name) \ 977static inline void gen_##name(DisasContext *ctx) \ 978{ \ 979 TCGv_i32 t0 = tcg_temp_new_i32(); \ 980 TCGv_i32 t1 = tcg_temp_new_i32(); \ 981 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ 982 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ 983 gen_helper_##name(t0, cpu_env, t0, t1); \ 984 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ 985 \ 986 tcg_temp_free_i32(t0); \ 987 tcg_temp_free_i32(t1); \ 988} 989#define GEN_SPEFPUOP_ARITH2_64_64(name) \ 990static inline void gen_##name(DisasContext *ctx) \ 991{ \ 992 TCGv_i64 t0, t1; \ 993 if (unlikely(!ctx->spe_enabled)) { \ 994 gen_exception(ctx, POWERPC_EXCP_SPEU); \ 995 return; \ 996 } \ 997 t0 = tcg_temp_new_i64(); \ 998 t1 = tcg_temp_new_i64(); \ 999 gen_load_gpr64(t0, rA(ctx->opcode)); \ 1000 gen_load_gpr64(t1, rB(ctx->opcode)); \ 1001 gen_helper_##name(t0, cpu_env, t0, t1); \ 1002 gen_store_gpr64(rD(ctx->opcode), t0); \ 1003 tcg_temp_free_i64(t0); \ 1004 tcg_temp_free_i64(t1); \ 1005} 1006#define GEN_SPEFPUOP_COMP_32(name) \ 1007static inline void gen_##name(DisasContext *ctx) \ 1008{ \ 1009 TCGv_i32 t0 = tcg_temp_new_i32(); \ 1010 TCGv_i32 t1 = tcg_temp_new_i32(); \ 1011 \ 1012 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ 1013 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ 1014 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ 1015 \ 1016 tcg_temp_free_i32(t0); \ 1017 tcg_temp_free_i32(t1); \ 1018} 1019#define GEN_SPEFPUOP_COMP_64(name) \ 1020static inline void gen_##name(DisasContext *ctx) \ 1021{ \ 1022 TCGv_i64 t0, t1; \ 1023 if (unlikely(!ctx->spe_enabled)) { \ 1024 gen_exception(ctx, POWERPC_EXCP_SPEU); \ 1025 return; \ 1026 } \ 1027 t0 = tcg_temp_new_i64(); \ 1028 t1 = tcg_temp_new_i64(); \ 1029 gen_load_gpr64(t0, rA(ctx->opcode)); \ 1030 gen_load_gpr64(t1, rB(ctx->opcode)); \ 1031 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ 1032 tcg_temp_free_i64(t0); \ 1033 tcg_temp_free_i64(t1); \ 1034} 1035 1036/* Single precision floating-point vectors operations */ 1037/* Arithmetic */ 1038GEN_SPEFPUOP_ARITH2_64_64(evfsadd); 1039GEN_SPEFPUOP_ARITH2_64_64(evfssub); 1040GEN_SPEFPUOP_ARITH2_64_64(evfsmul); 1041GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); 1042static inline void gen_evfsabs(DisasContext *ctx) 1043{ 1044 if (unlikely(!ctx->spe_enabled)) { 1045 gen_exception(ctx, POWERPC_EXCP_SPEU); 1046 return; 1047 } 1048 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1049 ~0x80000000); 1050 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 1051 ~0x80000000); 1052} 1053static inline void gen_evfsnabs(DisasContext *ctx) 1054{ 1055 if (unlikely(!ctx->spe_enabled)) { 1056 gen_exception(ctx, POWERPC_EXCP_SPEU); 1057 return; 1058 } 1059 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1060 0x80000000); 1061 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 1062 0x80000000); 1063} 1064static inline void gen_evfsneg(DisasContext *ctx) 1065{ 1066 if (unlikely(!ctx->spe_enabled)) { 1067 gen_exception(ctx, POWERPC_EXCP_SPEU); 1068 return; 1069 } 1070 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1071 0x80000000); 1072 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 1073 0x80000000); 1074} 1075 1076/* Conversion */ 1077GEN_SPEFPUOP_CONV_64_64(evfscfui); 1078GEN_SPEFPUOP_CONV_64_64(evfscfsi); 1079GEN_SPEFPUOP_CONV_64_64(evfscfuf); 1080GEN_SPEFPUOP_CONV_64_64(evfscfsf); 1081GEN_SPEFPUOP_CONV_64_64(evfsctui); 1082GEN_SPEFPUOP_CONV_64_64(evfsctsi); 1083GEN_SPEFPUOP_CONV_64_64(evfsctuf); 1084GEN_SPEFPUOP_CONV_64_64(evfsctsf); 1085GEN_SPEFPUOP_CONV_64_64(evfsctuiz); 1086GEN_SPEFPUOP_CONV_64_64(evfsctsiz); 1087 1088/* Comparison */ 1089GEN_SPEFPUOP_COMP_64(evfscmpgt); 1090GEN_SPEFPUOP_COMP_64(evfscmplt); 1091GEN_SPEFPUOP_COMP_64(evfscmpeq); 1092GEN_SPEFPUOP_COMP_64(evfststgt); 1093GEN_SPEFPUOP_COMP_64(evfststlt); 1094GEN_SPEFPUOP_COMP_64(evfststeq); 1095 1096/* Opcodes definitions */ 1097GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // 1098GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // 1099GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // 1100GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // 1101GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // 1102GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // 1103GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // 1104GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // 1105GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // 1106GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // 1107GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // 1108GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // 1109GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // 1110GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // 1111 1112/* Single precision floating-point operations */ 1113/* Arithmetic */ 1114GEN_SPEFPUOP_ARITH2_32_32(efsadd); 1115GEN_SPEFPUOP_ARITH2_32_32(efssub); 1116GEN_SPEFPUOP_ARITH2_32_32(efsmul); 1117GEN_SPEFPUOP_ARITH2_32_32(efsdiv); 1118static inline void gen_efsabs(DisasContext *ctx) 1119{ 1120 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1121 (target_long)~0x80000000LL); 1122} 1123static inline void gen_efsnabs(DisasContext *ctx) 1124{ 1125 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1126 0x80000000); 1127} 1128static inline void gen_efsneg(DisasContext *ctx) 1129{ 1130 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1131 0x80000000); 1132} 1133 1134/* Conversion */ 1135GEN_SPEFPUOP_CONV_32_32(efscfui); 1136GEN_SPEFPUOP_CONV_32_32(efscfsi); 1137GEN_SPEFPUOP_CONV_32_32(efscfuf); 1138GEN_SPEFPUOP_CONV_32_32(efscfsf); 1139GEN_SPEFPUOP_CONV_32_32(efsctui); 1140GEN_SPEFPUOP_CONV_32_32(efsctsi); 1141GEN_SPEFPUOP_CONV_32_32(efsctuf); 1142GEN_SPEFPUOP_CONV_32_32(efsctsf); 1143GEN_SPEFPUOP_CONV_32_32(efsctuiz); 1144GEN_SPEFPUOP_CONV_32_32(efsctsiz); 1145GEN_SPEFPUOP_CONV_32_64(efscfd); 1146 1147/* Comparison */ 1148GEN_SPEFPUOP_COMP_32(efscmpgt); 1149GEN_SPEFPUOP_COMP_32(efscmplt); 1150GEN_SPEFPUOP_COMP_32(efscmpeq); 1151GEN_SPEFPUOP_COMP_32(efststgt); 1152GEN_SPEFPUOP_COMP_32(efststlt); 1153GEN_SPEFPUOP_COMP_32(efststeq); 1154 1155/* Opcodes definitions */ 1156GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // 1157GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // 1158GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // 1159GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // 1160GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // 1161GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); // 1162GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // 1163GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // 1164GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // 1165GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // 1166GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // 1167GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // 1168GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // 1169GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // 1170 1171/* Double precision floating-point operations */ 1172/* Arithmetic */ 1173GEN_SPEFPUOP_ARITH2_64_64(efdadd); 1174GEN_SPEFPUOP_ARITH2_64_64(efdsub); 1175GEN_SPEFPUOP_ARITH2_64_64(efdmul); 1176GEN_SPEFPUOP_ARITH2_64_64(efddiv); 1177static inline void gen_efdabs(DisasContext *ctx) 1178{ 1179 if (unlikely(!ctx->spe_enabled)) { 1180 gen_exception(ctx, POWERPC_EXCP_SPEU); 1181 return; 1182 } 1183 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 1184 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 1185 ~0x80000000); 1186} 1187static inline void gen_efdnabs(DisasContext *ctx) 1188{ 1189 if (unlikely(!ctx->spe_enabled)) { 1190 gen_exception(ctx, POWERPC_EXCP_SPEU); 1191 return; 1192 } 1193 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 1194 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 1195 0x80000000); 1196} 1197static inline void gen_efdneg(DisasContext *ctx) 1198{ 1199 if (unlikely(!ctx->spe_enabled)) { 1200 gen_exception(ctx, POWERPC_EXCP_SPEU); 1201 return; 1202 } 1203 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 1204 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 1205 0x80000000); 1206} 1207 1208/* Conversion */ 1209GEN_SPEFPUOP_CONV_64_32(efdcfui); 1210GEN_SPEFPUOP_CONV_64_32(efdcfsi); 1211GEN_SPEFPUOP_CONV_64_32(efdcfuf); 1212GEN_SPEFPUOP_CONV_64_32(efdcfsf); 1213GEN_SPEFPUOP_CONV_32_64(efdctui); 1214GEN_SPEFPUOP_CONV_32_64(efdctsi); 1215GEN_SPEFPUOP_CONV_32_64(efdctuf); 1216GEN_SPEFPUOP_CONV_32_64(efdctsf); 1217GEN_SPEFPUOP_CONV_32_64(efdctuiz); 1218GEN_SPEFPUOP_CONV_32_64(efdctsiz); 1219GEN_SPEFPUOP_CONV_64_32(efdcfs); 1220GEN_SPEFPUOP_CONV_64_64(efdcfuid); 1221GEN_SPEFPUOP_CONV_64_64(efdcfsid); 1222GEN_SPEFPUOP_CONV_64_64(efdctuidz); 1223GEN_SPEFPUOP_CONV_64_64(efdctsidz); 1224 1225/* Comparison */ 1226GEN_SPEFPUOP_COMP_64(efdcmpgt); 1227GEN_SPEFPUOP_COMP_64(efdcmplt); 1228GEN_SPEFPUOP_COMP_64(efdcmpeq); 1229GEN_SPEFPUOP_COMP_64(efdtstgt); 1230GEN_SPEFPUOP_COMP_64(efdtstlt); 1231GEN_SPEFPUOP_COMP_64(efdtsteq); 1232 1233/* Opcodes definitions */ 1234GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // 1235GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // 1236GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); // 1237GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); // 1238GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // 1239GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // 1240GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // 1241GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); // 1242GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // 1243GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // 1244GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // 1245GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // 1246GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // 1247GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // 1248GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // 1249GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // 1250 1251#undef GEN_SPE 1252#undef GEN_SPEOP_LDST