vector-impl.c.inc (1873B)
1/* 2 * Power ISA decode for Vector Facility instructions 3 * 4 * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20#define REQUIRE_ALTIVEC(CTX) \ 21 do { \ 22 if (unlikely(!(CTX)->altivec_enabled)) { \ 23 gen_exception((CTX), POWERPC_EXCP_VPU); \ 24 return true; \ 25 } \ 26 } while (0) 27 28static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a) 29{ 30 TCGv_i64 tgt, src, mask; 31 32 REQUIRE_INSNS_FLAGS2(ctx, ISA310); 33 REQUIRE_ALTIVEC(ctx); 34 35 tgt = tcg_temp_new_i64(); 36 src = tcg_temp_new_i64(); 37 mask = tcg_temp_new_i64(); 38 39 /* centrifuge lower double word */ 40 get_cpu_vsrl(src, a->vra + 32); 41 get_cpu_vsrl(mask, a->vrb + 32); 42 gen_helper_cfuged(tgt, src, mask); 43 set_cpu_vsrl(a->vrt + 32, tgt); 44 45 /* centrifuge higher double word */ 46 get_cpu_vsrh(src, a->vra + 32); 47 get_cpu_vsrh(mask, a->vrb + 32); 48 gen_helper_cfuged(tgt, src, mask); 49 set_cpu_vsrh(a->vrt + 32, tgt); 50 51 tcg_temp_free_i64(tgt); 52 tcg_temp_free_i64(src); 53 tcg_temp_free_i64(mask); 54 55 return true; 56}