cpu.h (15387B)
1/* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20#ifndef RISCV_CPU_H 21#define RISCV_CPU_H 22 23#include "hw/core/cpu.h" 24#include "hw/registerfields.h" 25#include "exec/cpu-defs.h" 26#include "fpu/softfloat-types.h" 27#include "qom/object.h" 28 29#define TCG_GUEST_DEFAULT_MO 0 30 31#define TYPE_RISCV_CPU "riscv-cpu" 32 33#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 34#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 35#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 36 37#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 38#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 39#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 40#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 41#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 42#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 43#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 44#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 45#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 46#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 47 48#if defined(TARGET_RISCV32) 49# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 50#elif defined(TARGET_RISCV64) 51# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 52#endif 53 54#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) 55#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) 56 57#define RV(x) ((target_ulong)1 << (x - 'A')) 58 59#define RVI RV('I') 60#define RVE RV('E') /* E and I are mutually exclusive */ 61#define RVM RV('M') 62#define RVA RV('A') 63#define RVF RV('F') 64#define RVD RV('D') 65#define RVV RV('V') 66#define RVC RV('C') 67#define RVS RV('S') 68#define RVU RV('U') 69#define RVH RV('H') 70 71/* S extension denotes that Supervisor mode exists, however it is possible 72 to have a core that support S mode but does not have an MMU and there 73 is currently no bit in misa to indicate whether an MMU exists or not 74 so a cpu features bitfield is required, likewise for optional PMP support */ 75enum { 76 RISCV_FEATURE_MMU, 77 RISCV_FEATURE_PMP, 78 RISCV_FEATURE_EPMP, 79 RISCV_FEATURE_MISA 80}; 81 82#define PRIV_VERSION_1_10_0 0x00011000 83#define PRIV_VERSION_1_11_0 0x00011100 84 85#define VEXT_VERSION_0_07_1 0x00000701 86 87enum { 88 TRANSLATE_SUCCESS, 89 TRANSLATE_FAIL, 90 TRANSLATE_PMP_FAIL, 91 TRANSLATE_G_STAGE_FAIL 92}; 93 94#define MMU_USER_IDX 3 95 96#define MAX_RISCV_PMPS (16) 97 98typedef struct CPURISCVState CPURISCVState; 99 100#if !defined(CONFIG_USER_ONLY) 101#include "pmp.h" 102#endif 103 104#define RV_VLEN_MAX 256 105 106FIELD(VTYPE, VLMUL, 0, 2) 107FIELD(VTYPE, VSEW, 2, 3) 108FIELD(VTYPE, VEDIV, 5, 2) 109FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) 110FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) 111 112struct CPURISCVState { 113 target_ulong gpr[32]; 114 uint64_t fpr[32]; /* assume both F and D extensions */ 115 116 /* vector coprocessor state. */ 117 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 118 target_ulong vxrm; 119 target_ulong vxsat; 120 target_ulong vl; 121 target_ulong vstart; 122 target_ulong vtype; 123 124 target_ulong pc; 125 target_ulong load_res; 126 target_ulong load_val; 127 128 target_ulong frm; 129 130 target_ulong badaddr; 131 target_ulong guest_phys_fault_addr; 132 133 target_ulong priv_ver; 134 target_ulong bext_ver; 135 target_ulong vext_ver; 136 target_ulong misa; 137 target_ulong misa_mask; 138 139 uint32_t features; 140 141#ifdef CONFIG_USER_ONLY 142 uint32_t elf_flags; 143#endif 144 145#ifndef CONFIG_USER_ONLY 146 target_ulong priv; 147 /* This contains QEMU specific information about the virt state. */ 148 target_ulong virt; 149 target_ulong resetvec; 150 151 target_ulong mhartid; 152 /* 153 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 154 * For RV64 this is a 64-bit mstatus. 155 */ 156 uint64_t mstatus; 157 158 target_ulong mip; 159 160 uint32_t miclaim; 161 162 target_ulong mie; 163 target_ulong mideleg; 164 165 target_ulong satp; /* since: priv-1.10.0 */ 166 target_ulong stval; 167 target_ulong medeleg; 168 169 target_ulong stvec; 170 target_ulong sepc; 171 target_ulong scause; 172 173 target_ulong mtvec; 174 target_ulong mepc; 175 target_ulong mcause; 176 target_ulong mtval; /* since: priv-1.10.0 */ 177 178 /* Hypervisor CSRs */ 179 target_ulong hstatus; 180 target_ulong hedeleg; 181 target_ulong hideleg; 182 target_ulong hcounteren; 183 target_ulong htval; 184 target_ulong htinst; 185 target_ulong hgatp; 186 uint64_t htimedelta; 187 188 /* Virtual CSRs */ 189 /* 190 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 191 * For RV64 this is a 64-bit vsstatus. 192 */ 193 uint64_t vsstatus; 194 target_ulong vstvec; 195 target_ulong vsscratch; 196 target_ulong vsepc; 197 target_ulong vscause; 198 target_ulong vstval; 199 target_ulong vsatp; 200 201 target_ulong mtval2; 202 target_ulong mtinst; 203 204 /* HS Backup CSRs */ 205 target_ulong stvec_hs; 206 target_ulong sscratch_hs; 207 target_ulong sepc_hs; 208 target_ulong scause_hs; 209 target_ulong stval_hs; 210 target_ulong satp_hs; 211 uint64_t mstatus_hs; 212 213 /* Signals whether the current exception occurred with two-stage address 214 translation active. */ 215 bool two_stage_lookup; 216 217 target_ulong scounteren; 218 target_ulong mcounteren; 219 220 target_ulong sscratch; 221 target_ulong mscratch; 222 223 /* temporary htif regs */ 224 uint64_t mfromhost; 225 uint64_t mtohost; 226 uint64_t timecmp; 227 228 /* physical memory protection */ 229 pmp_table_t pmp_state; 230 target_ulong mseccfg; 231 232 /* machine specific rdtime callback */ 233 uint64_t (*rdtime_fn)(uint32_t); 234 uint32_t rdtime_fn_arg; 235 236 /* True if in debugger mode. */ 237 bool debugger; 238#endif 239 240 float_status fp_status; 241 242 /* Fields from here on are preserved across CPU reset. */ 243 QEMUTimer *timer; /* Internal timer */ 244}; 245 246OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, 247 RISCV_CPU) 248 249/** 250 * RISCVCPUClass: 251 * @parent_realize: The parent class' realize handler. 252 * @parent_reset: The parent class' reset handler. 253 * 254 * A RISCV CPU model. 255 */ 256struct RISCVCPUClass { 257 /*< private >*/ 258 CPUClass parent_class; 259 /*< public >*/ 260 DeviceRealize parent_realize; 261 DeviceReset parent_reset; 262}; 263 264/** 265 * RISCVCPU: 266 * @env: #CPURISCVState 267 * 268 * A RISCV CPU. 269 */ 270struct RISCVCPU { 271 /*< private >*/ 272 CPUState parent_obj; 273 /*< public >*/ 274 CPUNegativeOffsetState neg; 275 CPURISCVState env; 276 277 char *dyn_csr_xml; 278 279 /* Configuration Settings */ 280 struct { 281 bool ext_i; 282 bool ext_e; 283 bool ext_g; 284 bool ext_m; 285 bool ext_a; 286 bool ext_f; 287 bool ext_d; 288 bool ext_c; 289 bool ext_s; 290 bool ext_u; 291 bool ext_h; 292 bool ext_v; 293 bool ext_zba; 294 bool ext_zbb; 295 bool ext_zbc; 296 bool ext_zbs; 297 bool ext_counters; 298 bool ext_ifencei; 299 bool ext_icsr; 300 301 char *priv_spec; 302 char *user_spec; 303 char *bext_spec; 304 char *vext_spec; 305 uint16_t vlen; 306 uint16_t elen; 307 bool mmu; 308 bool pmp; 309 bool epmp; 310 uint64_t resetvec; 311 } cfg; 312}; 313 314static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 315{ 316 return (env->misa & ext) != 0; 317} 318 319static inline bool riscv_feature(CPURISCVState *env, int feature) 320{ 321 return env->features & (1ULL << feature); 322} 323 324#include "cpu_user.h" 325#include "cpu_bits.h" 326 327extern const char * const riscv_int_regnames[]; 328extern const char * const riscv_fpr_regnames[]; 329 330const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 331void riscv_cpu_do_interrupt(CPUState *cpu); 332int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 333 int cpuid, void *opaque); 334int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 335 int cpuid, void *opaque); 336int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 337int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 338bool riscv_cpu_fp_enabled(CPURISCVState *env); 339bool riscv_cpu_virt_enabled(CPURISCVState *env); 340void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 341bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); 342void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); 343bool riscv_cpu_two_stage_lookup(int mmu_idx); 344int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 345hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 346void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 347 MMUAccessType access_type, int mmu_idx, 348 uintptr_t retaddr) QEMU_NORETURN; 349bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 350 MMUAccessType access_type, int mmu_idx, 351 bool probe, uintptr_t retaddr); 352void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 353 vaddr addr, unsigned size, 354 MMUAccessType access_type, 355 int mmu_idx, MemTxAttrs attrs, 356 MemTxResult response, uintptr_t retaddr); 357char *riscv_isa_string(RISCVCPU *cpu); 358void riscv_cpu_list(void); 359 360#define cpu_list riscv_cpu_list 361#define cpu_mmu_index riscv_cpu_mmu_index 362 363#ifndef CONFIG_USER_ONLY 364bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 365void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 366int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 367uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 368#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 369void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 370 uint32_t arg); 371#endif 372void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 373 374void riscv_translate_init(void); 375void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 376 uint32_t exception, uintptr_t pc); 377 378target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 379void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 380 381#define TB_FLAGS_MMU_MASK 7 382#define TB_FLAGS_PRIV_MMU_MASK 3 383#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 384#define TB_FLAGS_MSTATUS_FS MSTATUS_FS 385 386typedef CPURISCVState CPUArchState; 387typedef RISCVCPU ArchCPU; 388#include "exec/cpu-all.h" 389 390FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1) 391FIELD(TB_FLAGS, LMUL, 3, 2) 392FIELD(TB_FLAGS, SEW, 5, 3) 393FIELD(TB_FLAGS, VILL, 8, 1) 394/* Is a Hypervisor instruction load/store allowed? */ 395FIELD(TB_FLAGS, HLSX, 9, 1) 396FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2) 397 398bool riscv_cpu_is_32bit(CPURISCVState *env); 399 400/* 401 * A simplification for VLMAX 402 * = (1 << LMUL) * VLEN / (8 * (1 << SEW)) 403 * = (VLEN << LMUL) / (8 << SEW) 404 * = (VLEN << LMUL) >> (SEW + 3) 405 * = VLEN >> (SEW + 3 - LMUL) 406 */ 407static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 408{ 409 uint8_t sew, lmul; 410 411 sew = FIELD_EX64(vtype, VTYPE, VSEW); 412 lmul = FIELD_EX64(vtype, VTYPE, VLMUL); 413 return cpu->cfg.vlen >> (sew + 3 - lmul); 414} 415 416static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 417 target_ulong *cs_base, uint32_t *pflags) 418{ 419 uint32_t flags = 0; 420 421 *pc = env->pc; 422 *cs_base = 0; 423 424 if (riscv_has_ext(env, RVV)) { 425 uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); 426 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); 427 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 428 FIELD_EX64(env->vtype, VTYPE, VILL)); 429 flags = FIELD_DP32(flags, TB_FLAGS, SEW, 430 FIELD_EX64(env->vtype, VTYPE, VSEW)); 431 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, 432 FIELD_EX64(env->vtype, VTYPE, VLMUL)); 433 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); 434 } else { 435 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); 436 } 437 438#ifdef CONFIG_USER_ONLY 439 flags |= TB_FLAGS_MSTATUS_FS; 440#else 441 flags |= cpu_mmu_index(env, 0); 442 if (riscv_cpu_fp_enabled(env)) { 443 flags |= env->mstatus & MSTATUS_FS; 444 } 445 446 if (riscv_has_ext(env, RVH)) { 447 if (env->priv == PRV_M || 448 (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 449 (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && 450 get_field(env->hstatus, HSTATUS_HU))) { 451 flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); 452 } 453 454 flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, 455 get_field(env->mstatus_hs, MSTATUS_FS)); 456 } 457#endif 458 459 *pflags = flags; 460} 461 462RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 463 target_ulong *ret_value, 464 target_ulong new_value, target_ulong write_mask); 465RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 466 target_ulong *ret_value, 467 target_ulong new_value, 468 target_ulong write_mask); 469 470static inline void riscv_csr_write(CPURISCVState *env, int csrno, 471 target_ulong val) 472{ 473 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 474} 475 476static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 477{ 478 target_ulong val = 0; 479 riscv_csrrw(env, csrno, &val, 0, 0); 480 return val; 481} 482 483typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 484 int csrno); 485typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 486 target_ulong *ret_value); 487typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 488 target_ulong new_value); 489typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 490 target_ulong *ret_value, 491 target_ulong new_value, 492 target_ulong write_mask); 493 494typedef struct { 495 const char *name; 496 riscv_csr_predicate_fn predicate; 497 riscv_csr_read_fn read; 498 riscv_csr_write_fn write; 499 riscv_csr_op_fn op; 500} riscv_csr_operations; 501 502/* CSR function table constants */ 503enum { 504 CSR_TABLE_SIZE = 0x1000 505}; 506 507/* CSR function table */ 508extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 509 510void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 511void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 512 513void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 514 515#endif /* RISCV_CPU_H */