cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

trans_privileged.c.inc (3915B)

      1/*
      2 * RISC-V translation routines for the RISC-V privileged instructions.
      3 *
      4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
      5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
      6 *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
      7 *
      8 * This program is free software; you can redistribute it and/or modify it
      9 * under the terms and conditions of the GNU General Public License,
     10 * version 2 or later, as published by the Free Software Foundation.
     11 *
     12 * This program is distributed in the hope it will be useful, but WITHOUT
     13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
     14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
     15 * more details.
     16 *
     17 * You should have received a copy of the GNU General Public License along with
     18 * this program.  If not, see <http://www.gnu.org/licenses/>.
     19 */
     20
     21static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
     22{
     23    /* always generates U-level ECALL, fixed in do_interrupt handler */
     24    generate_exception(ctx, RISCV_EXCP_U_ECALL);
     25    exit_tb(ctx); /* no chaining */
     26    ctx->base.is_jmp = DISAS_NORETURN;
     27    return true;
     28}
     29
     30static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
     31{
     32    target_ulong    ebreak_addr = ctx->base.pc_next;
     33    target_ulong    pre_addr = ebreak_addr - 4;
     34    target_ulong    post_addr = ebreak_addr + 4;
     35    uint32_t pre    = 0;
     36    uint32_t ebreak = 0;
     37    uint32_t post   = 0;
     38
     39    /*
     40     * The RISC-V semihosting spec specifies the following
     41     * three-instruction sequence to flag a semihosting call:
     42     *
     43     *      slli zero, zero, 0x1f       0x01f01013
     44     *      ebreak                      0x00100073
     45     *      srai zero, zero, 0x7        0x40705013
     46     *
     47     * The two shift operations on the zero register are no-ops, used
     48     * here to signify a semihosting exception, rather than a breakpoint.
     49     *
     50     * Uncompressed instructions are required so that the sequence is easy
     51     * to validate.
     52     *
     53     * The three instructions are required to lie in the same page so
     54     * that no exception will be raised when fetching them.
     55     */
     56
     57    if ((pre_addr & TARGET_PAGE_MASK) == (post_addr & TARGET_PAGE_MASK)) {
     58        pre    = opcode_at(&ctx->base, pre_addr);
     59        ebreak = opcode_at(&ctx->base, ebreak_addr);
     60        post   = opcode_at(&ctx->base, post_addr);
     61    }
     62
     63    if  (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
     64        generate_exception(ctx, RISCV_EXCP_SEMIHOST);
     65    } else {
     66        generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
     67    }
     68    exit_tb(ctx); /* no chaining */
     69    ctx->base.is_jmp = DISAS_NORETURN;
     70    return true;
     71}
     72
     73static bool trans_uret(DisasContext *ctx, arg_uret *a)
     74{
     75    return false;
     76}
     77
     78static bool trans_sret(DisasContext *ctx, arg_sret *a)
     79{
     80#ifndef CONFIG_USER_ONLY
     81    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
     82
     83    if (has_ext(ctx, RVS)) {
     84        gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
     85        exit_tb(ctx); /* no chaining */
     86        ctx->base.is_jmp = DISAS_NORETURN;
     87    } else {
     88        return false;
     89    }
     90    return true;
     91#else
     92    return false;
     93#endif
     94}
     95
     96static bool trans_mret(DisasContext *ctx, arg_mret *a)
     97{
     98#ifndef CONFIG_USER_ONLY
     99    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
    100    gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
    101    exit_tb(ctx); /* no chaining */
    102    ctx->base.is_jmp = DISAS_NORETURN;
    103    return true;
    104#else
    105    return false;
    106#endif
    107}
    108
    109static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
    110{
    111#ifndef CONFIG_USER_ONLY
    112    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
    113    gen_helper_wfi(cpu_env);
    114    return true;
    115#else
    116    return false;
    117#endif
    118}
    119
    120static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
    121{
    122#ifndef CONFIG_USER_ONLY
    123    gen_helper_tlb_flush(cpu_env);
    124    return true;
    125#endif
    126    return false;
    127}
    128
    129static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
    130{
    131    return false;
    132}