cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

meson.build (704B)

      1# FIXME extra_args should accept files()
      2dir = meson.current_source_dir()
      3
      4gen = [
      5  decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']),
      6  decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
      7]
      8
      9riscv_ss = ss.source_set()
     10riscv_ss.add(gen)
     11riscv_ss.add(files(
     12  'cpu.c',
     13  'cpu_helper.c',
     14  'csr.c',
     15  'fpu_helper.c',
     16  'gdbstub.c',
     17  'op_helper.c',
     18  'vector_helper.c',
     19  'bitmanip_helper.c',
     20  'translate.c',
     21))
     22
     23riscv_softmmu_ss = ss.source_set()
     24riscv_softmmu_ss.add(files(
     25  'arch_dump.c',
     26  'pmp.c',
     27  'monitor.c',
     28  'machine.c'
     29))
     30
     31target_arch += {'riscv': riscv_ss}
     32target_softmmu_arch += {'riscv': riscv_softmmu_ss}