cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

pmp.h (2808B)

      1/*
      2 * QEMU RISC-V PMP (Physical Memory Protection)
      3 *
      4 * Author: Daire McNamara, daire.mcnamara@emdalo.com
      5 *         Ivan Griffin, ivan.griffin@emdalo.com
      6 *
      7 * This provides a RISC-V Physical Memory Protection interface
      8 *
      9 * This program is free software; you can redistribute it and/or modify it
     10 * under the terms and conditions of the GNU General Public License,
     11 * version 2 or later, as published by the Free Software Foundation.
     12 *
     13 * This program is distributed in the hope it will be useful, but WITHOUT
     14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
     15 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
     16 * more details.
     17 *
     18 * You should have received a copy of the GNU General Public License along with
     19 * this program.  If not, see <http://www.gnu.org/licenses/>.
     20 */
     21
     22#ifndef RISCV_PMP_H
     23#define RISCV_PMP_H
     24
     25typedef enum {
     26    PMP_READ  = 1 << 0,
     27    PMP_WRITE = 1 << 1,
     28    PMP_EXEC  = 1 << 2,
     29    PMP_LOCK  = 1 << 7
     30} pmp_priv_t;
     31
     32typedef enum {
     33    PMP_AMATCH_OFF,  /* Null (off)                            */
     34    PMP_AMATCH_TOR,  /* Top of Range                          */
     35    PMP_AMATCH_NA4,  /* Naturally aligned four-byte region    */
     36    PMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */
     37} pmp_am_t;
     38
     39typedef enum {
     40    MSECCFG_MML  = 1 << 0,
     41    MSECCFG_MMWP = 1 << 1,
     42    MSECCFG_RLB  = 1 << 2
     43} mseccfg_field_t;
     44
     45typedef struct {
     46    target_ulong addr_reg;
     47    uint8_t  cfg_reg;
     48} pmp_entry_t;
     49
     50typedef struct {
     51    target_ulong sa;
     52    target_ulong ea;
     53} pmp_addr_t;
     54
     55typedef struct {
     56    pmp_entry_t pmp[MAX_RISCV_PMPS];
     57    pmp_addr_t  addr[MAX_RISCV_PMPS];
     58    uint32_t num_rules;
     59} pmp_table_t;
     60
     61void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
     62    target_ulong val);
     63target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
     64
     65void mseccfg_csr_write(CPURISCVState *env, target_ulong val);
     66target_ulong mseccfg_csr_read(CPURISCVState *env);
     67
     68void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
     69    target_ulong val);
     70target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
     71bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
     72    target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs,
     73    target_ulong mode);
     74bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
     75                         target_ulong *tlb_size);
     76void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
     77void pmp_update_rule_nums(CPURISCVState *env);
     78uint32_t pmp_get_num_rules(CPURISCVState *env);
     79int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
     80
     81#define MSECCFG_MML_ISSET(env) get_field(env->mseccfg, MSECCFG_MML)
     82#define MSECCFG_MMWP_ISSET(env) get_field(env->mseccfg, MSECCFG_MMWP)
     83#define MSECCFG_RLB_ISSET(env) get_field(env->mseccfg, MSECCFG_RLB)
     84
     85#endif