cpu.h (4948B)
1/* 2 * RX emulation definition 3 * 4 * Copyright (c) 2019 Yoshinori Sato 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19#ifndef RX_CPU_H 20#define RX_CPU_H 21 22#include "qemu/bitops.h" 23#include "qemu-common.h" 24#include "hw/registerfields.h" 25#include "cpu-qom.h" 26 27#include "exec/cpu-defs.h" 28 29/* PSW define */ 30REG32(PSW, 0) 31FIELD(PSW, C, 0, 1) 32FIELD(PSW, Z, 1, 1) 33FIELD(PSW, S, 2, 1) 34FIELD(PSW, O, 3, 1) 35FIELD(PSW, I, 16, 1) 36FIELD(PSW, U, 17, 1) 37FIELD(PSW, PM, 20, 1) 38FIELD(PSW, IPL, 24, 4) 39 40/* FPSW define */ 41REG32(FPSW, 0) 42FIELD(FPSW, RM, 0, 2) 43FIELD(FPSW, CV, 2, 1) 44FIELD(FPSW, CO, 3, 1) 45FIELD(FPSW, CZ, 4, 1) 46FIELD(FPSW, CU, 5, 1) 47FIELD(FPSW, CX, 6, 1) 48FIELD(FPSW, CE, 7, 1) 49FIELD(FPSW, CAUSE, 2, 6) 50FIELD(FPSW, DN, 8, 1) 51FIELD(FPSW, EV, 10, 1) 52FIELD(FPSW, EO, 11, 1) 53FIELD(FPSW, EZ, 12, 1) 54FIELD(FPSW, EU, 13, 1) 55FIELD(FPSW, EX, 14, 1) 56FIELD(FPSW, ENABLE, 10, 5) 57FIELD(FPSW, FV, 26, 1) 58FIELD(FPSW, FO, 27, 1) 59FIELD(FPSW, FZ, 28, 1) 60FIELD(FPSW, FU, 29, 1) 61FIELD(FPSW, FX, 30, 1) 62FIELD(FPSW, FLAGS, 26, 4) 63FIELD(FPSW, FS, 31, 1) 64 65enum { 66 NUM_REGS = 16, 67}; 68 69typedef struct CPURXState { 70 /* CPU registers */ 71 uint32_t regs[NUM_REGS]; /* general registers */ 72 uint32_t psw_o; /* O bit of status register */ 73 uint32_t psw_s; /* S bit of status register */ 74 uint32_t psw_z; /* Z bit of status register */ 75 uint32_t psw_c; /* C bit of status register */ 76 uint32_t psw_u; 77 uint32_t psw_i; 78 uint32_t psw_pm; 79 uint32_t psw_ipl; 80 uint32_t bpsw; /* backup status */ 81 uint32_t bpc; /* backup pc */ 82 uint32_t isp; /* global base register */ 83 uint32_t usp; /* vector base register */ 84 uint32_t pc; /* program counter */ 85 uint32_t intb; /* interrupt vector */ 86 uint32_t fintv; 87 uint32_t fpsw; 88 uint64_t acc; 89 90 /* Fields up to this point are cleared by a CPU reset */ 91 struct {} end_reset_fields; 92 93 /* Internal use */ 94 uint32_t in_sleep; 95 uint32_t req_irq; /* Requested interrupt no (hard) */ 96 uint32_t req_ipl; /* Requested interrupt level */ 97 uint32_t ack_irq; /* execute irq */ 98 uint32_t ack_ipl; /* execute ipl */ 99 float_status fp_status; 100 qemu_irq ack; /* Interrupt acknowledge */ 101} CPURXState; 102 103/* 104 * RXCPU: 105 * @env: #CPURXState 106 * 107 * A RX CPU 108 */ 109struct RXCPU { 110 /*< private >*/ 111 CPUState parent_obj; 112 /*< public >*/ 113 114 CPUNegativeOffsetState neg; 115 CPURXState env; 116}; 117 118typedef RXCPU ArchCPU; 119 120#define ENV_OFFSET offsetof(RXCPU, env) 121 122#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU 123#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX 124#define CPU_RESOLVING_TYPE TYPE_RX_CPU 125 126const char *rx_crname(uint8_t cr); 127#ifndef CONFIG_USER_ONLY 128void rx_cpu_do_interrupt(CPUState *cpu); 129bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req); 130#endif /* !CONFIG_USER_ONLY */ 131void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 132int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 133int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 134hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 135 136void rx_translate_init(void); 137void rx_cpu_list(void); 138void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte); 139 140#define cpu_list rx_cpu_list 141 142#include "exec/cpu-all.h" 143 144#define CPU_INTERRUPT_SOFT CPU_INTERRUPT_TGT_INT_0 145#define CPU_INTERRUPT_FIR CPU_INTERRUPT_TGT_INT_1 146 147#define RX_CPU_IRQ 0 148#define RX_CPU_FIR 1 149 150static inline void cpu_get_tb_cpu_state(CPURXState *env, target_ulong *pc, 151 target_ulong *cs_base, uint32_t *flags) 152{ 153 *pc = env->pc; 154 *cs_base = 0; 155 *flags = FIELD_DP32(0, PSW, PM, env->psw_pm); 156} 157 158static inline int cpu_mmu_index(CPURXState *env, bool ifetch) 159{ 160 return 0; 161} 162 163static inline uint32_t rx_cpu_pack_psw(CPURXState *env) 164{ 165 uint32_t psw = 0; 166 psw = FIELD_DP32(psw, PSW, IPL, env->psw_ipl); 167 psw = FIELD_DP32(psw, PSW, PM, env->psw_pm); 168 psw = FIELD_DP32(psw, PSW, U, env->psw_u); 169 psw = FIELD_DP32(psw, PSW, I, env->psw_i); 170 psw = FIELD_DP32(psw, PSW, O, env->psw_o >> 31); 171 psw = FIELD_DP32(psw, PSW, S, env->psw_s >> 31); 172 psw = FIELD_DP32(psw, PSW, Z, env->psw_z == 0); 173 psw = FIELD_DP32(psw, PSW, C, env->psw_c); 174 return psw; 175} 176 177#endif /* RX_CPU_H */