cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

int64_helper.c (9433B)

      1/*
      2 * Sparc64 interrupt helpers
      3 *
      4 *  Copyright (c) 2003-2005 Fabrice Bellard
      5 *
      6 * This library is free software; you can redistribute it and/or
      7 * modify it under the terms of the GNU Lesser General Public
      8 * License as published by the Free Software Foundation; either
      9 * version 2.1 of the License, or (at your option) any later version.
     10 *
     11 * This library is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     14 * Lesser General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU Lesser General Public
     17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
     18 */
     19
     20#include "qemu/osdep.h"
     21#include "qemu/main-loop.h"
     22#include "cpu.h"
     23#include "exec/helper-proto.h"
     24#include "exec/log.h"
     25#include "trace.h"
     26
     27#define DEBUG_PCALL
     28
     29#ifdef DEBUG_PCALL
     30static const char * const excp_names[0x80] = {
     31    [TT_TFAULT] = "Instruction Access Fault",
     32    [TT_TMISS] = "Instruction Access MMU Miss",
     33    [TT_CODE_ACCESS] = "Instruction Access Error",
     34    [TT_ILL_INSN] = "Illegal Instruction",
     35    [TT_PRIV_INSN] = "Privileged Instruction",
     36    [TT_NFPU_INSN] = "FPU Disabled",
     37    [TT_FP_EXCP] = "FPU Exception",
     38    [TT_TOVF] = "Tag Overflow",
     39    [TT_CLRWIN] = "Clean Windows",
     40    [TT_DIV_ZERO] = "Division By Zero",
     41    [TT_DFAULT] = "Data Access Fault",
     42    [TT_DMISS] = "Data Access MMU Miss",
     43    [TT_DATA_ACCESS] = "Data Access Error",
     44    [TT_DPROT] = "Data Protection Error",
     45    [TT_UNALIGNED] = "Unaligned Memory Access",
     46    [TT_PRIV_ACT] = "Privileged Action",
     47    [TT_EXTINT | 0x1] = "External Interrupt 1",
     48    [TT_EXTINT | 0x2] = "External Interrupt 2",
     49    [TT_EXTINT | 0x3] = "External Interrupt 3",
     50    [TT_EXTINT | 0x4] = "External Interrupt 4",
     51    [TT_EXTINT | 0x5] = "External Interrupt 5",
     52    [TT_EXTINT | 0x6] = "External Interrupt 6",
     53    [TT_EXTINT | 0x7] = "External Interrupt 7",
     54    [TT_EXTINT | 0x8] = "External Interrupt 8",
     55    [TT_EXTINT | 0x9] = "External Interrupt 9",
     56    [TT_EXTINT | 0xa] = "External Interrupt 10",
     57    [TT_EXTINT | 0xb] = "External Interrupt 11",
     58    [TT_EXTINT | 0xc] = "External Interrupt 12",
     59    [TT_EXTINT | 0xd] = "External Interrupt 13",
     60    [TT_EXTINT | 0xe] = "External Interrupt 14",
     61    [TT_EXTINT | 0xf] = "External Interrupt 15",
     62};
     63#endif
     64
     65void cpu_check_irqs(CPUSPARCState *env)
     66{
     67    CPUState *cs;
     68    uint32_t pil = env->pil_in |
     69                  (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
     70
     71    /* We should be holding the BQL before we mess with IRQs */
     72    g_assert(qemu_mutex_iothread_locked());
     73
     74    /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
     75    if (env->ivec_status & 0x20) {
     76        return;
     77    }
     78    cs = env_cpu(env);
     79    /*
     80     * check if TM or SM in SOFTINT are set
     81     * setting these also causes interrupt 14
     82     */
     83    if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
     84        pil |= 1 << 14;
     85    }
     86
     87    /*
     88     * The bit corresponding to psrpil is (1<< psrpil),
     89     * the next bit is (2 << psrpil).
     90     */
     91    if (pil < (2 << env->psrpil)) {
     92        if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
     93            trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
     94            env->interrupt_index = 0;
     95            cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
     96        }
     97        return;
     98    }
     99
    100    if (cpu_interrupts_enabled(env)) {
    101
    102        unsigned int i;
    103
    104        for (i = 15; i > env->psrpil; i--) {
    105            if (pil & (1 << i)) {
    106                int old_interrupt = env->interrupt_index;
    107                int new_interrupt = TT_EXTINT | i;
    108
    109                if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
    110                  && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
    111                    trace_sparc64_cpu_check_irqs_noset_irq(env->tl,
    112                                                      cpu_tsptr(env)->tt,
    113                                                      new_interrupt);
    114                } else if (old_interrupt != new_interrupt) {
    115                    env->interrupt_index = new_interrupt;
    116                    trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt,
    117                                                         new_interrupt);
    118                    cpu_interrupt(cs, CPU_INTERRUPT_HARD);
    119                }
    120                break;
    121            }
    122        }
    123    } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
    124        trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint,
    125                                              env->interrupt_index);
    126        env->interrupt_index = 0;
    127        cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
    128    }
    129}
    130
    131void sparc_cpu_do_interrupt(CPUState *cs)
    132{
    133    SPARCCPU *cpu = SPARC_CPU(cs);
    134    CPUSPARCState *env = &cpu->env;
    135    int intno = cs->exception_index;
    136    trap_state *tsptr;
    137
    138    /* Compute PSR before exposing state.  */
    139    if (env->cc_op != CC_OP_FLAGS) {
    140        cpu_get_psr(env);
    141    }
    142
    143#ifdef DEBUG_PCALL
    144    if (qemu_loglevel_mask(CPU_LOG_INT)) {
    145        static int count;
    146        const char *name;
    147
    148        if (intno < 0 || intno >= 0x1ff) {
    149            name = "Unknown";
    150        } else if (intno >= 0x180) {
    151            name = "Hyperprivileged Trap Instruction";
    152        } else if (intno >= 0x100) {
    153            name = "Trap Instruction";
    154        } else if (intno >= 0xc0) {
    155            name = "Window Fill";
    156        } else if (intno >= 0x80) {
    157            name = "Window Spill";
    158        } else {
    159            name = excp_names[intno];
    160            if (!name) {
    161                name = "Unknown";
    162            }
    163        }
    164
    165        qemu_log("%6d: %s (v=%04x)\n", count, name, intno);
    166        log_cpu_state(cs, 0);
    167#if 0
    168        {
    169            int i;
    170            uint8_t *ptr;
    171
    172            qemu_log("       code=");
    173            ptr = (uint8_t *)env->pc;
    174            for (i = 0; i < 16; i++) {
    175                qemu_log(" %02x", ldub(ptr + i));
    176            }
    177            qemu_log("\n");
    178        }
    179#endif
    180        count++;
    181    }
    182#endif
    183#if !defined(CONFIG_USER_ONLY)
    184    if (env->tl >= env->maxtl) {
    185        cpu_abort(cs, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
    186                  " Error state", cs->exception_index, env->tl, env->maxtl);
    187        return;
    188    }
    189#endif
    190    if (env->tl < env->maxtl - 1) {
    191        env->tl++;
    192    } else {
    193        env->pstate |= PS_RED;
    194        if (env->tl < env->maxtl) {
    195            env->tl++;
    196        }
    197    }
    198    tsptr = cpu_tsptr(env);
    199
    200    tsptr->tstate = sparc64_tstate(env);
    201    tsptr->tpc = env->pc;
    202    tsptr->tnpc = env->npc;
    203    tsptr->tt = intno;
    204
    205    if (cpu_has_hypervisor(env)) {
    206        env->htstate[env->tl] = env->hpstate;
    207        /* XXX OpenSPARC T1 - UltraSPARC T3 have MAXPTL=2
    208           but this may change in the future */
    209        if (env->tl > 2) {
    210            env->hpstate |= HS_PRIV;
    211        }
    212    }
    213
    214    if (env->def.features & CPU_FEATURE_GL) {
    215        cpu_gl_switch_gregs(env, env->gl + 1);
    216        env->gl++;
    217    }
    218
    219    switch (intno) {
    220    case TT_IVEC:
    221        if (!cpu_has_hypervisor(env)) {
    222            cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_IG);
    223        }
    224        break;
    225    case TT_TFAULT:
    226    case TT_DFAULT:
    227    case TT_TMISS ... TT_TMISS + 3:
    228    case TT_DMISS ... TT_DMISS + 3:
    229    case TT_DPROT ... TT_DPROT + 3:
    230        if (cpu_has_hypervisor(env)) {
    231            env->hpstate |= HS_PRIV;
    232            env->pstate = PS_PEF | PS_PRIV;
    233        } else {
    234            cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_MG);
    235        }
    236        break;
    237    case TT_INSN_REAL_TRANSLATION_MISS ... TT_DATA_REAL_TRANSLATION_MISS:
    238    case TT_HTRAP ... TT_HTRAP + 127:
    239        env->hpstate |= HS_PRIV;
    240        break;
    241    default:
    242        cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_AG);
    243        break;
    244    }
    245
    246    if (intno == TT_CLRWIN) {
    247        cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
    248    } else if ((intno & 0x1c0) == TT_SPILL) {
    249        cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
    250    } else if ((intno & 0x1c0) == TT_FILL) {
    251        cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
    252    }
    253
    254    if (cpu_hypervisor_mode(env)) {
    255        env->pc = (env->htba & ~0x3fffULL) | (intno << 5);
    256    } else {
    257        env->pc = env->tbr  & ~0x7fffULL;
    258        env->pc |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
    259    }
    260    env->npc = env->pc + 4;
    261    cs->exception_index = -1;
    262}
    263
    264trap_state *cpu_tsptr(CPUSPARCState* env)
    265{
    266    return &env->ts[env->tl & MAXTL_MASK];
    267}
    268
    269static bool do_modify_softint(CPUSPARCState *env, uint32_t value)
    270{
    271    if (env->softint != value) {
    272        env->softint = value;
    273#if !defined(CONFIG_USER_ONLY)
    274        if (cpu_interrupts_enabled(env)) {
    275            qemu_mutex_lock_iothread();
    276            cpu_check_irqs(env);
    277            qemu_mutex_unlock_iothread();
    278        }
    279#endif
    280        return true;
    281    }
    282    return false;
    283}
    284
    285void helper_set_softint(CPUSPARCState *env, uint64_t value)
    286{
    287    if (do_modify_softint(env, env->softint | (uint32_t)value)) {
    288        trace_int_helper_set_softint(env->softint);
    289    }
    290}
    291
    292void helper_clear_softint(CPUSPARCState *env, uint64_t value)
    293{
    294    if (do_modify_softint(env, env->softint & (uint32_t)~value)) {
    295        trace_int_helper_clear_softint(env->softint);
    296    }
    297}
    298
    299void helper_write_softint(CPUSPARCState *env, uint64_t value)
    300{
    301    if (do_modify_softint(env, (uint32_t)value)) {
    302        trace_int_helper_write_softint(env->softint);
    303    }
    304}