cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

tricore-opcodes.h (68169B)


      1/*
      2 *  Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
      3 *
      4 * This library is free software; you can redistribute it and/or
      5 * modify it under the terms of the GNU Lesser General Public
      6 * License as published by the Free Software Foundation; either
      7 * version 2.1 of the License, or (at your option) any later version.
      8 *
      9 * This library is distributed in the hope that it will be useful,
     10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     12 * Lesser General Public License for more details.
     13 *
     14 * You should have received a copy of the GNU Lesser General Public
     15 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
     16 */
     17
     18#ifndef TARGET_TRICORE_TRICORE_OPCODES_H
     19#define TARGET_TRICORE_TRICORE_OPCODES_H
     20
     21/*
     22 * Opcode Masks for Tricore
     23 * Format MASK_OP_InstrFormatName_Field
     24 */
     25
     26/* This creates a mask with bits start .. end set to 1 and applies it to op */
     27#define MASK_BITS_SHIFT(op, start, end) (extract32(op, (start), \
     28                                        (end) - (start) + 1))
     29#define MASK_BITS_SHIFT_SEXT(op, start, end) (sextract32(op, (start),\
     30                                             (end) - (start) + 1))
     31
     32/* new opcode masks */
     33
     34#define MASK_OP_MAJOR(op)      MASK_BITS_SHIFT(op, 0, 7)
     35
     36/* 16-Bit Formats */
     37#define MASK_OP_SB_DISP8(op)   MASK_BITS_SHIFT(op, 8, 15)
     38#define MASK_OP_SB_DISP8_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 8, 15)
     39
     40#define MASK_OP_SBC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
     41#define MASK_OP_SBC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
     42#define MASK_OP_SBC_DISP4(op)  MASK_BITS_SHIFT(op, 8, 11)
     43
     44#define MASK_OP_SBR_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
     45#define MASK_OP_SBR_DISP4(op)  MASK_BITS_SHIFT(op, 8, 11)
     46
     47#define MASK_OP_SBRN_N(op)     MASK_BITS_SHIFT(op, 12, 15)
     48#define MASK_OP_SBRN_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
     49
     50#define MASK_OP_SC_CONST8(op)  MASK_BITS_SHIFT(op, 8, 15)
     51
     52#define MASK_OP_SLR_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
     53#define MASK_OP_SLR_D(op)      MASK_BITS_SHIFT(op, 8, 11)
     54
     55#define MASK_OP_SLRO_OFF4(op)  MASK_BITS_SHIFT(op, 12, 15)
     56#define MASK_OP_SLRO_D(op)     MASK_BITS_SHIFT(op, 8, 11)
     57
     58#define MASK_OP_SR_OP2(op)     MASK_BITS_SHIFT(op, 12, 15)
     59#define MASK_OP_SR_S1D(op)     MASK_BITS_SHIFT(op, 8, 11)
     60
     61#define MASK_OP_SRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
     62#define MASK_OP_SRC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
     63#define MASK_OP_SRC_S1D(op)    MASK_BITS_SHIFT(op, 8, 11)
     64
     65#define MASK_OP_SRO_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
     66#define MASK_OP_SRO_OFF4(op)   MASK_BITS_SHIFT(op, 8, 11)
     67
     68#define MASK_OP_SRR_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
     69#define MASK_OP_SRR_S1D(op)    MASK_BITS_SHIFT(op, 8, 11)
     70
     71#define MASK_OP_SRRS_S2(op)    MASK_BITS_SHIFT(op, 12, 15)
     72#define MASK_OP_SRRS_S1D(op)   MASK_BITS_SHIFT(op, 8, 11)
     73#define MASK_OP_SRRS_N(op)     MASK_BITS_SHIFT(op, 6, 7)
     74
     75#define MASK_OP_SSR_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
     76#define MASK_OP_SSR_S1(op)     MASK_BITS_SHIFT(op, 8, 11)
     77
     78#define MASK_OP_SSRO_OFF4(op)  MASK_BITS_SHIFT(op, 12, 15)
     79#define MASK_OP_SSRO_S1(op)    MASK_BITS_SHIFT(op, 8, 11)
     80
     81/* 32-Bit Formats */
     82
     83/* ABS Format */
     84#define MASK_OP_ABS_OFF18(op)  (MASK_BITS_SHIFT(op, 16, 21) +       \
     85                               (MASK_BITS_SHIFT(op, 28, 31) << 6) + \
     86                               (MASK_BITS_SHIFT(op, 22, 25) << 10) +\
     87                               (MASK_BITS_SHIFT(op, 12, 15) << 14))
     88#define MASK_OP_ABS_OP2(op)    MASK_BITS_SHIFT(op, 26, 27)
     89#define MASK_OP_ABS_S1D(op)    MASK_BITS_SHIFT(op, 8, 11)
     90
     91/* ABSB Format */
     92#define MASK_OP_ABSB_OFF18(op) MASK_OP_ABS_OFF18(op)
     93#define MASK_OP_ABSB_OP2(op)   MASK_BITS_SHIFT(op, 26, 27)
     94#define MASK_OP_ABSB_B(op)     MASK_BITS_SHIFT(op, 11, 11)
     95#define MASK_OP_ABSB_BPOS(op)  MASK_BITS_SHIFT(op, 8, 10)
     96
     97/* B Format   */
     98#define MASK_OP_B_DISP24(op)   (MASK_BITS_SHIFT(op, 16, 31) + \
     99                               (MASK_BITS_SHIFT(op, 8, 15) << 16))
    100#define MASK_OP_B_DISP24_SEXT(op)   (MASK_BITS_SHIFT(op, 16, 31) + \
    101                                    (MASK_BITS_SHIFT_SEXT(op, 8, 15) << 16))
    102/* BIT Format */
    103#define MASK_OP_BIT_D(op)      MASK_BITS_SHIFT(op, 28, 31)
    104#define MASK_OP_BIT_POS2(op)   MASK_BITS_SHIFT(op, 23, 27)
    105#define MASK_OP_BIT_OP2(op)    MASK_BITS_SHIFT(op, 21, 22)
    106#define MASK_OP_BIT_POS1(op)   MASK_BITS_SHIFT(op, 16, 20)
    107#define MASK_OP_BIT_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
    108#define MASK_OP_BIT_S1(op)     MASK_BITS_SHIFT(op, 8, 11)
    109
    110/* BO Format */
    111#define MASK_OP_BO_OFF10(op)   (MASK_BITS_SHIFT(op, 16, 21) + \
    112                               (MASK_BITS_SHIFT(op, 28, 31) << 6))
    113#define MASK_OP_BO_OFF10_SEXT(op)   (MASK_BITS_SHIFT(op, 16, 21) + \
    114                                    (MASK_BITS_SHIFT_SEXT(op, 28, 31) << 6))
    115#define MASK_OP_BO_OP2(op)     MASK_BITS_SHIFT(op, 22, 27)
    116#define MASK_OP_BO_S2(op)      MASK_BITS_SHIFT(op, 12, 15)
    117#define MASK_OP_BO_S1D(op)     MASK_BITS_SHIFT(op, 8, 11)
    118
    119/* BOL Format */
    120#define MASK_OP_BOL_OFF16(op)  ((MASK_BITS_SHIFT(op, 16, 21) +        \
    121                               (MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
    122                               (MASK_BITS_SHIFT(op, 22, 27) << 10))
    123#define MASK_OP_BOL_OFF16_SEXT(op)  ((MASK_BITS_SHIFT(op, 16, 21) +        \
    124                                    (MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
    125                                    (MASK_BITS_SHIFT_SEXT(op, 22, 27) << 10))
    126#define MASK_OP_BOL_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
    127#define MASK_OP_BOL_S1D(op)    MASK_BITS_SHIFT(op, 8, 11)
    128
    129/* BRC Format */
    130#define MASK_OP_BRC_OP2(op)    MASK_BITS_SHIFT(op, 31, 31)
    131#define MASK_OP_BRC_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
    132#define MASK_OP_BRC_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30)
    133#define MASK_OP_BRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
    134#define MASK_OP_BRC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
    135#define MASK_OP_BRC_S1(op)     MASK_BITS_SHIFT(op, 8, 11)
    136
    137/* BRN Format */
    138#define MASK_OP_BRN_OP2(op)    MASK_BITS_SHIFT(op, 31, 31)
    139#define MASK_OP_BRN_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
    140#define MASK_OP_BRN_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30)
    141#define MASK_OP_BRN_N(op)      (MASK_BITS_SHIFT(op, 12, 15) + \
    142                               (MASK_BITS_SHIFT(op, 7, 7) << 4))
    143#define MASK_OP_BRN_S1(op)     MASK_BITS_SHIFT(op, 8, 11)
    144/* BRR Format */
    145#define MASK_OP_BRR_OP2(op)    MASK_BITS_SHIFT(op, 31, 31)
    146#define MASK_OP_BRR_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
    147#define MASK_OP_BRR_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30)
    148#define MASK_OP_BRR_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
    149#define MASK_OP_BRR_S1(op)     MASK_BITS_SHIFT(op, 8, 11)
    150
    151/* META MASK for similar instr Formats */
    152#define MASK_OP_META_D(op)     MASK_BITS_SHIFT(op, 28, 31)
    153#define MASK_OP_META_S1(op)    MASK_BITS_SHIFT(op, 8, 11)
    154
    155/* RC Format */
    156#define MASK_OP_RC_D(op)       MASK_OP_META_D(op)
    157#define MASK_OP_RC_OP2(op)     MASK_BITS_SHIFT(op, 21, 27)
    158#define MASK_OP_RC_CONST9(op)  MASK_BITS_SHIFT(op, 12, 20)
    159#define MASK_OP_RC_CONST9_SEXT(op)  MASK_BITS_SHIFT_SEXT(op, 12, 20)
    160#define MASK_OP_RC_S1(op)      MASK_OP_META_S1(op)
    161
    162/* RCPW Format */
    163
    164#define MASK_OP_RCPW_D(op)      MASK_OP_META_D(op)
    165#define MASK_OP_RCPW_POS(op)    MASK_BITS_SHIFT(op, 23, 27)
    166#define MASK_OP_RCPW_OP2(op)    MASK_BITS_SHIFT(op, 21, 22)
    167#define MASK_OP_RCPW_WIDTH(op)  MASK_BITS_SHIFT(op, 16, 20)
    168#define MASK_OP_RCPW_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
    169#define MASK_OP_RCPW_S1(op)     MASK_OP_META_S1(op)
    170
    171/* RCR Format */
    172
    173#define MASK_OP_RCR_D(op)      MASK_OP_META_D(op)
    174#define MASK_OP_RCR_S3(op)     MASK_BITS_SHIFT(op, 24, 27)
    175#define MASK_OP_RCR_OP2(op)    MASK_BITS_SHIFT(op, 21, 23)
    176#define MASK_OP_RCR_CONST9(op) MASK_BITS_SHIFT(op, 12, 20)
    177#define MASK_OP_RCR_CONST9_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 20)
    178#define MASK_OP_RCR_S1(op)     MASK_OP_META_S1(op)
    179
    180/* RCRR Format */
    181
    182#define MASK_OP_RCRR_D(op)      MASK_OP_META_D(op)
    183#define MASK_OP_RCRR_S3(op)     MASK_BITS_SHIFT(op, 24, 27)
    184#define MASK_OP_RCRR_OP2(op)    MASK_BITS_SHIFT(op, 21, 23)
    185#define MASK_OP_RCRR_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
    186#define MASK_OP_RCRR_S1(op)     MASK_OP_META_S1(op)
    187
    188/* RCRW Format */
    189
    190#define MASK_OP_RCRW_D(op)      MASK_OP_META_D(op)
    191#define MASK_OP_RCRW_S3(op)     MASK_BITS_SHIFT(op, 24, 27)
    192#define MASK_OP_RCRW_OP2(op)    MASK_BITS_SHIFT(op, 21, 23)
    193#define MASK_OP_RCRW_WIDTH(op)  MASK_BITS_SHIFT(op, 16, 20)
    194#define MASK_OP_RCRW_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
    195#define MASK_OP_RCRW_S1(op)     MASK_OP_META_S1(op)
    196
    197/* RLC Format */
    198
    199#define MASK_OP_RLC_D(op)       MASK_OP_META_D(op)
    200#define MASK_OP_RLC_CONST16(op) MASK_BITS_SHIFT(op, 12, 27)
    201#define MASK_OP_RLC_CONST16_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 27)
    202#define MASK_OP_RLC_S1(op)      MASK_OP_META_S1(op)
    203
    204/* RR  Format */
    205#define MASK_OP_RR_D(op)        MASK_OP_META_D(op)
    206#define MASK_OP_RR_OP2(op)      MASK_BITS_SHIFT(op, 20, 27)
    207#define MASK_OP_RR_N(op)        MASK_BITS_SHIFT(op, 16, 17)
    208#define MASK_OP_RR_S2(op)       MASK_BITS_SHIFT(op, 12, 15)
    209#define MASK_OP_RR_S1(op)       MASK_OP_META_S1(op)
    210
    211/* RR1  Format */
    212#define MASK_OP_RR1_D(op)       MASK_OP_META_D(op)
    213#define MASK_OP_RR1_OP2(op)     MASK_BITS_SHIFT(op, 18, 27)
    214#define MASK_OP_RR1_N(op)       MASK_BITS_SHIFT(op, 16, 17)
    215#define MASK_OP_RR1_S2(op)      MASK_BITS_SHIFT(op, 12, 15)
    216#define MASK_OP_RR1_S1(op)      MASK_OP_META_S1(op)
    217
    218/* RR2  Format */
    219#define MASK_OP_RR2_D(op)       MASK_OP_META_D(op)
    220#define MASK_OP_RR2_OP2(op)     MASK_BITS_SHIFT(op, 16, 27)
    221#define MASK_OP_RR2_S2(op)      MASK_BITS_SHIFT(op, 12, 15)
    222#define MASK_OP_RR2_S1(op)      MASK_OP_META_S1(op)
    223
    224/* RRPW  Format */
    225#define MASK_OP_RRPW_D(op)      MASK_OP_META_D(op)
    226#define MASK_OP_RRPW_POS(op)    MASK_BITS_SHIFT(op, 23, 27)
    227#define MASK_OP_RRPW_OP2(op)    MASK_BITS_SHIFT(op, 21, 22)
    228#define MASK_OP_RRPW_WIDTH(op)  MASK_BITS_SHIFT(op, 16, 20)
    229#define MASK_OP_RRPW_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
    230#define MASK_OP_RRPW_S1(op)     MASK_OP_META_S1(op)
    231
    232/* RRR  Format */
    233#define MASK_OP_RRR_D(op)       MASK_OP_META_D(op)
    234#define MASK_OP_RRR_S3(op)      MASK_BITS_SHIFT(op, 24, 27)
    235#define MASK_OP_RRR_OP2(op)     MASK_BITS_SHIFT(op, 20, 23)
    236#define MASK_OP_RRR_N(op)       MASK_BITS_SHIFT(op, 16, 17)
    237#define MASK_OP_RRR_S2(op)      MASK_BITS_SHIFT(op, 12, 15)
    238#define MASK_OP_RRR_S1(op)      MASK_OP_META_S1(op)
    239
    240/* RRR1  Format */
    241#define MASK_OP_RRR1_D(op)      MASK_OP_META_D(op)
    242#define MASK_OP_RRR1_S3(op)     MASK_BITS_SHIFT(op, 24, 27)
    243#define MASK_OP_RRR1_OP2(op)    MASK_BITS_SHIFT(op, 18, 23)
    244#define MASK_OP_RRR1_N(op)      MASK_BITS_SHIFT(op, 16, 17)
    245#define MASK_OP_RRR1_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
    246#define MASK_OP_RRR1_S1(op)     MASK_OP_META_S1(op)
    247
    248/* RRR2  Format */
    249#define MASK_OP_RRR2_D(op)      MASK_OP_META_D(op)
    250#define MASK_OP_RRR2_S3(op)     MASK_BITS_SHIFT(op, 24, 27)
    251#define MASK_OP_RRR2_OP2(op)    MASK_BITS_SHIFT(op, 16, 23)
    252#define MASK_OP_RRR2_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
    253#define MASK_OP_RRR2_S1(op)     MASK_OP_META_S1(op)
    254
    255/* RRRR  Format */
    256#define MASK_OP_RRRR_D(op)      MASK_OP_META_D(op)
    257#define MASK_OP_RRRR_S3(op)     MASK_BITS_SHIFT(op, 24, 27)
    258#define MASK_OP_RRRR_OP2(op)    MASK_BITS_SHIFT(op, 21, 23)
    259#define MASK_OP_RRRR_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
    260#define MASK_OP_RRRR_S1(op)     MASK_OP_META_S1(op)
    261
    262/* RRRW  Format */
    263#define MASK_OP_RRRW_D(op)      MASK_OP_META_D(op)
    264#define MASK_OP_RRRW_S3(op)     MASK_BITS_SHIFT(op, 24, 27)
    265#define MASK_OP_RRRW_OP2(op)    MASK_BITS_SHIFT(op, 21, 23)
    266#define MASK_OP_RRRW_WIDTH(op)  MASK_BITS_SHIFT(op, 16, 20)
    267#define MASK_OP_RRRW_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
    268#define MASK_OP_RRRW_S1(op)     MASK_OP_META_S1(op)
    269
    270/* SYS Format */
    271#define MASK_OP_SYS_OP2(op)     MASK_BITS_SHIFT(op, 22, 27)
    272#define MASK_OP_SYS_S1D(op)     MASK_OP_META_S1(op)
    273
    274
    275
    276/*
    277 * Tricore Opcodes Enums
    278 *
    279 * Format: OPC(1|2|M)_InstrLen_Name
    280 * OPC1 = only op1 field is used
    281 * OPC2 = op1 and op2 field used part of OPCM
    282 * OPCM = op1 field used to group Instr
    283 * InstrLen = 16|32
    284 * Name = Name of Instr
    285 */
    286
    287/* 16-Bit */
    288enum {
    289
    290    OPCM_16_SR_SYSTEM                                = 0x00,
    291    OPCM_16_SR_ACCU                                  = 0x32,
    292
    293    OPC1_16_SRC_ADD                                  = 0xc2,
    294    OPC1_16_SRC_ADD_A15                              = 0x92,
    295    OPC1_16_SRC_ADD_15A                              = 0x9a,
    296    OPC1_16_SRR_ADD                                  = 0x42,
    297    OPC1_16_SRR_ADD_A15                              = 0x12,
    298    OPC1_16_SRR_ADD_15A                              = 0x1a,
    299    OPC1_16_SRC_ADD_A                                = 0xb0,
    300    OPC1_16_SRR_ADD_A                                = 0x30,
    301    OPC1_16_SRR_ADDS                                 = 0x22,
    302    OPC1_16_SRRS_ADDSC_A                             = 0x10,
    303    OPC1_16_SC_AND                                   = 0x16,
    304    OPC1_16_SRR_AND                                  = 0x26,
    305    OPC1_16_SC_BISR                                  = 0xe0,
    306    OPC1_16_SRC_CADD                                 = 0x8a,
    307    OPC1_16_SRC_CADDN                                = 0xca,
    308    OPC1_16_SB_CALL                                  = 0x5c,
    309    OPC1_16_SRC_CMOV                                 = 0xaa,
    310    OPC1_16_SRR_CMOV                                 = 0x2a,
    311    OPC1_16_SRC_CMOVN                                = 0xea,
    312    OPC1_16_SRR_CMOVN                                = 0x6a,
    313    OPC1_16_SRC_EQ                                   = 0xba,
    314    OPC1_16_SRR_EQ                                   = 0x3a,
    315    OPC1_16_SB_J                                     = 0x3c,
    316    OPC1_16_SBC_JEQ                                  = 0x1e,
    317    OPC1_16_SBC_JEQ2                                 = 0x9e,
    318    OPC1_16_SBR_JEQ                                  = 0x3e,
    319    OPC1_16_SBR_JEQ2                                 = 0xbe,
    320    OPC1_16_SBR_JGEZ                                 = 0xce,
    321    OPC1_16_SBR_JGTZ                                 = 0x4e,
    322    OPC1_16_SR_JI                                    = 0xdc,
    323    OPC1_16_SBR_JLEZ                                 = 0x8e,
    324    OPC1_16_SBR_JLTZ                                 = 0x0e,
    325    OPC1_16_SBC_JNE                                  = 0x5e,
    326    OPC1_16_SBC_JNE2                                 = 0xde,
    327    OPC1_16_SBR_JNE                                  = 0x7e,
    328    OPC1_16_SBR_JNE2                                 = 0xfe,
    329    OPC1_16_SB_JNZ                                   = 0xee,
    330    OPC1_16_SBR_JNZ                                  = 0xf6,
    331    OPC1_16_SBR_JNZ_A                                = 0x7c,
    332    OPC1_16_SBRN_JNZ_T                               = 0xae,
    333    OPC1_16_SB_JZ                                    = 0x6e,
    334    OPC1_16_SBR_JZ                                   = 0x76,
    335    OPC1_16_SBR_JZ_A                                 = 0xbc,
    336    OPC1_16_SBRN_JZ_T                                = 0x2e,
    337    OPC1_16_SC_LD_A                                  = 0xd8,
    338    OPC1_16_SLR_LD_A                                 = 0xd4,
    339    OPC1_16_SLR_LD_A_POSTINC                         = 0xc4,
    340    OPC1_16_SLRO_LD_A                                = 0xc8,
    341    OPC1_16_SRO_LD_A                                 = 0xcc,
    342    OPC1_16_SLR_LD_BU                                = 0x14,
    343    OPC1_16_SLR_LD_BU_POSTINC                        = 0x04,
    344    OPC1_16_SLRO_LD_BU                               = 0x08,
    345    OPC1_16_SRO_LD_BU                                = 0x0c,
    346    OPC1_16_SLR_LD_H                                 = 0x94,
    347    OPC1_16_SLR_LD_H_POSTINC                         = 0x84,
    348    OPC1_16_SLRO_LD_H                                = 0x88,
    349    OPC1_16_SRO_LD_H                                 = 0x8c,
    350    OPC1_16_SC_LD_W                                  = 0x58,
    351    OPC1_16_SLR_LD_W                                 = 0x54,
    352    OPC1_16_SLR_LD_W_POSTINC                         = 0x44,
    353    OPC1_16_SLRO_LD_W                                = 0x48,
    354    OPC1_16_SRO_LD_W                                 = 0x4c,
    355    OPC1_16_SBR_LOOP                                 = 0xfc,
    356    OPC1_16_SRC_LT                                   = 0xfa,
    357    OPC1_16_SRR_LT                                   = 0x7a,
    358    OPC1_16_SC_MOV                                   = 0xda,
    359    OPC1_16_SRC_MOV                                  = 0x82,
    360    OPC1_16_SRR_MOV                                  = 0x02,
    361    OPC1_16_SRC_MOV_E                                = 0xd2,/* 1.6 only */
    362    OPC1_16_SRC_MOV_A                                = 0xa0,
    363    OPC1_16_SRR_MOV_A                                = 0x60,
    364    OPC1_16_SRR_MOV_AA                               = 0x40,
    365    OPC1_16_SRR_MOV_D                                = 0x80,
    366    OPC1_16_SRR_MUL                                  = 0xe2,
    367    OPC1_16_SR_NOT                                   = 0x46,
    368    OPC1_16_SC_OR                                    = 0x96,
    369    OPC1_16_SRR_OR                                   = 0xa6,
    370    OPC1_16_SRC_SH                                   = 0x06,
    371    OPC1_16_SRC_SHA                                  = 0x86,
    372    OPC1_16_SC_ST_A                                  = 0xf8,
    373    OPC1_16_SRO_ST_A                                 = 0xec,
    374    OPC1_16_SSR_ST_A                                 = 0xf4,
    375    OPC1_16_SSR_ST_A_POSTINC                         = 0xe4,
    376    OPC1_16_SSRO_ST_A                                = 0xe8,
    377    OPC1_16_SRO_ST_B                                 = 0x2c,
    378    OPC1_16_SSR_ST_B                                 = 0x34,
    379    OPC1_16_SSR_ST_B_POSTINC                         = 0x24,
    380    OPC1_16_SSRO_ST_B                                = 0x28,
    381    OPC1_16_SRO_ST_H                                 = 0xac,
    382    OPC1_16_SSR_ST_H                                 = 0xb4,
    383    OPC1_16_SSR_ST_H_POSTINC                         = 0xa4,
    384    OPC1_16_SSRO_ST_H                                = 0xa8,
    385    OPC1_16_SC_ST_W                                  = 0x78,
    386    OPC1_16_SRO_ST_W                                 = 0x6c,
    387    OPC1_16_SSR_ST_W                                 = 0x74,
    388    OPC1_16_SSR_ST_W_POSTINC                         = 0x64,
    389    OPC1_16_SSRO_ST_W                                = 0x68,
    390    OPC1_16_SRR_SUB                                  = 0xa2,
    391    OPC1_16_SRR_SUB_A15B                             = 0x52,
    392    OPC1_16_SRR_SUB_15AB                             = 0x5a,
    393    OPC1_16_SC_SUB_A                                 = 0x20,
    394    OPC1_16_SRR_SUBS                                 = 0x62,
    395    OPC1_16_SRR_XOR                                  = 0xc6,
    396
    397};
    398
    399/*
    400 * SR Format
    401 */
    402/* OPCM_16_SR_SYSTEM                                 */
    403enum {
    404
    405    OPC2_16_SR_NOP                                   = 0x00,
    406    OPC2_16_SR_RET                                   = 0x09,
    407    OPC2_16_SR_RFE                                   = 0x08,
    408    OPC2_16_SR_DEBUG                                 = 0x0a,
    409    OPC2_16_SR_FRET                                  = 0x07,
    410};
    411/* OPCM_16_SR_ACCU                                   */
    412enum {
    413    OPC2_16_SR_RSUB                                  = 0x05,
    414    OPC2_16_SR_SAT_B                                 = 0x00,
    415    OPC2_16_SR_SAT_BU                                = 0x01,
    416    OPC2_16_SR_SAT_H                                 = 0x02,
    417    OPC2_16_SR_SAT_HU                                = 0x03,
    418
    419};
    420
    421/* 32-Bit */
    422
    423enum {
    424/* ABS Format 1, M */
    425    OPCM_32_ABS_LDW                                  = 0x85,
    426    OPCM_32_ABS_LDB                                  = 0x05,
    427    OPCM_32_ABS_LDMST_SWAP                           = 0xe5,
    428    OPCM_32_ABS_LDST_CONTEXT                         = 0x15,
    429    OPCM_32_ABS_STORE                                = 0xa5,
    430    OPCM_32_ABS_STOREB_H                             = 0x25,
    431    OPC1_32_ABS_STOREQ                               = 0x65,
    432    OPC1_32_ABS_LD_Q                                 = 0x45,
    433    OPC1_32_ABS_LEA                                  = 0xc5,
    434/* ABSB Format */
    435    OPC1_32_ABSB_ST_T                                = 0xd5,
    436/* B Format */
    437    OPC1_32_B_CALL                                   = 0x6d,
    438    OPC1_32_B_CALLA                                  = 0xed,
    439    OPC1_32_B_FCALL                                  = 0x61,
    440    OPC1_32_B_FCALLA                                 = 0xe1,
    441    OPC1_32_B_J                                      = 0x1d,
    442    OPC1_32_B_JA                                     = 0x9d,
    443    OPC1_32_B_JL                                     = 0x5d,
    444    OPC1_32_B_JLA                                    = 0xdd,
    445/* Bit Format */
    446    OPCM_32_BIT_ANDACC                               = 0x47,
    447    OPCM_32_BIT_LOGICAL_T1                           = 0x87,
    448    OPCM_32_BIT_INSERT                               = 0x67,
    449    OPCM_32_BIT_LOGICAL_T2                           = 0x07,
    450    OPCM_32_BIT_ORAND                                = 0xc7,
    451    OPCM_32_BIT_SH_LOGIC1                            = 0x27,
    452    OPCM_32_BIT_SH_LOGIC2                            = 0xa7,
    453/* BO Format */
    454    OPCM_32_BO_ADDRMODE_POST_PRE_BASE                = 0x89,
    455    OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR          = 0xa9,
    456    OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE             = 0x09,
    457    OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR       = 0x29,
    458    OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE          = 0x49,
    459    OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR    = 0x69,
    460/* BOL Format */
    461    OPC1_32_BOL_LD_A_LONGOFF                         = 0x99,
    462    OPC1_32_BOL_LD_W_LONGOFF                         = 0x19,
    463    OPC1_32_BOL_LEA_LONGOFF                          = 0xd9,
    464    OPC1_32_BOL_ST_W_LONGOFF                         = 0x59,
    465    OPC1_32_BOL_ST_A_LONGOFF                         = 0xb5, /* 1.6 only */
    466    OPC1_32_BOL_LD_B_LONGOFF                         = 0x79, /* 1.6 only */
    467    OPC1_32_BOL_LD_BU_LONGOFF                        = 0x39, /* 1.6 only */
    468    OPC1_32_BOL_LD_H_LONGOFF                         = 0xc9, /* 1.6 only */
    469    OPC1_32_BOL_LD_HU_LONGOFF                        = 0xb9, /* 1.6 only */
    470    OPC1_32_BOL_ST_B_LONGOFF                         = 0xe9, /* 1.6 only */
    471    OPC1_32_BOL_ST_H_LONGOFF                         = 0xf9, /* 1.6 only */
    472/* BRC Format */
    473    OPCM_32_BRC_EQ_NEQ                               = 0xdf,
    474    OPCM_32_BRC_GE                                   = 0xff,
    475    OPCM_32_BRC_JLT                                  = 0xbf,
    476    OPCM_32_BRC_JNE                                  = 0x9f,
    477/* BRN Format */
    478    OPCM_32_BRN_JTT                                  = 0x6f,
    479/* BRR Format */
    480    OPCM_32_BRR_EQ_NEQ                               = 0x5f,
    481    OPCM_32_BRR_ADDR_EQ_NEQ                          = 0x7d,
    482    OPCM_32_BRR_GE                                   = 0x7f,
    483    OPCM_32_BRR_JLT                                  = 0x3f,
    484    OPCM_32_BRR_JNE                                  = 0x1f,
    485    OPCM_32_BRR_JNZ                                  = 0xbd,
    486    OPCM_32_BRR_LOOP                                 = 0xfd,
    487/* RC Format */
    488    OPCM_32_RC_LOGICAL_SHIFT                         = 0x8f,
    489    OPCM_32_RC_ACCUMULATOR                           = 0x8b,
    490    OPCM_32_RC_SERVICEROUTINE                        = 0xad,
    491    OPCM_32_RC_MUL                                   = 0x53,
    492/* RCPW Format */
    493    OPCM_32_RCPW_MASK_INSERT                         = 0xb7,
    494/* RCR Format */
    495    OPCM_32_RCR_COND_SELECT                          = 0xab,
    496    OPCM_32_RCR_MADD                                 = 0x13,
    497    OPCM_32_RCR_MSUB                                 = 0x33,
    498/* RCRR Format */
    499    OPC1_32_RCRR_INSERT                              = 0x97,
    500/* RCRW Format */
    501    OPCM_32_RCRW_MASK_INSERT                         = 0xd7,
    502/* RLC Format */
    503    OPC1_32_RLC_ADDI                                 = 0x1b,
    504    OPC1_32_RLC_ADDIH                                = 0x9b,
    505    OPC1_32_RLC_ADDIH_A                              = 0x11,
    506    OPC1_32_RLC_MFCR                                 = 0x4d,
    507    OPC1_32_RLC_MOV                                  = 0x3b,
    508    OPC1_32_RLC_MOV_64                               = 0xfb, /* 1.6 only */
    509    OPC1_32_RLC_MOV_U                                = 0xbb,
    510    OPC1_32_RLC_MOV_H                                = 0x7b,
    511    OPC1_32_RLC_MOVH_A                               = 0x91,
    512    OPC1_32_RLC_MTCR                                 = 0xcd,
    513/* RR Format */
    514    OPCM_32_RR_LOGICAL_SHIFT                         = 0x0f,
    515    OPCM_32_RR_ACCUMULATOR                           = 0x0b,
    516    OPCM_32_RR_ADDRESS                               = 0x01,
    517    OPCM_32_RR_DIVIDE                                = 0x4b,
    518    OPCM_32_RR_IDIRECT                               = 0x2d,
    519/* RR1 Format */
    520    OPCM_32_RR1_MUL                                  = 0xb3,
    521    OPCM_32_RR1_MULQ                                 = 0x93,
    522/* RR2 Format */
    523    OPCM_32_RR2_MUL                                  = 0x73,
    524/* RRPW Format */
    525    OPCM_32_RRPW_EXTRACT_INSERT                      = 0x37,
    526    OPC1_32_RRPW_DEXTR                               = 0x77,
    527/* RRR Format */
    528    OPCM_32_RRR_COND_SELECT                          = 0x2b,
    529    OPCM_32_RRR_DIVIDE                               = 0x6b,
    530/* RRR1 Format */
    531    OPCM_32_RRR1_MADD                                = 0x83,
    532    OPCM_32_RRR1_MADDQ_H                             = 0x43,
    533    OPCM_32_RRR1_MADDSU_H                            = 0xc3,
    534    OPCM_32_RRR1_MSUB_H                              = 0xa3,
    535    OPCM_32_RRR1_MSUB_Q                              = 0x63,
    536    OPCM_32_RRR1_MSUBAD_H                            = 0xe3,
    537/* RRR2 Format */
    538    OPCM_32_RRR2_MADD                                = 0x03,
    539    OPCM_32_RRR2_MSUB                                = 0x23,
    540/* RRRR Format */
    541    OPCM_32_RRRR_EXTRACT_INSERT                      = 0x17,
    542/* RRRW Format */
    543    OPCM_32_RRRW_EXTRACT_INSERT                      = 0x57,
    544/* SYS Format */
    545    OPCM_32_SYS_INTERRUPTS                           = 0x0d,
    546    OPC1_32_SYS_RSTV                                 = 0x2f,
    547};
    548
    549
    550
    551/*
    552 * ABS Format
    553 */
    554
    555/* OPCM_32_ABS_LDW  */
    556enum {
    557
    558    OPC2_32_ABS_LD_A                             = 0x02,
    559    OPC2_32_ABS_LD_D                             = 0x01,
    560    OPC2_32_ABS_LD_DA                            = 0x03,
    561    OPC2_32_ABS_LD_W                             = 0x00,
    562};
    563
    564/* OPCM_32_ABS_LDB */
    565enum {
    566    OPC2_32_ABS_LD_B                             = 0x00,
    567    OPC2_32_ABS_LD_BU                            = 0x01,
    568    OPC2_32_ABS_LD_H                             = 0x02,
    569    OPC2_32_ABS_LD_HU                            = 0x03,
    570};
    571/* OPCM_32_ABS_LDMST_SWAP       */
    572enum {
    573    OPC2_32_ABS_LDMST                            = 0x01,
    574    OPC2_32_ABS_SWAP_W                           = 0x00,
    575};
    576/* OPCM_32_ABS_LDST_CONTEXT     */
    577enum {
    578    OPC2_32_ABS_LDLCX                            = 0x02,
    579    OPC2_32_ABS_LDUCX                            = 0x03,
    580    OPC2_32_ABS_STLCX                            = 0x00,
    581    OPC2_32_ABS_STUCX                            = 0x01,
    582};
    583/* OPCM_32_ABS_STORE            */
    584enum {
    585    OPC2_32_ABS_ST_A                             = 0x02,
    586    OPC2_32_ABS_ST_D                             = 0x01,
    587    OPC2_32_ABS_ST_DA                            = 0x03,
    588    OPC2_32_ABS_ST_W                             = 0x00,
    589};
    590/* OPCM_32_ABS_STOREB_H */
    591enum {
    592    OPC2_32_ABS_ST_B                             = 0x00,
    593    OPC2_32_ABS_ST_H                             = 0x02,
    594};
    595/*
    596 * Bit Format
    597 */
    598/* OPCM_32_BIT_ANDACC              */
    599enum {
    600    OPC2_32_BIT_AND_AND_T                        = 0x00,
    601    OPC2_32_BIT_AND_ANDN_T                       = 0x03,
    602    OPC2_32_BIT_AND_NOR_T                        = 0x02,
    603    OPC2_32_BIT_AND_OR_T                         = 0x01,
    604};
    605/* OPCM_32_BIT_LOGICAL_T                       */
    606enum {
    607    OPC2_32_BIT_AND_T                            = 0x00,
    608    OPC2_32_BIT_ANDN_T                           = 0x03,
    609    OPC2_32_BIT_NOR_T                            = 0x02,
    610    OPC2_32_BIT_OR_T                             = 0x01,
    611};
    612/* OPCM_32_BIT_INSERT                   */
    613enum {
    614    OPC2_32_BIT_INS_T                            = 0x00,
    615    OPC2_32_BIT_INSN_T                           = 0x01,
    616};
    617/* OPCM_32_BIT_LOGICAL_T2              */
    618enum {
    619    OPC2_32_BIT_NAND_T                           = 0x00,
    620    OPC2_32_BIT_ORN_T                            = 0x01,
    621    OPC2_32_BIT_XNOR_T                           = 0x02,
    622    OPC2_32_BIT_XOR_T                            = 0x03,
    623};
    624/* OPCM_32_BIT_ORAND                    */
    625enum {
    626    OPC2_32_BIT_OR_AND_T                         = 0x00,
    627    OPC2_32_BIT_OR_ANDN_T                        = 0x03,
    628    OPC2_32_BIT_OR_NOR_T                         = 0x02,
    629    OPC2_32_BIT_OR_OR_T                          = 0x01,
    630};
    631/*OPCM_32_BIT_SH_LOGIC1                 */
    632enum {
    633    OPC2_32_BIT_SH_AND_T                         = 0x00,
    634    OPC2_32_BIT_SH_ANDN_T                        = 0x03,
    635    OPC2_32_BIT_SH_NOR_T                         = 0x02,
    636    OPC2_32_BIT_SH_OR_T                          = 0x01,
    637};
    638/* OPCM_32_BIT_SH_LOGIC2              */
    639enum {
    640    OPC2_32_BIT_SH_NAND_T                        = 0x00,
    641    OPC2_32_BIT_SH_ORN_T                         = 0x01,
    642    OPC2_32_BIT_SH_XNOR_T                        = 0x02,
    643    OPC2_32_BIT_SH_XOR_T                         = 0x03,
    644};
    645/*
    646 * BO Format
    647 */
    648/* OPCM_32_BO_ADDRMODE_POST_PRE_BASE     */
    649enum {
    650    OPC2_32_BO_CACHEA_I_SHORTOFF                 = 0x2e,
    651    OPC2_32_BO_CACHEA_I_POSTINC                  = 0x0e,
    652    OPC2_32_BO_CACHEA_I_PREINC                   = 0x1e,
    653    OPC2_32_BO_CACHEA_W_SHORTOFF                 = 0x2c,
    654    OPC2_32_BO_CACHEA_W_POSTINC                  = 0x0c,
    655    OPC2_32_BO_CACHEA_W_PREINC                   = 0x1c,
    656    OPC2_32_BO_CACHEA_WI_SHORTOFF                = 0x2d,
    657    OPC2_32_BO_CACHEA_WI_POSTINC                 = 0x0d,
    658    OPC2_32_BO_CACHEA_WI_PREINC                  = 0x1d,
    659    /* 1.3.1 only */
    660    OPC2_32_BO_CACHEI_W_SHORTOFF                 = 0x2b,
    661    OPC2_32_BO_CACHEI_W_POSTINC                  = 0x0b,
    662    OPC2_32_BO_CACHEI_W_PREINC                   = 0x1b,
    663    OPC2_32_BO_CACHEI_WI_SHORTOFF                = 0x2f,
    664    OPC2_32_BO_CACHEI_WI_POSTINC                 = 0x0f,
    665    OPC2_32_BO_CACHEI_WI_PREINC                  = 0x1f,
    666    /* end 1.3.1 only */
    667    OPC2_32_BO_ST_A_SHORTOFF                     = 0x26,
    668    OPC2_32_BO_ST_A_POSTINC                      = 0x06,
    669    OPC2_32_BO_ST_A_PREINC                       = 0x16,
    670    OPC2_32_BO_ST_B_SHORTOFF                     = 0x20,
    671    OPC2_32_BO_ST_B_POSTINC                      = 0x00,
    672    OPC2_32_BO_ST_B_PREINC                       = 0x10,
    673    OPC2_32_BO_ST_D_SHORTOFF                     = 0x25,
    674    OPC2_32_BO_ST_D_POSTINC                      = 0x05,
    675    OPC2_32_BO_ST_D_PREINC                       = 0x15,
    676    OPC2_32_BO_ST_DA_SHORTOFF                    = 0x27,
    677    OPC2_32_BO_ST_DA_POSTINC                     = 0x07,
    678    OPC2_32_BO_ST_DA_PREINC                      = 0x17,
    679    OPC2_32_BO_ST_H_SHORTOFF                     = 0x22,
    680    OPC2_32_BO_ST_H_POSTINC                      = 0x02,
    681    OPC2_32_BO_ST_H_PREINC                       = 0x12,
    682    OPC2_32_BO_ST_Q_SHORTOFF                     = 0x28,
    683    OPC2_32_BO_ST_Q_POSTINC                      = 0x08,
    684    OPC2_32_BO_ST_Q_PREINC                       = 0x18,
    685    OPC2_32_BO_ST_W_SHORTOFF                     = 0x24,
    686    OPC2_32_BO_ST_W_POSTINC                      = 0x04,
    687    OPC2_32_BO_ST_W_PREINC                       = 0x14,
    688};
    689/* OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR   */
    690enum {
    691    OPC2_32_BO_CACHEA_I_BR                       = 0x0e,
    692    OPC2_32_BO_CACHEA_I_CIRC                     = 0x1e,
    693    OPC2_32_BO_CACHEA_W_BR                       = 0x0c,
    694    OPC2_32_BO_CACHEA_W_CIRC                     = 0x1c,
    695    OPC2_32_BO_CACHEA_WI_BR                      = 0x0d,
    696    OPC2_32_BO_CACHEA_WI_CIRC                    = 0x1d,
    697    OPC2_32_BO_ST_A_BR                           = 0x06,
    698    OPC2_32_BO_ST_A_CIRC                         = 0x16,
    699    OPC2_32_BO_ST_B_BR                           = 0x00,
    700    OPC2_32_BO_ST_B_CIRC                         = 0x10,
    701    OPC2_32_BO_ST_D_BR                           = 0x05,
    702    OPC2_32_BO_ST_D_CIRC                         = 0x15,
    703    OPC2_32_BO_ST_DA_BR                          = 0x07,
    704    OPC2_32_BO_ST_DA_CIRC                        = 0x17,
    705    OPC2_32_BO_ST_H_BR                           = 0x02,
    706    OPC2_32_BO_ST_H_CIRC                         = 0x12,
    707    OPC2_32_BO_ST_Q_BR                           = 0x08,
    708    OPC2_32_BO_ST_Q_CIRC                         = 0x18,
    709    OPC2_32_BO_ST_W_BR                           = 0x04,
    710    OPC2_32_BO_ST_W_CIRC                         = 0x14,
    711};
    712/*    OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE   */
    713enum {
    714    OPC2_32_BO_LD_A_SHORTOFF                     = 0x26,
    715    OPC2_32_BO_LD_A_POSTINC                      = 0x06,
    716    OPC2_32_BO_LD_A_PREINC                       = 0x16,
    717    OPC2_32_BO_LD_B_SHORTOFF                     = 0x20,
    718    OPC2_32_BO_LD_B_POSTINC                      = 0x00,
    719    OPC2_32_BO_LD_B_PREINC                       = 0x10,
    720    OPC2_32_BO_LD_BU_SHORTOFF                    = 0x21,
    721    OPC2_32_BO_LD_BU_POSTINC                     = 0x01,
    722    OPC2_32_BO_LD_BU_PREINC                      = 0x11,
    723    OPC2_32_BO_LD_D_SHORTOFF                     = 0x25,
    724    OPC2_32_BO_LD_D_POSTINC                      = 0x05,
    725    OPC2_32_BO_LD_D_PREINC                       = 0x15,
    726    OPC2_32_BO_LD_DA_SHORTOFF                    = 0x27,
    727    OPC2_32_BO_LD_DA_POSTINC                     = 0x07,
    728    OPC2_32_BO_LD_DA_PREINC                      = 0x17,
    729    OPC2_32_BO_LD_H_SHORTOFF                     = 0x22,
    730    OPC2_32_BO_LD_H_POSTINC                      = 0x02,
    731    OPC2_32_BO_LD_H_PREINC                       = 0x12,
    732    OPC2_32_BO_LD_HU_SHORTOFF                    = 0x23,
    733    OPC2_32_BO_LD_HU_POSTINC                     = 0x03,
    734    OPC2_32_BO_LD_HU_PREINC                      = 0x13,
    735    OPC2_32_BO_LD_Q_SHORTOFF                     = 0x28,
    736    OPC2_32_BO_LD_Q_POSTINC                      = 0x08,
    737    OPC2_32_BO_LD_Q_PREINC                       = 0x18,
    738    OPC2_32_BO_LD_W_SHORTOFF                     = 0x24,
    739    OPC2_32_BO_LD_W_POSTINC                      = 0x04,
    740    OPC2_32_BO_LD_W_PREINC                       = 0x14,
    741};
    742/* OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR  */
    743enum {
    744    OPC2_32_BO_LD_A_BR                           = 0x06,
    745    OPC2_32_BO_LD_A_CIRC                         = 0x16,
    746    OPC2_32_BO_LD_B_BR                           = 0x00,
    747    OPC2_32_BO_LD_B_CIRC                         = 0x10,
    748    OPC2_32_BO_LD_BU_BR                          = 0x01,
    749    OPC2_32_BO_LD_BU_CIRC                        = 0x11,
    750    OPC2_32_BO_LD_D_BR                           = 0x05,
    751    OPC2_32_BO_LD_D_CIRC                         = 0x15,
    752    OPC2_32_BO_LD_DA_BR                          = 0x07,
    753    OPC2_32_BO_LD_DA_CIRC                        = 0x17,
    754    OPC2_32_BO_LD_H_BR                           = 0x02,
    755    OPC2_32_BO_LD_H_CIRC                         = 0x12,
    756    OPC2_32_BO_LD_HU_BR                          = 0x03,
    757    OPC2_32_BO_LD_HU_CIRC                        = 0x13,
    758    OPC2_32_BO_LD_Q_BR                           = 0x08,
    759    OPC2_32_BO_LD_Q_CIRC                         = 0x18,
    760    OPC2_32_BO_LD_W_BR                           = 0x04,
    761    OPC2_32_BO_LD_W_CIRC                         = 0x14,
    762};
    763/* OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE    */
    764enum {
    765    OPC2_32_BO_LDLCX_SHORTOFF                    = 0x24,
    766    OPC2_32_BO_LDMST_SHORTOFF                    = 0x21,
    767    OPC2_32_BO_LDMST_POSTINC                     = 0x01,
    768    OPC2_32_BO_LDMST_PREINC                      = 0x11,
    769    OPC2_32_BO_LDUCX_SHORTOFF                    = 0x25,
    770    OPC2_32_BO_LEA_SHORTOFF                      = 0x28,
    771    OPC2_32_BO_STLCX_SHORTOFF                    = 0x26,
    772    OPC2_32_BO_STUCX_SHORTOFF                    = 0x27,
    773    OPC2_32_BO_SWAP_W_SHORTOFF                   = 0x20,
    774    OPC2_32_BO_SWAP_W_POSTINC                    = 0x00,
    775    OPC2_32_BO_SWAP_W_PREINC                     = 0x10,
    776    OPC2_32_BO_CMPSWAP_W_SHORTOFF                = 0x23,
    777    OPC2_32_BO_CMPSWAP_W_POSTINC                 = 0x03,
    778    OPC2_32_BO_CMPSWAP_W_PREINC                  = 0x13,
    779    OPC2_32_BO_SWAPMSK_W_SHORTOFF                = 0x22,
    780    OPC2_32_BO_SWAPMSK_W_POSTINC                 = 0x02,
    781    OPC2_32_BO_SWAPMSK_W_PREINC                  = 0x12,
    782};
    783/*OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR  */
    784enum {
    785    OPC2_32_BO_LDMST_BR                          = 0x01,
    786    OPC2_32_BO_LDMST_CIRC                        = 0x11,
    787    OPC2_32_BO_SWAP_W_BR                         = 0x00,
    788    OPC2_32_BO_SWAP_W_CIRC                       = 0x10,
    789    OPC2_32_BO_CMPSWAP_W_BR                      = 0x03,
    790    OPC2_32_BO_CMPSWAP_W_CIRC                    = 0x13,
    791    OPC2_32_BO_SWAPMSK_W_BR                      = 0x02,
    792    OPC2_32_BO_SWAPMSK_W_CIRC                    = 0x12,
    793};
    794/*
    795 * BRC Format
    796 */
    797/*OPCM_32_BRC_EQ_NEQ                             */
    798enum {
    799    OPC2_32_BRC_JEQ                              = 0x00,
    800    OPC2_32_BRC_JNE                              = 0x01,
    801};
    802/* OPCM_32_BRC_GE                                   */
    803enum {
    804    OP2_32_BRC_JGE                               = 0x00,
    805    OPC_32_BRC_JGE_U                             = 0x01,
    806};
    807/* OPCM_32_BRC_JLT                                  */
    808enum {
    809    OPC2_32_BRC_JLT                              = 0x00,
    810    OPC2_32_BRC_JLT_U                            = 0x01,
    811};
    812/* OPCM_32_BRC_JNE                                  */
    813enum {
    814    OPC2_32_BRC_JNED                             = 0x01,
    815    OPC2_32_BRC_JNEI                             = 0x00,
    816};
    817/*
    818 * BRN Format
    819 */
    820/* OPCM_32_BRN_JTT                                  */
    821enum {
    822    OPC2_32_BRN_JNZ_T                            = 0x01,
    823    OPC2_32_BRN_JZ_T                             = 0x00,
    824};
    825/*
    826 * BRR Format
    827 */
    828/* OPCM_32_BRR_EQ_NEQ                               */
    829enum {
    830    OPC2_32_BRR_JEQ                              = 0x00,
    831    OPC2_32_BRR_JNE                              = 0x01,
    832};
    833/* OPCM_32_BRR_ADDR_EQ_NEQ                        */
    834enum {
    835    OPC2_32_BRR_JEQ_A                            = 0x00,
    836    OPC2_32_BRR_JNE_A                            = 0x01,
    837};
    838/*OPCM_32_BRR_GE                                   */
    839enum {
    840    OPC2_32_BRR_JGE                              = 0x00,
    841    OPC2_32_BRR_JGE_U                            = 0x01,
    842};
    843/* OPCM_32_BRR_JLT                                  */
    844enum {
    845    OPC2_32_BRR_JLT                              = 0x00,
    846    OPC2_32_BRR_JLT_U                            = 0x01,
    847};
    848/* OPCM_32_BRR_JNE                                  */
    849enum {
    850    OPC2_32_BRR_JNED                             = 0x01,
    851    OPC2_32_BRR_JNEI                             = 0x00,
    852};
    853/* OPCM_32_BRR_JNZ                                  */
    854enum {
    855    OPC2_32_BRR_JNZ_A                            = 0x01,
    856    OPC2_32_BRR_JZ_A                             = 0x00,
    857};
    858/* OPCM_32_BRR_LOOP                                 */
    859enum {
    860    OPC2_32_BRR_LOOP                             = 0x00,
    861    OPC2_32_BRR_LOOPU                            = 0x01,
    862};
    863/*
    864 * RC Format
    865 */
    866/* OPCM_32_RC_LOGICAL_SHIFT                         */
    867enum {
    868    OPC2_32_RC_AND                               = 0x08,
    869    OPC2_32_RC_ANDN                              = 0x0e,
    870    OPC2_32_RC_NAND                              = 0x09,
    871    OPC2_32_RC_NOR                               = 0x0b,
    872    OPC2_32_RC_OR                                = 0x0a,
    873    OPC2_32_RC_ORN                               = 0x0f,
    874    OPC2_32_RC_SH                                = 0x00,
    875    OPC2_32_RC_SH_H                              = 0x40,
    876    OPC2_32_RC_SHA                               = 0x01,
    877    OPC2_32_RC_SHA_H                             = 0x41,
    878    OPC2_32_RC_SHAS                              = 0x02,
    879    OPC2_32_RC_XNOR                              = 0x0d,
    880    OPC2_32_RC_XOR                               = 0x0c,
    881};
    882/* OPCM_32_RC_ACCUMULATOR                           */
    883enum {
    884    OPC2_32_RC_ABSDIF                            = 0x0e,
    885    OPC2_32_RC_ABSDIFS                           = 0x0f,
    886    OPC2_32_RC_ADD                               = 0x00,
    887    OPC2_32_RC_ADDC                              = 0x05,
    888    OPC2_32_RC_ADDS                              = 0x02,
    889    OPC2_32_RC_ADDS_U                            = 0x03,
    890    OPC2_32_RC_ADDX                              = 0x04,
    891    OPC2_32_RC_AND_EQ                            = 0x20,
    892    OPC2_32_RC_AND_GE                            = 0x24,
    893    OPC2_32_RC_AND_GE_U                          = 0x25,
    894    OPC2_32_RC_AND_LT                            = 0x22,
    895    OPC2_32_RC_AND_LT_U                          = 0x23,
    896    OPC2_32_RC_AND_NE                            = 0x21,
    897    OPC2_32_RC_EQ                                = 0x10,
    898    OPC2_32_RC_EQANY_B                           = 0x56,
    899    OPC2_32_RC_EQANY_H                           = 0x76,
    900    OPC2_32_RC_GE                                = 0x14,
    901    OPC2_32_RC_GE_U                              = 0x15,
    902    OPC2_32_RC_LT                                = 0x12,
    903    OPC2_32_RC_LT_U                              = 0x13,
    904    OPC2_32_RC_MAX                               = 0x1a,
    905    OPC2_32_RC_MAX_U                             = 0x1b,
    906    OPC2_32_RC_MIN                               = 0x18,
    907    OPC2_32_RC_MIN_U                             = 0x19,
    908    OPC2_32_RC_NE                                = 0x11,
    909    OPC2_32_RC_OR_EQ                             = 0x27,
    910    OPC2_32_RC_OR_GE                             = 0x2b,
    911    OPC2_32_RC_OR_GE_U                           = 0x2c,
    912    OPC2_32_RC_OR_LT                             = 0x29,
    913    OPC2_32_RC_OR_LT_U                           = 0x2a,
    914    OPC2_32_RC_OR_NE                             = 0x28,
    915    OPC2_32_RC_RSUB                              = 0x08,
    916    OPC2_32_RC_RSUBS                             = 0x0a,
    917    OPC2_32_RC_RSUBS_U                           = 0x0b,
    918    OPC2_32_RC_SH_EQ                             = 0x37,
    919    OPC2_32_RC_SH_GE                             = 0x3b,
    920    OPC2_32_RC_SH_GE_U                           = 0x3c,
    921    OPC2_32_RC_SH_LT                             = 0x39,
    922    OPC2_32_RC_SH_LT_U                           = 0x3a,
    923    OPC2_32_RC_SH_NE                             = 0x38,
    924    OPC2_32_RC_XOR_EQ                            = 0x2f,
    925    OPC2_32_RC_XOR_GE                            = 0x33,
    926    OPC2_32_RC_XOR_GE_U                          = 0x34,
    927    OPC2_32_RC_XOR_LT                            = 0x31,
    928    OPC2_32_RC_XOR_LT_U                          = 0x32,
    929    OPC2_32_RC_XOR_NE                            = 0x30,
    930};
    931/* OPCM_32_RC_SERVICEROUTINE                        */
    932enum {
    933    OPC2_32_RC_BISR                              = 0x00,
    934    OPC2_32_RC_SYSCALL                           = 0x04,
    935};
    936/* OPCM_32_RC_MUL                                   */
    937enum {
    938    OPC2_32_RC_MUL_32                            = 0x01,
    939    OPC2_32_RC_MUL_64                            = 0x03,
    940    OPC2_32_RC_MULS_32                           = 0x05,
    941    OPC2_32_RC_MUL_U_64                          = 0x02,
    942    OPC2_32_RC_MULS_U_32                         = 0x04,
    943};
    944/*
    945 * RCPW Format
    946 */
    947/* OPCM_32_RCPW_MASK_INSERT                         */
    948enum {
    949    OPC2_32_RCPW_IMASK                           = 0x01,
    950    OPC2_32_RCPW_INSERT                          = 0x00,
    951};
    952/*
    953 * RCR Format
    954 */
    955/* OPCM_32_RCR_COND_SELECT                          */
    956enum {
    957    OPC2_32_RCR_CADD                             = 0x00,
    958    OPC2_32_RCR_CADDN                            = 0x01,
    959    OPC2_32_RCR_SEL                              = 0x04,
    960    OPC2_32_RCR_SELN                             = 0x05,
    961};
    962/* OPCM_32_RCR_MADD                                 */
    963enum {
    964    OPC2_32_RCR_MADD_32                          = 0x01,
    965    OPC2_32_RCR_MADD_64                          = 0x03,
    966    OPC2_32_RCR_MADDS_32                         = 0x05,
    967    OPC2_32_RCR_MADDS_64                         = 0x07,
    968    OPC2_32_RCR_MADD_U_64                        = 0x02,
    969    OPC2_32_RCR_MADDS_U_32                       = 0x04,
    970    OPC2_32_RCR_MADDS_U_64                       = 0x06,
    971};
    972/* OPCM_32_RCR_MSUB                                 */
    973enum {
    974    OPC2_32_RCR_MSUB_32                          = 0x01,
    975    OPC2_32_RCR_MSUB_64                          = 0x03,
    976    OPC2_32_RCR_MSUBS_32                         = 0x05,
    977    OPC2_32_RCR_MSUBS_64                         = 0x07,
    978    OPC2_32_RCR_MSUB_U_64                        = 0x02,
    979    OPC2_32_RCR_MSUBS_U_32                       = 0x04,
    980    OPC2_32_RCR_MSUBS_U_64                       = 0x06,
    981};
    982/*
    983 * RCRW Format
    984 */
    985/* OPCM_32_RCRW_MASK_INSERT                         */
    986enum {
    987    OPC2_32_RCRW_IMASK                           = 0x01,
    988    OPC2_32_RCRW_INSERT                          = 0x00,
    989};
    990
    991/*
    992 * RR Format
    993 */
    994/* OPCM_32_RR_LOGICAL_SHIFT                         */
    995enum {
    996    OPC2_32_RR_AND                               = 0x08,
    997    OPC2_32_RR_ANDN                              = 0x0e,
    998    OPC2_32_RR_CLO                               = 0x1c,
    999    OPC2_32_RR_CLO_H                             = 0x7d,
   1000    OPC2_32_RR_CLS                               = 0x1d,
   1001    OPC2_32_RR_CLS_H                             = 0x7e,
   1002    OPC2_32_RR_CLZ                               = 0x1b,
   1003    OPC2_32_RR_CLZ_H                             = 0x7c,
   1004    OPC2_32_RR_NAND                              = 0x09,
   1005    OPC2_32_RR_NOR                               = 0x0b,
   1006    OPC2_32_RR_OR                                = 0x0a,
   1007    OPC2_32_RR_ORN                               = 0x0f,
   1008    OPC2_32_RR_SH                                = 0x00,
   1009    OPC2_32_RR_SH_H                              = 0x40,
   1010    OPC2_32_RR_SHA                               = 0x01,
   1011    OPC2_32_RR_SHA_H                             = 0x41,
   1012    OPC2_32_RR_SHAS                              = 0x02,
   1013    OPC2_32_RR_XNOR                              = 0x0d,
   1014    OPC2_32_RR_XOR                               = 0x0c,
   1015};
   1016/* OPCM_32_RR_ACCUMULATOR                           */
   1017enum {
   1018    OPC2_32_RR_ABS                               = 0x1c,
   1019    OPC2_32_RR_ABS_B                             = 0x5c,
   1020    OPC2_32_RR_ABS_H                             = 0x7c,
   1021    OPC2_32_RR_ABSDIF                            = 0x0e,
   1022    OPC2_32_RR_ABSDIF_B                          = 0x4e,
   1023    OPC2_32_RR_ABSDIF_H                          = 0x6e,
   1024    OPC2_32_RR_ABSDIFS                           = 0x0f,
   1025    OPC2_32_RR_ABSDIFS_H                         = 0x6f,
   1026    OPC2_32_RR_ABSS                              = 0x1d,
   1027    OPC2_32_RR_ABSS_H                            = 0x7d,
   1028    OPC2_32_RR_ADD                               = 0x00,
   1029    OPC2_32_RR_ADD_B                             = 0x40,
   1030    OPC2_32_RR_ADD_H                             = 0x60,
   1031    OPC2_32_RR_ADDC                              = 0x05,
   1032    OPC2_32_RR_ADDS                              = 0x02,
   1033    OPC2_32_RR_ADDS_H                            = 0x62,
   1034    OPC2_32_RR_ADDS_HU                           = 0x63,
   1035    OPC2_32_RR_ADDS_U                            = 0x03,
   1036    OPC2_32_RR_ADDX                              = 0x04,
   1037    OPC2_32_RR_AND_EQ                            = 0x20,
   1038    OPC2_32_RR_AND_GE                            = 0x24,
   1039    OPC2_32_RR_AND_GE_U                          = 0x25,
   1040    OPC2_32_RR_AND_LT                            = 0x22,
   1041    OPC2_32_RR_AND_LT_U                          = 0x23,
   1042    OPC2_32_RR_AND_NE                            = 0x21,
   1043    OPC2_32_RR_EQ                                = 0x10,
   1044    OPC2_32_RR_EQ_B                              = 0x50,
   1045    OPC2_32_RR_EQ_H                              = 0x70,
   1046    OPC2_32_RR_EQ_W                              = 0x90,
   1047    OPC2_32_RR_EQANY_B                           = 0x56,
   1048    OPC2_32_RR_EQANY_H                           = 0x76,
   1049    OPC2_32_RR_GE                                = 0x14,
   1050    OPC2_32_RR_GE_U                              = 0x15,
   1051    OPC2_32_RR_LT                                = 0x12,
   1052    OPC2_32_RR_LT_U                              = 0x13,
   1053    OPC2_32_RR_LT_B                              = 0x52,
   1054    OPC2_32_RR_LT_BU                             = 0x53,
   1055    OPC2_32_RR_LT_H                              = 0x72,
   1056    OPC2_32_RR_LT_HU                             = 0x73,
   1057    OPC2_32_RR_LT_W                              = 0x92,
   1058    OPC2_32_RR_LT_WU                             = 0x93,
   1059    OPC2_32_RR_MAX                               = 0x1a,
   1060    OPC2_32_RR_MAX_U                             = 0x1b,
   1061    OPC2_32_RR_MAX_B                             = 0x5a,
   1062    OPC2_32_RR_MAX_BU                            = 0x5b,
   1063    OPC2_32_RR_MAX_H                             = 0x7a,
   1064    OPC2_32_RR_MAX_HU                            = 0x7b,
   1065    OPC2_32_RR_MIN                               = 0x18,
   1066    OPC2_32_RR_MIN_U                             = 0x19,
   1067    OPC2_32_RR_MIN_B                             = 0x58,
   1068    OPC2_32_RR_MIN_BU                            = 0x59,
   1069    OPC2_32_RR_MIN_H                             = 0x78,
   1070    OPC2_32_RR_MIN_HU                            = 0x79,
   1071    OPC2_32_RR_MOV                               = 0x1f,
   1072    OPC2_32_RR_MOVS_64                           = 0x80,
   1073    OPC2_32_RR_MOV_64                            = 0x81,
   1074    OPC2_32_RR_NE                                = 0x11,
   1075    OPC2_32_RR_OR_EQ                             = 0x27,
   1076    OPC2_32_RR_OR_GE                             = 0x2b,
   1077    OPC2_32_RR_OR_GE_U                           = 0x2c,
   1078    OPC2_32_RR_OR_LT                             = 0x29,
   1079    OPC2_32_RR_OR_LT_U                           = 0x2a,
   1080    OPC2_32_RR_OR_NE                             = 0x28,
   1081    OPC2_32_RR_SAT_B                             = 0x5e,
   1082    OPC2_32_RR_SAT_BU                            = 0x5f,
   1083    OPC2_32_RR_SAT_H                             = 0x7e,
   1084    OPC2_32_RR_SAT_HU                            = 0x7f,
   1085    OPC2_32_RR_SH_EQ                             = 0x37,
   1086    OPC2_32_RR_SH_GE                             = 0x3b,
   1087    OPC2_32_RR_SH_GE_U                           = 0x3c,
   1088    OPC2_32_RR_SH_LT                             = 0x39,
   1089    OPC2_32_RR_SH_LT_U                           = 0x3a,
   1090    OPC2_32_RR_SH_NE                             = 0x38,
   1091    OPC2_32_RR_SUB                               = 0x08,
   1092    OPC2_32_RR_SUB_B                             = 0x48,
   1093    OPC2_32_RR_SUB_H                             = 0x68,
   1094    OPC2_32_RR_SUBC                              = 0x0d,
   1095    OPC2_32_RR_SUBS                              = 0x0a,
   1096    OPC2_32_RR_SUBS_U                            = 0x0b,
   1097    OPC2_32_RR_SUBS_H                            = 0x6a,
   1098    OPC2_32_RR_SUBS_HU                           = 0x6b,
   1099    OPC2_32_RR_SUBX                              = 0x0c,
   1100    OPC2_32_RR_XOR_EQ                            = 0x2f,
   1101    OPC2_32_RR_XOR_GE                            = 0x33,
   1102    OPC2_32_RR_XOR_GE_U                          = 0x34,
   1103    OPC2_32_RR_XOR_LT                            = 0x31,
   1104    OPC2_32_RR_XOR_LT_U                          = 0x32,
   1105    OPC2_32_RR_XOR_NE                            = 0x30,
   1106};
   1107/* OPCM_32_RR_ADDRESS                               */
   1108enum {
   1109    OPC2_32_RR_ADD_A                             = 0x01,
   1110    OPC2_32_RR_ADDSC_A                           = 0x60,
   1111    OPC2_32_RR_ADDSC_AT                          = 0x62,
   1112    OPC2_32_RR_EQ_A                              = 0x40,
   1113    OPC2_32_RR_EQZ                               = 0x48,
   1114    OPC2_32_RR_GE_A                              = 0x43,
   1115    OPC2_32_RR_LT_A                              = 0x42,
   1116    OPC2_32_RR_MOV_A                             = 0x63,
   1117    OPC2_32_RR_MOV_AA                            = 0x00,
   1118    OPC2_32_RR_MOV_D                             = 0x4c,
   1119    OPC2_32_RR_NE_A                              = 0x41,
   1120    OPC2_32_RR_NEZ_A                             = 0x49,
   1121    OPC2_32_RR_SUB_A                             = 0x02,
   1122};
   1123/* OPCM_32_RR_FLOAT                                 */
   1124enum {
   1125    OPC2_32_RR_BMERGE                            = 0x01,
   1126    OPC2_32_RR_BSPLIT                            = 0x09,
   1127    OPC2_32_RR_DVINIT_B                          = 0x5a,
   1128    OPC2_32_RR_DVINIT_BU                         = 0x4a,
   1129    OPC2_32_RR_DVINIT_H                          = 0x3a,
   1130    OPC2_32_RR_DVINIT_HU                         = 0x2a,
   1131    OPC2_32_RR_DVINIT                            = 0x1a,
   1132    OPC2_32_RR_DVINIT_U                          = 0x0a,
   1133    OPC2_32_RR_PARITY                            = 0x02,
   1134    OPC2_32_RR_UNPACK                            = 0x08,
   1135    OPC2_32_RR_CRC32                             = 0x03,
   1136    OPC2_32_RR_DIV                               = 0x20,
   1137    OPC2_32_RR_DIV_U                             = 0x21,
   1138    OPC2_32_RR_MUL_F                             = 0x04,
   1139    OPC2_32_RR_DIV_F                             = 0x05,
   1140    OPC2_32_RR_FTOI                              = 0x10,
   1141    OPC2_32_RR_ITOF                              = 0x14,
   1142    OPC2_32_RR_CMP_F                             = 0x00,
   1143    OPC2_32_RR_FTOIZ                             = 0x13,
   1144    OPC2_32_RR_FTOQ31                            = 0x11,
   1145    OPC2_32_RR_FTOQ31Z                           = 0x18,
   1146    OPC2_32_RR_FTOU                              = 0x12,
   1147    OPC2_32_RR_FTOUZ                             = 0x17,
   1148    OPC2_32_RR_Q31TOF                            = 0x15,
   1149    OPC2_32_RR_QSEED_F                           = 0x19,
   1150    OPC2_32_RR_UPDFL                             = 0x0c,
   1151    OPC2_32_RR_UTOF                              = 0x16,
   1152};
   1153/* OPCM_32_RR_IDIRECT                               */
   1154enum {
   1155    OPC2_32_RR_JI                                = 0x03,
   1156    OPC2_32_RR_JLI                               = 0x02,
   1157    OPC2_32_RR_CALLI                             = 0x00,
   1158    OPC2_32_RR_FCALLI                            = 0x01,
   1159};
   1160/*
   1161 * RR1 Format
   1162 */
   1163/* OPCM_32_RR1_MUL                                  */
   1164enum {
   1165    OPC2_32_RR1_MUL_H_32_LL                      = 0x1a,
   1166    OPC2_32_RR1_MUL_H_32_LU                      = 0x19,
   1167    OPC2_32_RR1_MUL_H_32_UL                      = 0x18,
   1168    OPC2_32_RR1_MUL_H_32_UU                      = 0x1b,
   1169    OPC2_32_RR1_MULM_H_64_LL                     = 0x1e,
   1170    OPC2_32_RR1_MULM_H_64_LU                     = 0x1d,
   1171    OPC2_32_RR1_MULM_H_64_UL                     = 0x1c,
   1172    OPC2_32_RR1_MULM_H_64_UU                     = 0x1f,
   1173    OPC2_32_RR1_MULR_H_16_LL                     = 0x0e,
   1174    OPC2_32_RR1_MULR_H_16_LU                     = 0x0d,
   1175    OPC2_32_RR1_MULR_H_16_UL                     = 0x0c,
   1176    OPC2_32_RR1_MULR_H_16_UU                     = 0x0f,
   1177};
   1178/* OPCM_32_RR1_MULQ                                 */
   1179enum {
   1180    OPC2_32_RR1_MUL_Q_32                         = 0x02,
   1181    OPC2_32_RR1_MUL_Q_64                         = 0x1b,
   1182    OPC2_32_RR1_MUL_Q_32_L                       = 0x01,
   1183    OPC2_32_RR1_MUL_Q_64_L                       = 0x19,
   1184    OPC2_32_RR1_MUL_Q_32_U                       = 0x00,
   1185    OPC2_32_RR1_MUL_Q_64_U                       = 0x18,
   1186    OPC2_32_RR1_MUL_Q_32_LL                      = 0x05,
   1187    OPC2_32_RR1_MUL_Q_32_UU                      = 0x04,
   1188    OPC2_32_RR1_MULR_Q_32_L                      = 0x07,
   1189    OPC2_32_RR1_MULR_Q_32_U                      = 0x06,
   1190};
   1191/*
   1192 * RR2 Format
   1193 */
   1194/* OPCM_32_RR2_MUL                                  */
   1195enum {
   1196    OPC2_32_RR2_MUL_32                           = 0x0a,
   1197    OPC2_32_RR2_MUL_64                           = 0x6a,
   1198    OPC2_32_RR2_MULS_32                          = 0x8a,
   1199    OPC2_32_RR2_MUL_U_64                         = 0x68,
   1200    OPC2_32_RR2_MULS_U_32                        = 0x88,
   1201};
   1202/*
   1203 * RRPW Format
   1204 */
   1205/* OPCM_32_RRPW_EXTRACT_INSERT                      */
   1206enum {
   1207
   1208    OPC2_32_RRPW_EXTR                            = 0x02,
   1209    OPC2_32_RRPW_EXTR_U                          = 0x03,
   1210    OPC2_32_RRPW_IMASK                           = 0x01,
   1211    OPC2_32_RRPW_INSERT                          = 0x00,
   1212};
   1213/*
   1214 * RRR Format
   1215 */
   1216/* OPCM_32_RRR_COND_SELECT                          */
   1217enum {
   1218    OPC2_32_RRR_CADD                             = 0x00,
   1219    OPC2_32_RRR_CADDN                            = 0x01,
   1220    OPC2_32_RRR_CSUB                             = 0x02,
   1221    OPC2_32_RRR_CSUBN                            = 0x03,
   1222    OPC2_32_RRR_SEL                              = 0x04,
   1223    OPC2_32_RRR_SELN                             = 0x05,
   1224};
   1225/* OPCM_32_RRR_FLOAT                                */
   1226enum {
   1227    OPC2_32_RRR_DVADJ                            = 0x0d,
   1228    OPC2_32_RRR_DVSTEP                           = 0x0f,
   1229    OPC2_32_RRR_DVSTEP_U                         = 0x0e,
   1230    OPC2_32_RRR_IXMAX                            = 0x0a,
   1231    OPC2_32_RRR_IXMAX_U                          = 0x0b,
   1232    OPC2_32_RRR_IXMIN                            = 0x08,
   1233    OPC2_32_RRR_IXMIN_U                          = 0x09,
   1234    OPC2_32_RRR_PACK                             = 0x00,
   1235    OPC2_32_RRR_ADD_F                            = 0x02,
   1236    OPC2_32_RRR_SUB_F                            = 0x03,
   1237    OPC2_32_RRR_MADD_F                           = 0x06,
   1238    OPC2_32_RRR_MSUB_F                           = 0x07,
   1239};
   1240/*
   1241 * RRR1 Format
   1242 */
   1243/* OPCM_32_RRR1_MADD                                */
   1244enum {
   1245    OPC2_32_RRR1_MADD_H_LL                       = 0x1a,
   1246    OPC2_32_RRR1_MADD_H_LU                       = 0x19,
   1247    OPC2_32_RRR1_MADD_H_UL                       = 0x18,
   1248    OPC2_32_RRR1_MADD_H_UU                       = 0x1b,
   1249    OPC2_32_RRR1_MADDS_H_LL                      = 0x3a,
   1250    OPC2_32_RRR1_MADDS_H_LU                      = 0x39,
   1251    OPC2_32_RRR1_MADDS_H_UL                      = 0x38,
   1252    OPC2_32_RRR1_MADDS_H_UU                      = 0x3b,
   1253    OPC2_32_RRR1_MADDM_H_LL                      = 0x1e,
   1254    OPC2_32_RRR1_MADDM_H_LU                      = 0x1d,
   1255    OPC2_32_RRR1_MADDM_H_UL                      = 0x1c,
   1256    OPC2_32_RRR1_MADDM_H_UU                      = 0x1f,
   1257    OPC2_32_RRR1_MADDMS_H_LL                     = 0x3e,
   1258    OPC2_32_RRR1_MADDMS_H_LU                     = 0x3d,
   1259    OPC2_32_RRR1_MADDMS_H_UL                     = 0x3c,
   1260    OPC2_32_RRR1_MADDMS_H_UU                     = 0x3f,
   1261    OPC2_32_RRR1_MADDR_H_LL                      = 0x0e,
   1262    OPC2_32_RRR1_MADDR_H_LU                      = 0x0d,
   1263    OPC2_32_RRR1_MADDR_H_UL                      = 0x0c,
   1264    OPC2_32_RRR1_MADDR_H_UU                      = 0x0f,
   1265    OPC2_32_RRR1_MADDRS_H_LL                     = 0x2e,
   1266    OPC2_32_RRR1_MADDRS_H_LU                     = 0x2d,
   1267    OPC2_32_RRR1_MADDRS_H_UL                     = 0x2c,
   1268    OPC2_32_RRR1_MADDRS_H_UU                     = 0x2f,
   1269};
   1270/* OPCM_32_RRR1_MADDQ_H                             */
   1271enum {
   1272    OPC2_32_RRR1_MADD_Q_32                       = 0x02,
   1273    OPC2_32_RRR1_MADD_Q_64                       = 0x1b,
   1274    OPC2_32_RRR1_MADD_Q_32_L                     = 0x01,
   1275    OPC2_32_RRR1_MADD_Q_64_L                     = 0x19,
   1276    OPC2_32_RRR1_MADD_Q_32_U                     = 0x00,
   1277    OPC2_32_RRR1_MADD_Q_64_U                     = 0x18,
   1278    OPC2_32_RRR1_MADD_Q_32_LL                    = 0x05,
   1279    OPC2_32_RRR1_MADD_Q_64_LL                    = 0x1d,
   1280    OPC2_32_RRR1_MADD_Q_32_UU                    = 0x04,
   1281    OPC2_32_RRR1_MADD_Q_64_UU                    = 0x1c,
   1282    OPC2_32_RRR1_MADDS_Q_32                      = 0x22,
   1283    OPC2_32_RRR1_MADDS_Q_64                      = 0x3b,
   1284    OPC2_32_RRR1_MADDS_Q_32_L                    = 0x21,
   1285    OPC2_32_RRR1_MADDS_Q_64_L                    = 0x39,
   1286    OPC2_32_RRR1_MADDS_Q_32_U                    = 0x20,
   1287    OPC2_32_RRR1_MADDS_Q_64_U                    = 0x38,
   1288    OPC2_32_RRR1_MADDS_Q_32_LL                   = 0x25,
   1289    OPC2_32_RRR1_MADDS_Q_64_LL                   = 0x3d,
   1290    OPC2_32_RRR1_MADDS_Q_32_UU                   = 0x24,
   1291    OPC2_32_RRR1_MADDS_Q_64_UU                   = 0x3c,
   1292    OPC2_32_RRR1_MADDR_H_64_UL                   = 0x1e,
   1293    OPC2_32_RRR1_MADDRS_H_64_UL                  = 0x3e,
   1294    OPC2_32_RRR1_MADDR_Q_32_LL                   = 0x07,
   1295    OPC2_32_RRR1_MADDR_Q_32_UU                   = 0x06,
   1296    OPC2_32_RRR1_MADDRS_Q_32_LL                  = 0x27,
   1297    OPC2_32_RRR1_MADDRS_Q_32_UU                  = 0x26,
   1298};
   1299/* OPCM_32_RRR1_MADDSU_H                            */
   1300enum {
   1301    OPC2_32_RRR1_MADDSU_H_32_LL                  = 0x1a,
   1302    OPC2_32_RRR1_MADDSU_H_32_LU                  = 0x19,
   1303    OPC2_32_RRR1_MADDSU_H_32_UL                  = 0x18,
   1304    OPC2_32_RRR1_MADDSU_H_32_UU                  = 0x1b,
   1305    OPC2_32_RRR1_MADDSUS_H_32_LL                 = 0x3a,
   1306    OPC2_32_RRR1_MADDSUS_H_32_LU                 = 0x39,
   1307    OPC2_32_RRR1_MADDSUS_H_32_UL                 = 0x38,
   1308    OPC2_32_RRR1_MADDSUS_H_32_UU                 = 0x3b,
   1309    OPC2_32_RRR1_MADDSUM_H_64_LL                 = 0x1e,
   1310    OPC2_32_RRR1_MADDSUM_H_64_LU                 = 0x1d,
   1311    OPC2_32_RRR1_MADDSUM_H_64_UL                 = 0x1c,
   1312    OPC2_32_RRR1_MADDSUM_H_64_UU                 = 0x1f,
   1313    OPC2_32_RRR1_MADDSUMS_H_64_LL                = 0x3e,
   1314    OPC2_32_RRR1_MADDSUMS_H_64_LU                = 0x3d,
   1315    OPC2_32_RRR1_MADDSUMS_H_64_UL                = 0x3c,
   1316    OPC2_32_RRR1_MADDSUMS_H_64_UU                = 0x3f,
   1317    OPC2_32_RRR1_MADDSUR_H_16_LL                 = 0x0e,
   1318    OPC2_32_RRR1_MADDSUR_H_16_LU                 = 0x0d,
   1319    OPC2_32_RRR1_MADDSUR_H_16_UL                 = 0x0c,
   1320    OPC2_32_RRR1_MADDSUR_H_16_UU                 = 0x0f,
   1321    OPC2_32_RRR1_MADDSURS_H_16_LL                = 0x2e,
   1322    OPC2_32_RRR1_MADDSURS_H_16_LU                = 0x2d,
   1323    OPC2_32_RRR1_MADDSURS_H_16_UL                = 0x2c,
   1324    OPC2_32_RRR1_MADDSURS_H_16_UU                = 0x2f,
   1325};
   1326/* OPCM_32_RRR1_MSUB_H                              */
   1327enum {
   1328    OPC2_32_RRR1_MSUB_H_LL                       = 0x1a,
   1329    OPC2_32_RRR1_MSUB_H_LU                       = 0x19,
   1330    OPC2_32_RRR1_MSUB_H_UL                       = 0x18,
   1331    OPC2_32_RRR1_MSUB_H_UU                       = 0x1b,
   1332    OPC2_32_RRR1_MSUBS_H_LL                      = 0x3a,
   1333    OPC2_32_RRR1_MSUBS_H_LU                      = 0x39,
   1334    OPC2_32_RRR1_MSUBS_H_UL                      = 0x38,
   1335    OPC2_32_RRR1_MSUBS_H_UU                      = 0x3b,
   1336    OPC2_32_RRR1_MSUBM_H_LL                      = 0x1e,
   1337    OPC2_32_RRR1_MSUBM_H_LU                      = 0x1d,
   1338    OPC2_32_RRR1_MSUBM_H_UL                      = 0x1c,
   1339    OPC2_32_RRR1_MSUBM_H_UU                      = 0x1f,
   1340    OPC2_32_RRR1_MSUBMS_H_LL                     = 0x3e,
   1341    OPC2_32_RRR1_MSUBMS_H_LU                     = 0x3d,
   1342    OPC2_32_RRR1_MSUBMS_H_UL                     = 0x3c,
   1343    OPC2_32_RRR1_MSUBMS_H_UU                     = 0x3f,
   1344    OPC2_32_RRR1_MSUBR_H_LL                      = 0x0e,
   1345    OPC2_32_RRR1_MSUBR_H_LU                      = 0x0d,
   1346    OPC2_32_RRR1_MSUBR_H_UL                      = 0x0c,
   1347    OPC2_32_RRR1_MSUBR_H_UU                      = 0x0f,
   1348    OPC2_32_RRR1_MSUBRS_H_LL                     = 0x2e,
   1349    OPC2_32_RRR1_MSUBRS_H_LU                     = 0x2d,
   1350    OPC2_32_RRR1_MSUBRS_H_UL                     = 0x2c,
   1351    OPC2_32_RRR1_MSUBRS_H_UU                     = 0x2f,
   1352};
   1353/* OPCM_32_RRR1_MSUB_Q                              */
   1354enum {
   1355    OPC2_32_RRR1_MSUB_Q_32                       = 0x02,
   1356    OPC2_32_RRR1_MSUB_Q_64                       = 0x1b,
   1357    OPC2_32_RRR1_MSUB_Q_32_L                     = 0x01,
   1358    OPC2_32_RRR1_MSUB_Q_64_L                     = 0x19,
   1359    OPC2_32_RRR1_MSUB_Q_32_U                     = 0x00,
   1360    OPC2_32_RRR1_MSUB_Q_64_U                     = 0x18,
   1361    OPC2_32_RRR1_MSUB_Q_32_LL                    = 0x05,
   1362    OPC2_32_RRR1_MSUB_Q_64_LL                    = 0x1d,
   1363    OPC2_32_RRR1_MSUB_Q_32_UU                    = 0x04,
   1364    OPC2_32_RRR1_MSUB_Q_64_UU                    = 0x1c,
   1365    OPC2_32_RRR1_MSUBS_Q_32                      = 0x22,
   1366    OPC2_32_RRR1_MSUBS_Q_64                      = 0x3b,
   1367    OPC2_32_RRR1_MSUBS_Q_32_L                    = 0x21,
   1368    OPC2_32_RRR1_MSUBS_Q_64_L                    = 0x39,
   1369    OPC2_32_RRR1_MSUBS_Q_32_U                    = 0x20,
   1370    OPC2_32_RRR1_MSUBS_Q_64_U                    = 0x38,
   1371    OPC2_32_RRR1_MSUBS_Q_32_LL                   = 0x25,
   1372    OPC2_32_RRR1_MSUBS_Q_64_LL                   = 0x3d,
   1373    OPC2_32_RRR1_MSUBS_Q_32_UU                   = 0x24,
   1374    OPC2_32_RRR1_MSUBS_Q_64_UU                   = 0x3c,
   1375    OPC2_32_RRR1_MSUBR_H_64_UL                   = 0x1e,
   1376    OPC2_32_RRR1_MSUBRS_H_64_UL                  = 0x3e,
   1377    OPC2_32_RRR1_MSUBR_Q_32_LL                   = 0x07,
   1378    OPC2_32_RRR1_MSUBR_Q_32_UU                   = 0x06,
   1379    OPC2_32_RRR1_MSUBRS_Q_32_LL                  = 0x27,
   1380    OPC2_32_RRR1_MSUBRS_Q_32_UU                  = 0x26,
   1381};
   1382/* OPCM_32_RRR1_MSUBADS_H                           */
   1383enum {
   1384    OPC2_32_RRR1_MSUBAD_H_32_LL                  = 0x1a,
   1385    OPC2_32_RRR1_MSUBAD_H_32_LU                  = 0x19,
   1386    OPC2_32_RRR1_MSUBAD_H_32_UL                  = 0x18,
   1387    OPC2_32_RRR1_MSUBAD_H_32_UU                  = 0x1b,
   1388    OPC2_32_RRR1_MSUBADS_H_32_LL                 = 0x3a,
   1389    OPC2_32_RRR1_MSUBADS_H_32_LU                 = 0x39,
   1390    OPC2_32_RRR1_MSUBADS_H_32_UL                 = 0x38,
   1391    OPC2_32_RRR1_MSUBADS_H_32_UU                 = 0x3b,
   1392    OPC2_32_RRR1_MSUBADM_H_64_LL                 = 0x1e,
   1393    OPC2_32_RRR1_MSUBADM_H_64_LU                 = 0x1d,
   1394    OPC2_32_RRR1_MSUBADM_H_64_UL                 = 0x1c,
   1395    OPC2_32_RRR1_MSUBADM_H_64_UU                 = 0x1f,
   1396    OPC2_32_RRR1_MSUBADMS_H_64_LL                = 0x3e,
   1397    OPC2_32_RRR1_MSUBADMS_H_64_LU                = 0x3d,
   1398    OPC2_32_RRR1_MSUBADMS_H_64_UL                = 0x3c,
   1399    OPC2_32_RRR1_MSUBADMS_H_64_UU                = 0x3f,
   1400    OPC2_32_RRR1_MSUBADR_H_16_LL                 = 0x0e,
   1401    OPC2_32_RRR1_MSUBADR_H_16_LU                 = 0x0d,
   1402    OPC2_32_RRR1_MSUBADR_H_16_UL                 = 0x0c,
   1403    OPC2_32_RRR1_MSUBADR_H_16_UU                 = 0x0f,
   1404    OPC2_32_RRR1_MSUBADRS_H_16_LL                = 0x2e,
   1405    OPC2_32_RRR1_MSUBADRS_H_16_LU                = 0x2d,
   1406    OPC2_32_RRR1_MSUBADRS_H_16_UL                = 0x2c,
   1407    OPC2_32_RRR1_MSUBADRS_H_16_UU                = 0x2f,
   1408};
   1409/*
   1410 * RRR2 Format
   1411 */
   1412/* OPCM_32_RRR2_MADD                                */
   1413enum {
   1414    OPC2_32_RRR2_MADD_32                         = 0x0a,
   1415    OPC2_32_RRR2_MADD_64                         = 0x6a,
   1416    OPC2_32_RRR2_MADDS_32                        = 0x8a,
   1417    OPC2_32_RRR2_MADDS_64                        = 0xea,
   1418    OPC2_32_RRR2_MADD_U_64                       = 0x68,
   1419    OPC2_32_RRR2_MADDS_U_32                      = 0x88,
   1420    OPC2_32_RRR2_MADDS_U_64                      = 0xe8,
   1421};
   1422/* OPCM_32_RRR2_MSUB                                */
   1423enum {
   1424    OPC2_32_RRR2_MSUB_32                         = 0x0a,
   1425    OPC2_32_RRR2_MSUB_64                         = 0x6a,
   1426    OPC2_32_RRR2_MSUBS_32                        = 0x8a,
   1427    OPC2_32_RRR2_MSUBS_64                        = 0xea,
   1428    OPC2_32_RRR2_MSUB_U_64                       = 0x68,
   1429    OPC2_32_RRR2_MSUBS_U_32                      = 0x88,
   1430    OPC2_32_RRR2_MSUBS_U_64                      = 0xe8,
   1431};
   1432/*
   1433 * RRRR Format
   1434 */
   1435/* OPCM_32_RRRR_EXTRACT_INSERT                      */
   1436enum {
   1437    OPC2_32_RRRR_DEXTR                           = 0x04,
   1438    OPC2_32_RRRR_EXTR                            = 0x02,
   1439    OPC2_32_RRRR_EXTR_U                          = 0x03,
   1440    OPC2_32_RRRR_INSERT                          = 0x00,
   1441};
   1442/*
   1443 * RRRW Format
   1444 */
   1445/* OPCM_32_RRRW_EXTRACT_INSERT                      */
   1446enum {
   1447    OPC2_32_RRRW_EXTR                            = 0x02,
   1448    OPC2_32_RRRW_EXTR_U                          = 0x03,
   1449    OPC2_32_RRRW_IMASK                           = 0x01,
   1450    OPC2_32_RRRW_INSERT                          = 0x00,
   1451};
   1452/*
   1453 * SYS Format
   1454 */
   1455/* OPCM_32_SYS_INTERRUPTS                           */
   1456enum {
   1457    OPC2_32_SYS_DEBUG                            = 0x04,
   1458    OPC2_32_SYS_DISABLE                          = 0x0d,
   1459    OPC2_32_SYS_DSYNC                            = 0x12,
   1460    OPC2_32_SYS_ENABLE                           = 0x0c,
   1461    OPC2_32_SYS_ISYNC                            = 0x13,
   1462    OPC2_32_SYS_NOP                              = 0x00,
   1463    OPC2_32_SYS_RET                              = 0x06,
   1464    OPC2_32_SYS_RFE                              = 0x07,
   1465    OPC2_32_SYS_RFM                              = 0x05,
   1466    OPC2_32_SYS_RSLCX                            = 0x09,
   1467    OPC2_32_SYS_SVLCX                            = 0x08,
   1468    OPC2_32_SYS_TRAPSV                           = 0x15,
   1469    OPC2_32_SYS_TRAPV                            = 0x14,
   1470    OPC2_32_SYS_RESTORE                          = 0x0e,
   1471    OPC2_32_SYS_FRET                             = 0x03,
   1472};
   1473
   1474#endif