overlay_tool.h (25414B)
1/* 2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#define XTREG(idx, ofs, bi, sz, al, no, fl, cp, typ, grp, name, \ 29 a1, a2, a3, a4, a5, a6) { \ 30 .targno = (no), \ 31 .flags = (fl), \ 32 .type = (typ), \ 33 .group = (grp), \ 34 .size = (sz), \ 35}, 36#define XTREG_END { .targno = -1 }, 37 38#ifndef XCHAL_HAVE_DEPBITS 39#define XCHAL_HAVE_DEPBITS 0 40#endif 41 42#ifndef XCHAL_HAVE_DFP 43#define XCHAL_HAVE_DFP 0 44#endif 45 46#ifndef XCHAL_HAVE_DFPU_SINGLE_ONLY 47#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 48#endif 49 50#ifndef XCHAL_HAVE_DFPU_SINGLE_DOUBLE 51#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE XCHAL_HAVE_DFP 52#endif 53 54/* 55 * We need to know the type of FP unit, not only its precision. 56 * Unfortunately XCHAL macros don't tell this explicitly. 57 */ 58#define XCHAL_HAVE_DFPU (XCHAL_HAVE_DFP || \ 59 XCHAL_HAVE_DFPU_SINGLE_ONLY || \ 60 XCHAL_HAVE_DFPU_SINGLE_DOUBLE) 61 62#ifndef XCHAL_HAVE_DIV32 63#define XCHAL_HAVE_DIV32 0 64#endif 65 66#ifndef XCHAL_UNALIGNED_LOAD_HW 67#define XCHAL_UNALIGNED_LOAD_HW 0 68#endif 69 70#ifndef XCHAL_HAVE_VECBASE 71#define XCHAL_HAVE_VECBASE 0 72#define XCHAL_VECBASE_RESET_VADDR 0 73#endif 74 75#ifndef XCHAL_RESET_VECTOR0_VADDR 76#define XCHAL_RESET_VECTOR0_VADDR XCHAL_RESET_VECTOR_VADDR 77#endif 78 79#ifndef XCHAL_RESET_VECTOR1_VADDR 80#define XCHAL_RESET_VECTOR1_VADDR XCHAL_RESET_VECTOR_VADDR 81#endif 82 83#ifndef XCHAL_HW_VERSION 84#define XCHAL_HW_VERSION (XCHAL_HW_VERSION_MAJOR * 100 \ 85 + XCHAL_HW_VERSION_MINOR) 86#endif 87 88#ifndef XCHAL_LOOP_BUFFER_SIZE 89#define XCHAL_LOOP_BUFFER_SIZE 0 90#endif 91 92#ifndef XCHAL_HAVE_EXTERN_REGS 93#define XCHAL_HAVE_EXTERN_REGS 0 94#endif 95 96#ifndef XCHAL_HAVE_MPU 97#define XCHAL_HAVE_MPU 0 98#endif 99 100#ifndef XCHAL_HAVE_EXCLUSIVE 101#define XCHAL_HAVE_EXCLUSIVE 0 102#endif 103 104#define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0) 105 106#define XTENSA_OPTIONS ( \ 107 XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) | \ 108 XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) | \ 109 XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) | \ 110 XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) | \ 111 XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) | \ 112 XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) | \ 113 XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) | \ 114 XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) | \ 115 XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) | \ 116 XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) | \ 117 XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) | \ 118 XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) | \ 119 XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \ 120 XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \ 121 XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \ 122 XCHAL_OPTION(XCHAL_HAVE_DFPU, XTENSA_OPTION_DFP_COPROCESSOR) | \ 123 XCHAL_OPTION(XCHAL_HAVE_DFPU_SINGLE_ONLY, \ 124 XTENSA_OPTION_DFPU_SINGLE_ONLY) | \ 125 XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \ 126 XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \ 127 XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000) || \ 128 XCHAL_HAVE_EXCLUSIVE), XTENSA_OPTION_ATOMCTL) | \ 129 XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \ 130 /* Interrupts and exceptions */ \ 131 XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \ 132 XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \ 133 XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \ 134 XTENSA_OPTION_UNALIGNED_EXCEPTION) | \ 135 XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) | \ 136 XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \ 137 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) | \ 138 XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \ 139 /* Local memory, TODO */ \ 140 XCHAL_OPTION(XCHAL_ICACHE_SIZE, XTENSA_OPTION_ICACHE) | \ 141 XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \ 142 XTENSA_OPTION_ICACHE_INDEX_LOCK) | \ 143 XCHAL_OPTION(XCHAL_DCACHE_SIZE, XTENSA_OPTION_DCACHE) | \ 144 XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \ 145 XTENSA_OPTION_DCACHE_INDEX_LOCK) | \ 146 XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \ 147 XCHAL_OPTION(XCHAL_HAVE_MEM_ECC_PARITY, \ 148 XTENSA_OPTION_MEMORY_ECC_PARITY) | \ 149 /* Memory protection and translation */ \ 150 XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \ 151 XTENSA_OPTION_REGION_PROTECTION) | \ 152 XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \ 153 XTENSA_OPTION_REGION_TRANSLATION) | \ 154 XCHAL_OPTION(XCHAL_HAVE_MPU, XTENSA_OPTION_MPU) | \ 155 XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \ 156 XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) | \ 157 /* Other, TODO */ \ 158 XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \ 159 XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) |\ 160 XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) | \ 161 XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) | \ 162 XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID) | \ 163 XCHAL_OPTION(XCHAL_HAVE_EXTERN_REGS, XTENSA_OPTION_EXTERN_REGS)) 164 165#ifndef XCHAL_WINDOW_OF4_VECOFS 166#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 167#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 168#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 169#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 170#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 171#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 172#endif 173 174#if XCHAL_HAVE_WINDOWED 175#define WINDOW_VECTORS \ 176 [EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \ 177 XCHAL_WINDOW_VECTORS_VADDR, \ 178 [EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \ 179 XCHAL_WINDOW_VECTORS_VADDR, \ 180 [EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \ 181 XCHAL_WINDOW_VECTORS_VADDR, \ 182 [EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \ 183 XCHAL_WINDOW_VECTORS_VADDR, \ 184 [EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \ 185 XCHAL_WINDOW_VECTORS_VADDR, \ 186 [EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \ 187 XCHAL_WINDOW_VECTORS_VADDR, 188#else 189#define WINDOW_VECTORS 190#endif 191 192#define EXCEPTION_VECTORS { \ 193 [EXC_RESET0] = XCHAL_RESET_VECTOR0_VADDR, \ 194 [EXC_RESET1] = XCHAL_RESET_VECTOR1_VADDR, \ 195 WINDOW_VECTORS \ 196 [EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \ 197 [EXC_USER] = XCHAL_USER_VECTOR_VADDR, \ 198 [EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \ 199 [EXC_DEBUG] = XCHAL_DEBUG_VECTOR_VADDR, \ 200 } 201 202#define INTERRUPT_VECTORS { \ 203 0, \ 204 0, \ 205 XCHAL_INTLEVEL2_VECTOR_VADDR, \ 206 XCHAL_INTLEVEL3_VECTOR_VADDR, \ 207 XCHAL_INTLEVEL4_VECTOR_VADDR, \ 208 XCHAL_INTLEVEL5_VECTOR_VADDR, \ 209 XCHAL_INTLEVEL6_VECTOR_VADDR, \ 210 XCHAL_INTLEVEL7_VECTOR_VADDR, \ 211 } 212 213#define LEVEL_MASKS { \ 214 [1] = XCHAL_INTLEVEL1_MASK, \ 215 [2] = XCHAL_INTLEVEL2_MASK, \ 216 [3] = XCHAL_INTLEVEL3_MASK, \ 217 [4] = XCHAL_INTLEVEL4_MASK, \ 218 [5] = XCHAL_INTLEVEL5_MASK, \ 219 [6] = XCHAL_INTLEVEL6_MASK, \ 220 [7] = XCHAL_INTLEVEL7_MASK, \ 221 } 222 223#define INTTYPE_MASKS { \ 224 [INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \ 225 [INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \ 226 [INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \ 227 } 228 229#define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL 230#define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE 231#define XTHAL_INTTYPE_NMI INTTYPE_NMI 232#define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE 233#define XTHAL_INTTYPE_TIMER INTTYPE_TIMER 234#define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG 235#define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR 236#define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR 237#define XTHAL_INTTYPE_PROFILING INTTYPE_PROFILING 238#define XTHAL_INTTYPE_IDMA_DONE INTTYPE_IDMA_DONE 239#define XTHAL_INTTYPE_IDMA_ERR INTTYPE_IDMA_ERR 240#define XTHAL_INTTYPE_GS_ERR INTTYPE_GS_ERR 241 242#ifndef XCHAL_NMILEVEL 243#define XCHAL_NMILEVEL (XCHAL_NUM_INTLEVELS + 1) 244#endif 245 246#define INTERRUPT(i) { \ 247 .level = XCHAL_INT ## i ## _LEVEL, \ 248 .inttype = XCHAL_INT ## i ## _TYPE, \ 249 } 250 251#define INTERRUPTS { \ 252 [0] = INTERRUPT(0), \ 253 [1] = INTERRUPT(1), \ 254 [2] = INTERRUPT(2), \ 255 [3] = INTERRUPT(3), \ 256 [4] = INTERRUPT(4), \ 257 [5] = INTERRUPT(5), \ 258 [6] = INTERRUPT(6), \ 259 [7] = INTERRUPT(7), \ 260 [8] = INTERRUPT(8), \ 261 [9] = INTERRUPT(9), \ 262 [10] = INTERRUPT(10), \ 263 [11] = INTERRUPT(11), \ 264 [12] = INTERRUPT(12), \ 265 [13] = INTERRUPT(13), \ 266 [14] = INTERRUPT(14), \ 267 [15] = INTERRUPT(15), \ 268 [16] = INTERRUPT(16), \ 269 [17] = INTERRUPT(17), \ 270 [18] = INTERRUPT(18), \ 271 [19] = INTERRUPT(19), \ 272 [20] = INTERRUPT(20), \ 273 [21] = INTERRUPT(21), \ 274 [22] = INTERRUPT(22), \ 275 [23] = INTERRUPT(23), \ 276 [24] = INTERRUPT(24), \ 277 [25] = INTERRUPT(25), \ 278 [26] = INTERRUPT(26), \ 279 [27] = INTERRUPT(27), \ 280 [28] = INTERRUPT(28), \ 281 [29] = INTERRUPT(29), \ 282 [30] = INTERRUPT(30), \ 283 [31] = INTERRUPT(31), \ 284 } 285 286#define TIMERINTS { \ 287 [0] = XCHAL_TIMER0_INTERRUPT, \ 288 [1] = XCHAL_TIMER1_INTERRUPT, \ 289 [2] = XCHAL_TIMER2_INTERRUPT, \ 290 } 291 292#define EXTINTS { \ 293 [0] = XCHAL_EXTINT0_NUM, \ 294 [1] = XCHAL_EXTINT1_NUM, \ 295 [2] = XCHAL_EXTINT2_NUM, \ 296 [3] = XCHAL_EXTINT3_NUM, \ 297 [4] = XCHAL_EXTINT4_NUM, \ 298 [5] = XCHAL_EXTINT5_NUM, \ 299 [6] = XCHAL_EXTINT6_NUM, \ 300 [7] = XCHAL_EXTINT7_NUM, \ 301 [8] = XCHAL_EXTINT8_NUM, \ 302 [9] = XCHAL_EXTINT9_NUM, \ 303 [10] = XCHAL_EXTINT10_NUM, \ 304 [11] = XCHAL_EXTINT11_NUM, \ 305 [12] = XCHAL_EXTINT12_NUM, \ 306 [13] = XCHAL_EXTINT13_NUM, \ 307 [14] = XCHAL_EXTINT14_NUM, \ 308 [15] = XCHAL_EXTINT15_NUM, \ 309 [16] = XCHAL_EXTINT16_NUM, \ 310 [17] = XCHAL_EXTINT17_NUM, \ 311 [18] = XCHAL_EXTINT18_NUM, \ 312 [19] = XCHAL_EXTINT19_NUM, \ 313 [20] = XCHAL_EXTINT20_NUM, \ 314 [21] = XCHAL_EXTINT21_NUM, \ 315 [22] = XCHAL_EXTINT22_NUM, \ 316 [23] = XCHAL_EXTINT23_NUM, \ 317 [24] = XCHAL_EXTINT24_NUM, \ 318 [25] = XCHAL_EXTINT25_NUM, \ 319 [26] = XCHAL_EXTINT26_NUM, \ 320 [27] = XCHAL_EXTINT27_NUM, \ 321 [28] = XCHAL_EXTINT28_NUM, \ 322 [29] = XCHAL_EXTINT29_NUM, \ 323 [30] = XCHAL_EXTINT30_NUM, \ 324 [31] = XCHAL_EXTINT31_NUM, \ 325 } 326 327#define EXCEPTIONS_SECTION \ 328 .excm_level = XCHAL_EXCM_LEVEL, \ 329 .vecbase = XCHAL_VECBASE_RESET_VADDR, \ 330 .exception_vector = EXCEPTION_VECTORS 331 332#define INTERRUPTS_SECTION \ 333 .ninterrupt = XCHAL_NUM_INTERRUPTS, \ 334 .nlevel = XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI, \ 335 .nmi_level = XCHAL_NMILEVEL, \ 336 .interrupt_vector = INTERRUPT_VECTORS, \ 337 .level_mask = LEVEL_MASKS, \ 338 .inttype_mask = INTTYPE_MASKS, \ 339 .interrupt = INTERRUPTS, \ 340 .nccompare = XCHAL_NUM_TIMERS, \ 341 .timerint = TIMERINTS, \ 342 .nextint = XCHAL_NUM_EXTINTERRUPTS, \ 343 .extint = EXTINTS 344 345#if XCHAL_HAVE_PTP_MMU 346 347#define TLB_TEMPLATE(ways, refill_way_size, way56) { \ 348 .nways = ways, \ 349 .way_size = { \ 350 (refill_way_size), (refill_way_size), \ 351 (refill_way_size), (refill_way_size), \ 352 4, (way56) ? 4 : 2, (way56) ? 8 : 2, 1, 1, 1, \ 353 }, \ 354 .varway56 = (way56), \ 355 .nrefillentries = (refill_way_size) * 4, \ 356 } 357 358#define ITLB(varway56) \ 359 TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56) 360 361#define DTLB(varway56) \ 362 TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56) 363 364#define TLB_SECTION \ 365 .itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \ 366 .dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY) 367 368#ifndef XCHAL_SYSROM0_PADDR 369#define XCHAL_SYSROM0_PADDR 0xfe000000 370#define XCHAL_SYSROM0_SIZE 0x02000000 371#endif 372 373#ifndef XCHAL_SYSRAM0_PADDR 374#define XCHAL_SYSRAM0_PADDR 0x00000000 375#define XCHAL_SYSRAM0_SIZE 0x08000000 376#endif 377 378#elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR 379 380#define TLB_TEMPLATE { \ 381 .nways = 1, \ 382 .way_size = { \ 383 8, \ 384 } \ 385 } 386 387#define TLB_SECTION \ 388 .itlb = TLB_TEMPLATE, \ 389 .dtlb = TLB_TEMPLATE 390 391#ifndef XCHAL_SYSROM0_PADDR 392#define XCHAL_SYSROM0_PADDR 0x50000000 393#define XCHAL_SYSROM0_SIZE 0x04000000 394#endif 395 396#ifndef XCHAL_SYSRAM0_PADDR 397#define XCHAL_SYSRAM0_PADDR 0x60000000 398#define XCHAL_SYSRAM0_SIZE 0x04000000 399#endif 400 401#elif XCHAL_HAVE_MPU 402 403#ifndef XTENSA_MPU_BG_MAP 404#ifdef XCHAL_MPU_BACKGROUND_MAP 405#define XCHAL_MPU_BGMAP(s, vaddr_start, vaddr_last, rights, memtype, x...) \ 406 { .vaddr = (vaddr_start), .attr = ((rights) << 8) | ((memtype) << 12), }, 407 408#define XTENSA_MPU_BG_MAP (xtensa_mpu_entry []){\ 409 XCHAL_MPU_BACKGROUND_MAP(0) \ 410} 411 412#define XTENSA_MPU_BG_MAP_ENTRIES XCHAL_MPU_BACKGROUND_ENTRIES 413#else 414#define XTENSA_MPU_BG_MAP (xtensa_mpu_entry []){\ 415 { .vaddr = 0, .attr = 0x00006700, }, \ 416} 417 418#define XTENSA_MPU_BG_MAP_ENTRIES 1 419#endif 420#endif 421 422#define TLB_SECTION \ 423 .mpu_align = XCHAL_MPU_ALIGN, \ 424 .n_mpu_fg_segments = XCHAL_MPU_ENTRIES, \ 425 .n_mpu_bg_segments = XTENSA_MPU_BG_MAP_ENTRIES, \ 426 .mpu_bg = XTENSA_MPU_BG_MAP 427 428#ifndef XCHAL_SYSROM0_PADDR 429#define XCHAL_SYSROM0_PADDR 0x50000000 430#define XCHAL_SYSROM0_SIZE 0x04000000 431#endif 432 433#ifndef XCHAL_SYSRAM0_PADDR 434#define XCHAL_SYSRAM0_PADDR 0x60000000 435#define XCHAL_SYSRAM0_SIZE 0x04000000 436#endif 437 438#else 439 440#ifndef XCHAL_SYSROM0_PADDR 441#define XCHAL_SYSROM0_PADDR 0x50000000 442#define XCHAL_SYSROM0_SIZE 0x04000000 443#endif 444 445#ifndef XCHAL_SYSRAM0_PADDR 446#define XCHAL_SYSRAM0_PADDR 0x60000000 447#define XCHAL_SYSRAM0_SIZE 0x04000000 448#endif 449 450#endif 451 452#if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0) 453#define REGISTER_CORE(core) \ 454 static void __attribute__((constructor)) register_core(void) \ 455 { \ 456 static XtensaConfigList node = { \ 457 .config = &core, \ 458 }; \ 459 xtensa_register_core(&node); \ 460 } 461#else 462#define REGISTER_CORE(core) 463#endif 464 465#define DEBUG_SECTION \ 466 .debug_level = XCHAL_DEBUGLEVEL, \ 467 .nibreak = XCHAL_NUM_IBREAK, \ 468 .ndbreak = XCHAL_NUM_DBREAK 469 470#define CACHE_SECTION \ 471 .icache_ways = XCHAL_ICACHE_WAYS, \ 472 .dcache_ways = XCHAL_DCACHE_WAYS, \ 473 .dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \ 474 .memctl_mask = \ 475 (XCHAL_ICACHE_SIZE ? MEMCTL_IUSEWAYS_MASK : 0) | \ 476 (XCHAL_DCACHE_SIZE ? \ 477 MEMCTL_DALLOCWAYS_MASK | MEMCTL_DUSEWAYS_MASK : 0) | \ 478 MEMCTL_ISNP | MEMCTL_DSNP | \ 479 (XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE ? MEMCTL_IL0EN : 0) 480 481#define MEM_LOCATION(name, n) \ 482 { \ 483 .addr = XCHAL_ ## name ## n ## _PADDR, \ 484 .size = XCHAL_ ## name ## n ## _SIZE, \ 485 } 486 487#define MEM_SECTIONS(name) \ 488 MEM_LOCATION(name, 0), \ 489 MEM_LOCATION(name, 1), \ 490 MEM_LOCATION(name, 2), \ 491 MEM_LOCATION(name, 3) 492 493#define MEM_SECTION(name) \ 494 .num = XCHAL_NUM_ ## name, \ 495 .location = { \ 496 MEM_SECTIONS(name) \ 497 } 498 499#define SYSMEM_SECTION(name) \ 500 .num = 1, \ 501 .location = { \ 502 { \ 503 .addr = XCHAL_ ## name ## 0_PADDR, \ 504 .size = XCHAL_ ## name ## 0_SIZE, \ 505 } \ 506 } 507 508#define LOCAL_MEMORIES_SECTION \ 509 .instrom = { \ 510 MEM_SECTION(INSTROM) \ 511 }, \ 512 .instram = { \ 513 MEM_SECTION(INSTRAM) \ 514 }, \ 515 .datarom = { \ 516 MEM_SECTION(DATAROM) \ 517 }, \ 518 .dataram = { \ 519 MEM_SECTION(DATARAM) \ 520 }, \ 521 .sysrom = { \ 522 SYSMEM_SECTION(SYSROM) \ 523 }, \ 524 .sysram = { \ 525 SYSMEM_SECTION(SYSRAM) \ 526 } 527 528#define CONFIG_SECTION \ 529 .hw_version = XCHAL_HW_VERSION, \ 530 .configid = { \ 531 XCHAL_HW_CONFIGID0, \ 532 XCHAL_HW_CONFIGID1, \ 533 } 534 535#define DEFAULT_SECTIONS \ 536 .options = XTENSA_OPTIONS, \ 537 .nareg = XCHAL_NUM_AREGS, \ 538 .ndepc = (XCHAL_XEA_VERSION >= 2), \ 539 .inst_fetch_width = XCHAL_INST_FETCH_WIDTH, \ 540 .max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \ 541 .use_first_nan = !XCHAL_HAVE_DFPU, \ 542 EXCEPTIONS_SECTION, \ 543 INTERRUPTS_SECTION, \ 544 TLB_SECTION, \ 545 DEBUG_SECTION, \ 546 CACHE_SECTION, \ 547 LOCAL_MEMORIES_SECTION, \ 548 CONFIG_SECTION 549 550 551#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2 552#define XCHAL_INTLEVEL2_VECTOR_VADDR 0 553#endif 554#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3 555#define XCHAL_INTLEVEL3_VECTOR_VADDR 0 556#endif 557#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4 558#define XCHAL_INTLEVEL4_VECTOR_VADDR 0 559#endif 560#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5 561#define XCHAL_INTLEVEL5_VECTOR_VADDR 0 562#endif 563#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6 564#define XCHAL_INTLEVEL6_VECTOR_VADDR 0 565#endif 566#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7 567#define XCHAL_INTLEVEL7_VECTOR_VADDR 0 568#endif 569 570 571#if XCHAL_NUM_INTERRUPTS <= 0 572#define XCHAL_INT0_LEVEL 0 573#define XCHAL_INT0_TYPE 0 574#endif 575#if XCHAL_NUM_INTERRUPTS <= 1 576#define XCHAL_INT1_LEVEL 0 577#define XCHAL_INT1_TYPE 0 578#endif 579#if XCHAL_NUM_INTERRUPTS <= 2 580#define XCHAL_INT2_LEVEL 0 581#define XCHAL_INT2_TYPE 0 582#endif 583#if XCHAL_NUM_INTERRUPTS <= 3 584#define XCHAL_INT3_LEVEL 0 585#define XCHAL_INT3_TYPE 0 586#endif 587#if XCHAL_NUM_INTERRUPTS <= 4 588#define XCHAL_INT4_LEVEL 0 589#define XCHAL_INT4_TYPE 0 590#endif 591#if XCHAL_NUM_INTERRUPTS <= 5 592#define XCHAL_INT5_LEVEL 0 593#define XCHAL_INT5_TYPE 0 594#endif 595#if XCHAL_NUM_INTERRUPTS <= 6 596#define XCHAL_INT6_LEVEL 0 597#define XCHAL_INT6_TYPE 0 598#endif 599#if XCHAL_NUM_INTERRUPTS <= 7 600#define XCHAL_INT7_LEVEL 0 601#define XCHAL_INT7_TYPE 0 602#endif 603#if XCHAL_NUM_INTERRUPTS <= 8 604#define XCHAL_INT8_LEVEL 0 605#define XCHAL_INT8_TYPE 0 606#endif 607#if XCHAL_NUM_INTERRUPTS <= 9 608#define XCHAL_INT9_LEVEL 0 609#define XCHAL_INT9_TYPE 0 610#endif 611#if XCHAL_NUM_INTERRUPTS <= 10 612#define XCHAL_INT10_LEVEL 0 613#define XCHAL_INT10_TYPE 0 614#endif 615#if XCHAL_NUM_INTERRUPTS <= 11 616#define XCHAL_INT11_LEVEL 0 617#define XCHAL_INT11_TYPE 0 618#endif 619#if XCHAL_NUM_INTERRUPTS <= 12 620#define XCHAL_INT12_LEVEL 0 621#define XCHAL_INT12_TYPE 0 622#endif 623#if XCHAL_NUM_INTERRUPTS <= 13 624#define XCHAL_INT13_LEVEL 0 625#define XCHAL_INT13_TYPE 0 626#endif 627#if XCHAL_NUM_INTERRUPTS <= 14 628#define XCHAL_INT14_LEVEL 0 629#define XCHAL_INT14_TYPE 0 630#endif 631#if XCHAL_NUM_INTERRUPTS <= 15 632#define XCHAL_INT15_LEVEL 0 633#define XCHAL_INT15_TYPE 0 634#endif 635#if XCHAL_NUM_INTERRUPTS <= 16 636#define XCHAL_INT16_LEVEL 0 637#define XCHAL_INT16_TYPE 0 638#endif 639#if XCHAL_NUM_INTERRUPTS <= 17 640#define XCHAL_INT17_LEVEL 0 641#define XCHAL_INT17_TYPE 0 642#endif 643#if XCHAL_NUM_INTERRUPTS <= 18 644#define XCHAL_INT18_LEVEL 0 645#define XCHAL_INT18_TYPE 0 646#endif 647#if XCHAL_NUM_INTERRUPTS <= 19 648#define XCHAL_INT19_LEVEL 0 649#define XCHAL_INT19_TYPE 0 650#endif 651#if XCHAL_NUM_INTERRUPTS <= 20 652#define XCHAL_INT20_LEVEL 0 653#define XCHAL_INT20_TYPE 0 654#endif 655#if XCHAL_NUM_INTERRUPTS <= 21 656#define XCHAL_INT21_LEVEL 0 657#define XCHAL_INT21_TYPE 0 658#endif 659#if XCHAL_NUM_INTERRUPTS <= 22 660#define XCHAL_INT22_LEVEL 0 661#define XCHAL_INT22_TYPE 0 662#endif 663#if XCHAL_NUM_INTERRUPTS <= 23 664#define XCHAL_INT23_LEVEL 0 665#define XCHAL_INT23_TYPE 0 666#endif 667#if XCHAL_NUM_INTERRUPTS <= 24 668#define XCHAL_INT24_LEVEL 0 669#define XCHAL_INT24_TYPE 0 670#endif 671#if XCHAL_NUM_INTERRUPTS <= 25 672#define XCHAL_INT25_LEVEL 0 673#define XCHAL_INT25_TYPE 0 674#endif 675#if XCHAL_NUM_INTERRUPTS <= 26 676#define XCHAL_INT26_LEVEL 0 677#define XCHAL_INT26_TYPE 0 678#endif 679#if XCHAL_NUM_INTERRUPTS <= 27 680#define XCHAL_INT27_LEVEL 0 681#define XCHAL_INT27_TYPE 0 682#endif 683#if XCHAL_NUM_INTERRUPTS <= 28 684#define XCHAL_INT28_LEVEL 0 685#define XCHAL_INT28_TYPE 0 686#endif 687#if XCHAL_NUM_INTERRUPTS <= 29 688#define XCHAL_INT29_LEVEL 0 689#define XCHAL_INT29_TYPE 0 690#endif 691#if XCHAL_NUM_INTERRUPTS <= 30 692#define XCHAL_INT30_LEVEL 0 693#define XCHAL_INT30_TYPE 0 694#endif 695#if XCHAL_NUM_INTERRUPTS <= 31 696#define XCHAL_INT31_LEVEL 0 697#define XCHAL_INT31_TYPE 0 698#endif 699 700 701#if XCHAL_NUM_EXTINTERRUPTS <= 0 702#define XCHAL_EXTINT0_NUM 0 703#endif 704#if XCHAL_NUM_EXTINTERRUPTS <= 1 705#define XCHAL_EXTINT1_NUM 0 706#endif 707#if XCHAL_NUM_EXTINTERRUPTS <= 2 708#define XCHAL_EXTINT2_NUM 0 709#endif 710#if XCHAL_NUM_EXTINTERRUPTS <= 3 711#define XCHAL_EXTINT3_NUM 0 712#endif 713#if XCHAL_NUM_EXTINTERRUPTS <= 4 714#define XCHAL_EXTINT4_NUM 0 715#endif 716#if XCHAL_NUM_EXTINTERRUPTS <= 5 717#define XCHAL_EXTINT5_NUM 0 718#endif 719#if XCHAL_NUM_EXTINTERRUPTS <= 6 720#define XCHAL_EXTINT6_NUM 0 721#endif 722#if XCHAL_NUM_EXTINTERRUPTS <= 7 723#define XCHAL_EXTINT7_NUM 0 724#endif 725#if XCHAL_NUM_EXTINTERRUPTS <= 8 726#define XCHAL_EXTINT8_NUM 0 727#endif 728#if XCHAL_NUM_EXTINTERRUPTS <= 9 729#define XCHAL_EXTINT9_NUM 0 730#endif 731#if XCHAL_NUM_EXTINTERRUPTS <= 10 732#define XCHAL_EXTINT10_NUM 0 733#endif 734#if XCHAL_NUM_EXTINTERRUPTS <= 11 735#define XCHAL_EXTINT11_NUM 0 736#endif 737#if XCHAL_NUM_EXTINTERRUPTS <= 12 738#define XCHAL_EXTINT12_NUM 0 739#endif 740#if XCHAL_NUM_EXTINTERRUPTS <= 13 741#define XCHAL_EXTINT13_NUM 0 742#endif 743#if XCHAL_NUM_EXTINTERRUPTS <= 14 744#define XCHAL_EXTINT14_NUM 0 745#endif 746#if XCHAL_NUM_EXTINTERRUPTS <= 15 747#define XCHAL_EXTINT15_NUM 0 748#endif 749#if XCHAL_NUM_EXTINTERRUPTS <= 16 750#define XCHAL_EXTINT16_NUM 0 751#endif 752#if XCHAL_NUM_EXTINTERRUPTS <= 17 753#define XCHAL_EXTINT17_NUM 0 754#endif 755#if XCHAL_NUM_EXTINTERRUPTS <= 18 756#define XCHAL_EXTINT18_NUM 0 757#endif 758#if XCHAL_NUM_EXTINTERRUPTS <= 19 759#define XCHAL_EXTINT19_NUM 0 760#endif 761#if XCHAL_NUM_EXTINTERRUPTS <= 20 762#define XCHAL_EXTINT20_NUM 0 763#endif 764#if XCHAL_NUM_EXTINTERRUPTS <= 21 765#define XCHAL_EXTINT21_NUM 0 766#endif 767#if XCHAL_NUM_EXTINTERRUPTS <= 22 768#define XCHAL_EXTINT22_NUM 0 769#endif 770#if XCHAL_NUM_EXTINTERRUPTS <= 23 771#define XCHAL_EXTINT23_NUM 0 772#endif 773#if XCHAL_NUM_EXTINTERRUPTS <= 24 774#define XCHAL_EXTINT24_NUM 0 775#endif 776#if XCHAL_NUM_EXTINTERRUPTS <= 25 777#define XCHAL_EXTINT25_NUM 0 778#endif 779#if XCHAL_NUM_EXTINTERRUPTS <= 26 780#define XCHAL_EXTINT26_NUM 0 781#endif 782#if XCHAL_NUM_EXTINTERRUPTS <= 27 783#define XCHAL_EXTINT27_NUM 0 784#endif 785#if XCHAL_NUM_EXTINTERRUPTS <= 28 786#define XCHAL_EXTINT28_NUM 0 787#endif 788#if XCHAL_NUM_EXTINTERRUPTS <= 29 789#define XCHAL_EXTINT29_NUM 0 790#endif 791#if XCHAL_NUM_EXTINTERRUPTS <= 30 792#define XCHAL_EXTINT30_NUM 0 793#endif 794#if XCHAL_NUM_EXTINTERRUPTS <= 31 795#define XCHAL_EXTINT31_NUM 0 796#endif 797 798 799#define XTHAL_TIMER_UNCONFIGURED 0 800 801#if XCHAL_NUM_INSTROM < 1 802#define XCHAL_INSTROM0_PADDR 0 803#define XCHAL_INSTROM0_SIZE 0 804#endif 805#if XCHAL_NUM_INSTROM < 2 806#define XCHAL_INSTROM1_PADDR 0 807#define XCHAL_INSTROM1_SIZE 0 808#endif 809#if XCHAL_NUM_INSTROM < 3 810#define XCHAL_INSTROM2_PADDR 0 811#define XCHAL_INSTROM2_SIZE 0 812#endif 813#if XCHAL_NUM_INSTROM < 4 814#define XCHAL_INSTROM3_PADDR 0 815#define XCHAL_INSTROM3_SIZE 0 816#endif 817#if XCHAL_NUM_INSTROM > MAX_NMEMORY 818#error XCHAL_NUM_INSTROM > MAX_NMEMORY 819#endif 820 821#if XCHAL_NUM_INSTRAM < 1 822#define XCHAL_INSTRAM0_PADDR 0 823#define XCHAL_INSTRAM0_SIZE 0 824#endif 825#if XCHAL_NUM_INSTRAM < 2 826#define XCHAL_INSTRAM1_PADDR 0 827#define XCHAL_INSTRAM1_SIZE 0 828#endif 829#if XCHAL_NUM_INSTRAM < 3 830#define XCHAL_INSTRAM2_PADDR 0 831#define XCHAL_INSTRAM2_SIZE 0 832#endif 833#if XCHAL_NUM_INSTRAM < 4 834#define XCHAL_INSTRAM3_PADDR 0 835#define XCHAL_INSTRAM3_SIZE 0 836#endif 837#if XCHAL_NUM_INSTRAM > MAX_NMEMORY 838#error XCHAL_NUM_INSTRAM > MAX_NMEMORY 839#endif 840 841#if XCHAL_NUM_DATAROM < 1 842#define XCHAL_DATAROM0_PADDR 0 843#define XCHAL_DATAROM0_SIZE 0 844#endif 845#if XCHAL_NUM_DATAROM < 2 846#define XCHAL_DATAROM1_PADDR 0 847#define XCHAL_DATAROM1_SIZE 0 848#endif 849#if XCHAL_NUM_DATAROM < 3 850#define XCHAL_DATAROM2_PADDR 0 851#define XCHAL_DATAROM2_SIZE 0 852#endif 853#if XCHAL_NUM_DATAROM < 4 854#define XCHAL_DATAROM3_PADDR 0 855#define XCHAL_DATAROM3_SIZE 0 856#endif 857#if XCHAL_NUM_DATAROM > MAX_NMEMORY 858#error XCHAL_NUM_DATAROM > MAX_NMEMORY 859#endif 860 861#if XCHAL_NUM_DATARAM < 1 862#define XCHAL_DATARAM0_PADDR 0 863#define XCHAL_DATARAM0_SIZE 0 864#endif 865#if XCHAL_NUM_DATARAM < 2 866#define XCHAL_DATARAM1_PADDR 0 867#define XCHAL_DATARAM1_SIZE 0 868#endif 869#if XCHAL_NUM_DATARAM < 3 870#define XCHAL_DATARAM2_PADDR 0 871#define XCHAL_DATARAM2_SIZE 0 872#endif 873#if XCHAL_NUM_DATARAM < 4 874#define XCHAL_DATARAM3_PADDR 0 875#define XCHAL_DATARAM3_SIZE 0 876#endif 877#if XCHAL_NUM_DATARAM > MAX_NMEMORY 878#error XCHAL_NUM_DATARAM > MAX_NMEMORY 879#endif