cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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tcg-target-con-set.h (965B)

      1/* SPDX-License-Identifier: MIT */
      2/*
      3 * Define Arm target-specific constraint sets.
      4 * Copyright (c) 2021 Linaro
      5 */
      6
      7/*
      8 * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
      9 * Each operand should be a sequence of constraint letters as defined by
     10 * tcg-target-con-str.h; the constraint combination is inclusive or.
     11 */
     12C_O0_I1(r)
     13C_O0_I2(r, r)
     14C_O0_I2(r, rIN)
     15C_O0_I2(s, s)
     16C_O0_I2(w, r)
     17C_O0_I3(s, s, s)
     18C_O0_I4(r, r, rI, rI)
     19C_O0_I4(s, s, s, s)
     20C_O1_I1(r, l)
     21C_O1_I1(r, r)
     22C_O1_I1(w, r)
     23C_O1_I1(w, w)
     24C_O1_I1(w, wr)
     25C_O1_I2(r, 0, rZ)
     26C_O1_I2(r, l, l)
     27C_O1_I2(r, r, r)
     28C_O1_I2(r, r, rI)
     29C_O1_I2(r, r, rIK)
     30C_O1_I2(r, r, rIN)
     31C_O1_I2(r, r, ri)
     32C_O1_I2(r, rZ, rZ)
     33C_O1_I2(w, 0, w)
     34C_O1_I2(w, w, w)
     35C_O1_I2(w, w, wO)
     36C_O1_I2(w, w, wV)
     37C_O1_I2(w, w, wZ)
     38C_O1_I3(w, w, w, w)
     39C_O1_I4(r, r, r, rI, rI)
     40C_O1_I4(r, r, rIN, rIK, 0)
     41C_O2_I1(r, r, l)
     42C_O2_I2(r, r, l, l)
     43C_O2_I2(r, r, r, r)
     44C_O2_I4(r, r, r, r, rIN, rIK)
     45C_O2_I4(r, r, rI, rI, rIN, rIK)