cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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tcg-target-con-str.h (587B)

      1/* SPDX-License-Identifier: MIT */
      2/*
      3 * Define Arm target-specific operand constraints.
      4 * Copyright (c) 2021 Linaro
      5 */
      6
      7/*
      8 * Define constraint letters for register sets:
      9 * REGS(letter, register_mask)
     10 */
     11REGS('r', ALL_GENERAL_REGS)
     12REGS('l', ALL_QLOAD_REGS)
     13REGS('s', ALL_QSTORE_REGS)
     14REGS('w', ALL_VECTOR_REGS)
     15
     16/*
     17 * Define constraint letters for constants:
     18 * CONST(letter, TCG_CT_CONST_* bit set)
     19 */
     20CONST('I', TCG_CT_CONST_ARM)
     21CONST('K', TCG_CT_CONST_INV)
     22CONST('N', TCG_CT_CONST_NEG)
     23CONST('O', TCG_CT_CONST_ORRI)
     24CONST('V', TCG_CT_CONST_ANDI)
     25CONST('Z', TCG_CT_CONST_ZERO)