cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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tcg-target-con-set.h (1184B)

      1/* SPDX-License-Identifier: MIT */
      2/*
      3 * Define i386 target-specific constraint sets.
      4 * Copyright (c) 2021 Linaro
      5 */
      6
      7/*
      8 * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
      9 * Each operand should be a sequence of constraint letters as defined by
     10 * tcg-target-con-str.h; the constraint combination is inclusive or.
     11 *
     12 * C_N1_Im(...) defines a constraint set with 1 output and <m> inputs,
     13 * except that the output must use a new register.
     14 */
     15C_O0_I1(r)
     16C_O0_I2(L, L)
     17C_O0_I2(qi, r)
     18C_O0_I2(re, r)
     19C_O0_I2(ri, r)
     20C_O0_I2(r, re)
     21C_O0_I2(s, L)
     22C_O0_I2(x, r)
     23C_O0_I3(L, L, L)
     24C_O0_I3(s, L, L)
     25C_O0_I4(L, L, L, L)
     26C_O0_I4(r, r, ri, ri)
     27C_O1_I1(r, 0)
     28C_O1_I1(r, L)
     29C_O1_I1(r, q)
     30C_O1_I1(r, r)
     31C_O1_I1(x, r)
     32C_O1_I1(x, x)
     33C_O1_I2(Q, 0, Q)
     34C_O1_I2(q, r, re)
     35C_O1_I2(r, 0, ci)
     36C_O1_I2(r, 0, r)
     37C_O1_I2(r, 0, re)
     38C_O1_I2(r, 0, reZ)
     39C_O1_I2(r, 0, ri)
     40C_O1_I2(r, 0, rI)
     41C_O1_I2(r, L, L)
     42C_O1_I2(r, r, re)
     43C_O1_I2(r, r, ri)
     44C_O1_I2(r, r, rI)
     45C_O1_I2(x, x, x)
     46C_N1_I2(r, r, r)
     47C_N1_I2(r, r, rW)
     48C_O1_I3(x, x, x, x)
     49C_O1_I4(r, r, re, r, 0)
     50C_O1_I4(r, r, r, ri, ri)
     51C_O2_I1(r, r, L)
     52C_O2_I2(a, d, a, r)
     53C_O2_I2(r, r, L, L)
     54C_O2_I3(a, d, 0, 1, r)
     55C_O2_I4(r, r, 0, 1, re, re)