cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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tcg-target-con-set.h (816B)

      1/* SPDX-License-Identifier: MIT */
      2/*
      3 * Define MIPS target-specific constraint sets.
      4 * Copyright (c) 2021 Linaro
      5 */
      6
      7/*
      8 * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
      9 * Each operand should be a sequence of constraint letters as defined by
     10 * tcg-target-con-str.h; the constraint combination is inclusive or.
     11 */
     12C_O0_I1(r)
     13C_O0_I2(rZ, r)
     14C_O0_I2(rZ, rZ)
     15C_O0_I2(SZ, S)
     16C_O0_I3(SZ, S, S)
     17C_O0_I3(SZ, SZ, S)
     18C_O0_I4(rZ, rZ, rZ, rZ)
     19C_O0_I4(SZ, SZ, S, S)
     20C_O1_I1(r, L)
     21C_O1_I1(r, r)
     22C_O1_I2(r, 0, rZ)
     23C_O1_I2(r, L, L)
     24C_O1_I2(r, r, ri)
     25C_O1_I2(r, r, rI)
     26C_O1_I2(r, r, rIK)
     27C_O1_I2(r, r, rJ)
     28C_O1_I2(r, r, rWZ)
     29C_O1_I2(r, rZ, rN)
     30C_O1_I2(r, rZ, rZ)
     31C_O1_I4(r, rZ, rZ, rZ, 0)
     32C_O1_I4(r, rZ, rZ, rZ, rZ)
     33C_O2_I1(r, r, L)
     34C_O2_I2(r, r, L, L)
     35C_O2_I2(r, r, r, r)
     36C_O2_I4(r, r, rZ, rZ, rN, rN)