cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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tcg-target-con-str.h (749B)

      1/* SPDX-License-Identifier: MIT */
      2/*
      3 * Define S390 target-specific operand constraints.
      4 * Copyright (c) 2021 Linaro
      5 */
      6
      7/*
      8 * Define constraint letters for register sets:
      9 * REGS(letter, register_mask)
     10 */
     11REGS('r', ALL_GENERAL_REGS)
     12REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
     13REGS('v', ALL_VECTOR_REGS)
     14/*
     15 * A (single) even/odd pair for division.
     16 * TODO: Add something to the register allocator to allow
     17 * this kind of regno+1 pairing to be done more generally.
     18 */
     19REGS('a', 1u << TCG_REG_R2)
     20REGS('b', 1u << TCG_REG_R3)
     21
     22/*
     23 * Define constraint letters for constants:
     24 * CONST(letter, TCG_CT_CONST_* bit set)
     25 */
     26CONST('A', TCG_CT_CONST_S33)
     27CONST('I', TCG_CT_CONST_S16)
     28CONST('J', TCG_CT_CONST_S32)
     29CONST('Z', TCG_CT_CONST_ZERO)