cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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tcg-target-con-str.h (574B)

      1/* SPDX-License-Identifier: MIT */
      2/*
      3 * Define Sparc target-specific operand constraints.
      4 * Copyright (c) 2021 Linaro
      5 */
      6
      7/*
      8 * Define constraint letters for register sets:
      9 * REGS(letter, register_mask)
     10 */
     11REGS('r', ALL_GENERAL_REGS)
     12REGS('R', ALL_GENERAL_REGS64)
     13REGS('s', ALL_QLDST_REGS)
     14REGS('S', ALL_QLDST_REGS64)
     15REGS('A', TARGET_LONG_BITS == 64 ? ALL_QLDST_REGS64 : ALL_QLDST_REGS)
     16
     17/*
     18 * Define constraint letters for constants:
     19 * CONST(letter, TCG_CT_CONST_* bit set)
     20 */
     21CONST('I', TCG_CT_CONST_S11)
     22CONST('J', TCG_CT_CONST_S13)
     23CONST('Z', TCG_CT_CONST_ZERO)