cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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a-b-kernel.S (1826B)


      1#
      2# Copyright (c) 2018 Red Hat, Inc. and/or its affiliates
      3#
      4# Author:
      5#   Wei Huang <wei@redhat.com>
      6#
      7# This work is licensed under the terms of the GNU GPL, version 2 or later.
      8# See the COPYING file in the top-level directory.
      9#
     10# Note: Please make sure the compiler compiles the assembly code below with
     11# pc-relative address. Also the branch instructions should use relative
     12# addresses only.
     13
     14#include "../migration-test.h"
     15
     16.section .text
     17
     18        .globl  _start
     19
     20_start:
     21        /* disable MMU to use phys mem address */
     22        mrs     x0, sctlr_el1
     23        bic     x0, x0, #(1<<0)
     24        msr     sctlr_el1, x0
     25        isb
     26
     27        /* traverse test memory region */
     28        mov     x0, #ARM_TEST_MEM_START
     29        mov     x1, #ARM_TEST_MEM_END
     30
     31        /* output char 'A' to PL011 */
     32        mov     w3, 'A'
     33        mov     x2, #ARM_MACH_VIRT_UART
     34        strb    w3, [x2]
     35
     36        /* clean up memory */
     37        mov     w3, #0
     38        mov     x4, x0
     39clean:
     40        strb    w3, [x4]
     41        add     x4, x4, #TEST_MEM_PAGE_SIZE
     42        cmp     x4, x1
     43        ble     clean
     44
     45        /* w5 keeps a counter so we can limit the output speed */
     46        mov     w5, #0
     47
     48        /* main body */
     49mainloop:
     50        mov     x4, x0
     51
     52innerloop:
     53        /* increment the first byte of each page by 1 */
     54        ldrb    w3, [x4]
     55        add     w3, w3, #1
     56        and     w3, w3, #0xff
     57        strb    w3, [x4]
     58
     59        /* make sure QEMU user space can see consistent data as MMU is off */
     60        dc      civac, x4
     61
     62        add     x4, x4, #TEST_MEM_PAGE_SIZE
     63        cmp     x4, x1
     64        blt     innerloop
     65
     66        add     w5, w5, #1
     67        and     w5, w5, #0xff
     68        cmp     w5, #0
     69        bne     mainloop
     70
     71        /* output char 'B' to PL011 */
     72        mov     w3, 'B'
     73        strb    w3, [x2]
     74
     75        b       mainloop