cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

check_movmp.s (2223B)

      1# mach: crisv3 crisv8 crisv10 crisv32
      2# output: ffffff00\nffff0000\n0\nffffff00\nffff0000\n0\nffffff00\nffff0000\n0\nbb113344\n664433aa\ncc557788\nabcde012\nabcde000\n77880000\n0\n
      3
      4# Test generic "move Ps,[]" and "move [],Pd" insns; the ones with
      5# functionality common to all models.
      6
      7 .include "testutils.inc"
      8 start
      9
     10 .data
     11filler:
     12 .byte 0xaa
     13 .word 0x4433
     14 .dword 0x55778866
     15 .byte 0xcc
     16
     17 .text
     18; Test that writing to zero-registers is a nop
     19 .if 0
     20 ; We used to just ignore the writes, but now an error is emitted.  We
     21 ; keep the test-code but disabled, in case we need to change this again.
     22 move 0xaa,p0
     23 move 0x4433,p4
     24 move 0x55774433,p8
     25 .endif
     26
     27 moveq -1,r3
     28 setf zcvn
     29 clear.b r3
     30 test_cc 1 1 1 1
     31 checkr3 ffffff00
     32
     33 moveq -1,r3
     34 clearf zcvn
     35 clear.w r3
     36 test_cc 0 0 0 0
     37 checkr3 ffff0000
     38
     39 moveq -1,r3
     40 clear.d r3
     41 checkr3 0
     42
     43; "Write" using ordinary memory references too.
     44 .if 0 ; See ".if 0" above.
     45 move.d filler,r6
     46 move [r6],p0
     47 move [r6],p4
     48 move [r6],p8
     49 .endif
     50
     51# ffffff00\nffff0000\n0\nffffff00\nffff0000\n0\nbb113344\n664433aa\ncc557788\nabcde012\nabcde000\n77880000\n0\n
     52
     53 moveq -1,r3
     54 clear.b r3
     55 checkr3 ffffff00
     56
     57 moveq -1,r3
     58 clear.w r3
     59 checkr3 ffff0000
     60
     61 moveq -1,r3
     62 clear.d r3
     63 checkr3 0
     64
     65; And postincremented.
     66 .if 0 ; See ".if 0" above.
     67 move [r6+],p0
     68 move [r6+],p4
     69 move [r6+],p8
     70 .endif
     71
     72# ffffff00\nffff0000\n0\nbb113344\n664433aa\ncc557788\nabcde012\nabcde000\n77880000\n0\n
     73
     74 moveq -1,r3
     75 clear.b r3
     76 checkr3 ffffff00
     77
     78 moveq -1,r3
     79 clear.w r3
     80 checkr3 ffff0000
     81
     82 moveq -1,r3
     83 clear.d r3
     84 checkr3 0
     85
     86; Now see that we can write to the registers too.
     87# bb113344\n664433aa\ncc557788\nabcde012\nabcde000\n77880000\n0\n
     88; [PC+]
     89 move.d filler,r9
     90 move 0xbb113344,srp
     91 move srp,r3
     92 checkr3 bb113344
     93
     94; [R+]
     95 move [r9+],srp
     96 move srp,r3
     97 checkr3 664433aa
     98
     99; [R]
    100 move [r9],srp
    101 move srp,r3
    102 checkr3 cc557788
    103
    104; And check writing to memory, clear and srp.
    105
    106 move.d filler,r9
    107 move 0xabcde012,srp
    108 setf zcvn
    109 move srp,[r9+]
    110 test_cc 1 1 1 1
    111 subq 4,r9
    112 move.d [r9],r3
    113 checkr3 abcde012
    114
    115 clearf zcvn
    116 clear.b [r9]
    117 test_cc 0 0 0 0
    118 move.d [r9],r3
    119 checkr3 abcde000
    120
    121 addq 2,r9
    122 clear.w [r9+]
    123 subq 2,r9
    124 move.d [r9],r3
    125 checkr3 77880000
    126
    127 clear.d [r9]
    128 move.d [r9],r3
    129 checkr3 0
    130
    131 quit