cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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test_dsp_r1_mthlip.c (1191B)

      1#include<stdio.h>
      2#include<assert.h>
      3
      4int main()
      5{
      6    int rs, ach, acl, dsp;
      7    int result, resulth, resultl;
      8
      9    dsp = 0x07;
     10    ach = 0x05;
     11    acl = 0xB4CB;
     12    rs  = 0x00FFBBAA;
     13    resulth = 0xB4CB;
     14    resultl = 0x00FFBBAA;
     15    result  = 0x27;
     16
     17    __asm
     18        ("wrdsp %0, 0x01\n\t"
     19         "mthi %1, $ac1\n\t"
     20         "mtlo %2, $ac1\n\t"
     21         "mthlip %3, $ac1\n\t"
     22         "mfhi %1, $ac1\n\t"
     23         "mflo %2, $ac1\n\t"
     24         "rddsp %0\n\t"
     25         : "+r"(dsp), "+r"(ach), "+r"(acl)
     26         : "r"(rs)
     27        );
     28    dsp = dsp & 0x3F;
     29    assert(dsp == result);
     30    assert(ach == resulth);
     31    assert(acl == resultl);
     32
     33    dsp = 0x1f;
     34    ach = 0x05;
     35    acl = 0xB4CB;
     36    rs  = 0x00FFBBAA;
     37    resulth = 0xB4CB;
     38    resultl = 0x00FFBBAA;
     39    result  = 0x3f;
     40
     41    __asm
     42        ("wrdsp %0, 0x01\n\t"
     43         "mthi %1, $ac1\n\t"
     44         "mtlo %2, $ac1\n\t"
     45         "mthlip %3, $ac1\n\t"
     46         "mfhi %1, $ac1\n\t"
     47         "mflo %2, $ac1\n\t"
     48         "rddsp %0\n\t"
     49         : "+r"(dsp), "+r"(ach), "+r"(acl)
     50         : "r"(rs)
     51        );
     52    dsp = dsp & 0x3F;
     53    assert(dsp == result);
     54    assert(ach == resulth);
     55    assert(acl == resultl);
     56
     57    return 0;
     58}