cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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test_fp0_sqrt.S (1750B)


      1#include "macros.inc"
      2#include "fpu.h"
      3
      4test_suite fp0_sqrt
      5
      6#if XCHAL_HAVE_FP_SQRT
      7
      8.macro  sqrt_seq r, a, y, t1, hn, h2, t5, h
      9    sqrt0.s     \y, \a
     10    const.s     \t1, 0
     11    maddn.s     \t1, \y, \y
     12    nexp01.s    \hn, \a
     13    const.s     \r, 3
     14    addexp.s    \hn, \r
     15    maddn.s     \r, \t1, \hn
     16    nexp01.s    \t1, \a
     17    neg.s       \h2, \t1
     18    maddn.s     \y, \r, \y
     19    const.s     \r, 0
     20    const.s     \t5, 0
     21    const.s     \h, 0
     22    maddn.s     \r, \h2, \y
     23    maddn.s     \t5, \y, \hn
     24    const.s     \hn, 3
     25    maddn.s     \h, \hn, \y
     26    maddn.s     \t1, \r, \r
     27    maddn.s     \hn, \t5, \y
     28    neg.s       \y, \h
     29    maddn.s     \r, \t1, \y
     30    maddn.s     \h, \hn, \h
     31    mksadj.s    \y, \a
     32    nexp01.s    \a, \a
     33    maddn.s     \a, \r, \r
     34    neg.s       \t1, \h
     35    addexpm.s   \r, \y
     36    addexp.s    \t1, \y
     37    divn.s      \r, \a, \t1
     38.endm
     39
     40.macro sqrt_s fr0, fr1
     41    sqrt_seq    \fr0, \fr1, f10, f11, f12, f13, f14, f15
     42.endm
     43
     44.macro movfp fr, v
     45    movi        a2, \v
     46    wfr         \fr, a2
     47.endm
     48
     49.macro check_res fr, r, sr
     50    rfr         a2, \fr
     51    dump        a2
     52    movi        a3, \r
     53    assert      eq, a2, a3
     54    rur         a2, fsr
     55    movi        a3, \sr
     56    assert      eq, a2, a3
     57.endm
     58
     59test sqrt_s
     60    movi        a2, 1
     61    wsr         a2, cpenable
     62
     63    test_op1    sqrt_s, f0, f1, 0x40000000, \
     64        0x3fb504f3, 0x3fb504f3, 0x3fb504f4, 0x3fb504f3, \
     65             FSR_I,      FSR_I,      FSR_I,      FSR_I
     66    test_op1    sqrt_s, f3, f4, F32_1, \
     67        F32_1, F32_1, F32_1, F32_1, \
     68        FSR__, FSR__, FSR__, FSR__
     69    test_op1    sqrt_s, f6, f7, F32_MINUS | F32_1, \
     70        F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \
     71           FSR_V,    FSR_V,    FSR_V,    FSR_V
     72test_end
     73
     74#endif
     75
     76test_suite_end