cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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test_fp1.S (4296B)


      1#include "macros.inc"
      2#include "fpu.h"
      3
      4test_suite fp1
      5
      6#if XCHAL_HAVE_FP
      7
      8.macro movfp fr, v
      9    movi    a2, \v
     10    wfr     \fr, a2
     11.endm
     12
     13.macro test_ord_ex op, br, fr0, fr1, v0, v1, r, sr
     14    movi    a2, 0
     15    wur     a2, fsr
     16    movfp   \fr0, \v0
     17    movfp   \fr1, \v1
     18    \op     \br, \fr0, \fr1
     19    movi    a2, 0
     20    movi    a3, 1
     21    movt    a2, a3, \br
     22    assert  eqi, a2, \r
     23    rur     a2, fsr
     24#if DFPU
     25    movi    a3, \sr
     26    assert  eq, a2, a3
     27#else
     28    assert  eqi, a2, 0
     29#endif
     30.endm
     31
     32.macro test_ord op, br, fr0, fr1, v0, v1, r, sr
     33    movi    a2, 0
     34    wur     a2, fcr
     35    test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r, \sr
     36    movi    a2, 0x7c
     37    wur     a2, fcr
     38    test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r, \sr
     39.endm
     40
     41.macro test_ord_all op, aa, ab, ba, aPI, PIa, aN, Na, II, IN, NI, qnan_sr
     42    test_ord \op  b0,  f0,  f1, 0x3f800000, 0x3f800000, \aa,  FSR__    /*   ord == ord */
     43    test_ord \op  b1,  f2,  f3, 0x3f800000, 0x3fc00000, \ab,  FSR__    /*   ord <  ord */
     44    test_ord \op  b2,  f4,  f5, 0x3fc00000, 0x3f800000, \ba,  FSR__    /*   ord >  ord */
     45    test_ord \op  b3,  f6,  f7, 0x3f800000, 0x7f800000, \aPI, FSR__    /*   ord   +INF */
     46    test_ord \op  b4,  f8,  f9, 0x7f800000, 0x3f800000, \PIa, FSR__    /*  +INF    ord */
     47    test_ord \op  b5, f10, f11, 0x3f800000, 0xffc00001, \aN,  \qnan_sr /*   ord  -QNaN */
     48    test_ord \op  b6, f12, f13, 0x3f800000, 0xff800001, \aN,  FSR_V    /*   ord  -SNaN */
     49    test_ord \op  b7, f14, f15, 0x3f800000, 0x7f800001, \aN,  FSR_V    /*   ord  +SNaN */
     50    test_ord \op  b8,  f0,  f1, 0x3f800000, 0x7fc00000, \aN,  \qnan_sr /*   ord  +QNaN */
     51    test_ord \op  b9,  f2,  f3, 0xffc00001, 0x3f800000, \Na,  \qnan_sr /* -QNaN    ord */
     52    test_ord \op b10,  f4,  f5, 0xff800001, 0x3f800000, \Na,  FSR_V    /* -SNaN    ord */
     53    test_ord \op b11,  f6,  f7, 0x7f800001, 0x3f800000, \Na,  FSR_V    /* +SNaN    ord */
     54    test_ord \op b12,  f8,  f9, 0x7fc00000, 0x3f800000, \Na,  \qnan_sr /* +QNaN    ord */
     55    test_ord \op b13, f10, f11, 0x7f800000, 0x7f800000, \II,  FSR__    /*  +INF   +INF */
     56    test_ord \op b14, f12, f13, 0x7f800000, 0x7fc00000, \IN,  \qnan_sr /*  +INF  +QNaN */
     57    test_ord \op b15, f14, f15, 0x7fc00000, 0x7f800000, \NI,  \qnan_sr /* +QNaN   +INF */
     58.endm
     59
     60test un_s
     61    movi    a2, 1
     62    wsr     a2, cpenable
     63    test_ord_all un.s, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, FSR__
     64test_end
     65
     66test oeq_s
     67    test_ord_all oeq.s, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, FSR__
     68test_end
     69
     70test ueq_s
     71    test_ord_all ueq.s, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, FSR__
     72test_end
     73
     74test olt_s
     75    test_ord_all olt.s, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, FSR_V
     76test_end
     77
     78test ult_s
     79    test_ord_all ult.s, 0, 1, 0, 1, 0, 1, 1, 0, 1, 1, FSR__
     80test_end
     81
     82test ole_s
     83    test_ord_all ole.s, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, FSR_V
     84test_end
     85
     86test ule_s
     87    test_ord_all ule.s, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, FSR__
     88test_end
     89
     90.macro test_cond op, fr0, fr1, cr, v0, v1, r
     91    movfp   \fr0, \v0
     92    movfp   \fr1, \v1
     93    \op     \fr0, \fr1, \cr
     94    rfr     a2, \fr0
     95    movi    a3, \r
     96    assert  eq, a2, a3
     97.endm
     98
     99test moveqz_s
    100    movi    a3, 0
    101    test_cond moveqz.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
    102    movi    a3, 1
    103    test_cond moveqz.s, f0, f1, a3, 0, 0x3f800000, 0
    104test_end
    105
    106test movnez_s
    107    movi    a3, 0
    108    test_cond movnez.s, f0, f1, a3, 0, 0x3f800000, 0
    109    movi    a3, 1
    110    test_cond movnez.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
    111test_end
    112
    113test movltz_s
    114    movi    a3, -1
    115    test_cond movltz.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
    116    movi    a3, 0
    117    test_cond movltz.s, f0, f1, a3, 0, 0x3f800000, 0
    118    movi    a3, 1
    119    test_cond movltz.s, f0, f1, a3, 0, 0x3f800000, 0
    120test_end
    121
    122test movgez_s
    123    movi    a3, -1
    124    test_cond movgez.s, f0, f1, a3, 0, 0x3f800000, 0
    125    movi    a3, 0
    126    test_cond movgez.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
    127    movi    a3, 1
    128    test_cond movgez.s, f0, f1, a3, 0, 0x3f800000, 0x3f800000
    129test_end
    130
    131test movf_s
    132    olt.s   b0, f0, f0
    133    test_cond movf.s, f0, f1, b0, 0, 0x3f800000, 0x3f800000
    134    ueq.s   b0, f0, f0
    135    test_cond movf.s, f0, f1, b0, 0, 0x3f800000, 0
    136test_end
    137
    138test movt_s
    139    ueq.s   b0, f0, f0
    140    test_cond movt.s, f0, f1, b0, 0, 0x3f800000, 0x3f800000
    141    olt.s   b0, f0, f0
    142    test_cond movt.s, f0, f1, b0, 0, 0x3f800000, 0
    143test_end
    144
    145#endif
    146
    147test_suite_end