cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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test_lsc.S (4698B)


      1#include "macros.inc"
      2#include "fpu.h"
      3
      4test_suite lsc
      5
      6#if XCHAL_HAVE_FP
      7
      8test lsi
      9    movi    a2, 1
     10    wsr     a2, cpenable
     11
     12    movi    a2, 1f
     13    lsi     f1, a2, 4
     14#if DFPU
     15    lsi     f2, a2, 8
     16    lsip    f0, a2, 8
     17#else
     18    lsi     f0, a2, 0
     19    lsiu    f2, a2, 8
     20#endif
     21    movi    a3, 1f + 8
     22    assert  eq, a2, a3
     23    rfr     a2, f0
     24    movi    a3, 0x3f800000
     25    assert  eq, a2, a3
     26    rfr     a2, f1
     27    movi    a3, 0x40000000
     28    assert  eq, a2, a3
     29    rfr     a2, f2
     30    movi    a3, 0x40400000
     31    assert  eq, a2, a3
     32.data
     33    .align  4
     341:
     35.float 1, 2, 3
     36.text
     37test_end
     38
     39test ssi
     40    movi    a2, 1f
     41    movi    a3, 0x40800000
     42    wfr     f3, a3
     43    movi    a3, 0x40a00000
     44    wfr     f4, a3
     45    movi    a3, 0x40c00000
     46    wfr     f5, a3
     47    ssi     f4, a2, 4
     48#if DFPU
     49    ssi     f5, a2, 8
     50    ssip    f3, a2, 8
     51#else
     52    ssi     f3, a2, 0
     53    ssiu    f5, a2, 8
     54#endif
     55    movi    a3, 1f + 8
     56    assert  eq, a2, a3
     57    l32i    a4, a2, -8
     58    movi    a3, 0x40800000
     59    assert  eq, a4, a3
     60    l32i    a4, a2, -4
     61    movi    a3, 0x40a00000
     62    assert  eq, a4, a3
     63    l32i    a4, a2, 0
     64    movi    a3, 0x40c00000
     65    assert  eq, a4, a3
     66.data
     67    .align  4
     681:
     69.float 0, 0, 0
     70.text
     71test_end
     72
     73test lsx
     74    movi    a2, 1f
     75    movi    a3, 0
     76    movi    a4, 4
     77    movi    a5, 8
     78    lsx     f7, a2, a4
     79#if DFPU
     80    lsx     f8, a2, a5
     81    lsxp    f6, a2, a5
     82#else
     83    lsx     f6, a2, a3
     84    lsxu    f8, a2, a5
     85#endif
     86    movi    a3, 1f + 8
     87    assert  eq, a2, a3
     88    rfr     a2, f6
     89    movi    a3, 0x40e00000
     90    assert  eq, a2, a3
     91    rfr     a2, f7
     92    movi    a3, 0x41000000
     93    assert  eq, a2, a3
     94    rfr     a2, f8
     95    movi    a3, 0x41100000
     96    assert  eq, a2, a3
     97.data
     98    .align  4
     991:
    100.float 7, 8, 9
    101.text
    102test_end
    103
    104test ssx
    105    movi    a2, 1f
    106    movi    a4, 0x41200000
    107    wfr     f9, a4
    108    movi    a4, 0x41300000
    109    wfr     f10, a4
    110    movi    a4, 0x41400000
    111    wfr     f11, a4
    112    movi    a3, 0
    113    movi    a4, 4
    114    movi    a5, 8
    115    ssx     f10, a2, a4
    116#if DFPU
    117    ssx     f11, a2, a5
    118    ssxp    f9, a2, a5
    119#else
    120    ssx     f9, a2, a3
    121    ssxu    f11, a2, a5
    122#endif
    123    movi    a3, 1f + 8
    124    assert  eq, a2, a3
    125    l32i    a4, a2, -8
    126    movi    a3, 0x41200000
    127    assert  eq, a4, a3
    128    l32i    a4, a2, -4
    129    movi    a3, 0x41300000
    130    assert  eq, a4, a3
    131    l32i    a4, a2, 0
    132    movi    a3, 0x41400000
    133    assert  eq, a4, a3
    134.data
    135    .align  4
    1361:
    137.float 0, 0, 0
    138.text
    139test_end
    140
    141#endif
    142
    143#if XCHAL_HAVE_DFP
    144
    145#if XCHAL_HAVE_BE
    146#define F64_HIGH_OFF 0
    147#else
    148#define F64_HIGH_OFF 4
    149#endif
    150
    151.macro movdf fr, hi, lo
    152    movi    a2, \hi
    153    movi    a3, \lo
    154    wfrd    \fr, a2, a3
    155.endm
    156
    157test ldi
    158    movi    a2, 1
    159    wsr     a2, cpenable
    160
    161    movi    a2, 1f
    162    ldi     f1, a2, 8
    163    ldi     f2, a2, 16
    164    ldip    f0, a2, 16
    165    movi    a3, 1f + 16
    166    assert  eq, a2, a3
    167    rfrd    a2, f0
    168    movi    a3, 0x3ff00000
    169    assert  eq, a2, a3
    170    rfrd    a2, f1
    171    movi    a3, 0x40000000
    172    assert  eq, a2, a3
    173    rfrd    a2, f2
    174    movi    a3, 0x40080000
    175    assert  eq, a2, a3
    176.data
    177    .align  8
    1781:
    179.double 1, 2, 3
    180.text
    181test_end
    182
    183test sdi
    184    movdf   f3, 0x40800000, 0
    185    movdf   f4, 0x40a00000, 0
    186    movdf   f5, 0x40c00000, 0
    187    movi    a2, 1f
    188    sdi     f4, a2, 8
    189    sdi     f5, a2, 16
    190    sdip    f3, a2, 16
    191    movi    a3, 1f + 16
    192    assert  eq, a2, a3
    193    l32i    a4, a2, -16 + F64_HIGH_OFF
    194    movi    a3, 0x40800000
    195    assert  eq, a4, a3
    196    l32i    a4, a2, -8 + F64_HIGH_OFF
    197    movi    a3, 0x40a00000
    198    assert  eq, a4, a3
    199    l32i    a4, a2, F64_HIGH_OFF
    200    movi    a3, 0x40c00000
    201    assert  eq, a4, a3
    202.data
    203    .align  8
    2041:
    205.double 0, 0, 0
    206.text
    207test_end
    208
    209test ldx
    210    movi    a2, 1f
    211    movi    a3, 0
    212    movi    a4, 8
    213    movi    a5, 16
    214    ldx     f7, a2, a4
    215    ldx     f8, a2, a5
    216    ldxp    f6, a2, a5
    217    movi    a3, 1f + 16
    218    assert  eq, a2, a3
    219    rfrd    a2, f6
    220    movi    a3, 0x401c0000
    221    assert  eq, a2, a3
    222    rfrd    a2, f7
    223    movi    a3, 0x40200000
    224    assert  eq, a2, a3
    225    rfrd    a2, f8
    226    movi    a3, 0x40220000
    227    assert  eq, a2, a3
    228.data
    229    .align  8
    2301:
    231.double 7, 8, 9
    232.text
    233test_end
    234
    235test sdx
    236    movdf   f9, 0x41200000, 0
    237    movdf   f10, 0x41300000, 0
    238    movdf   f11, 0x41400000, 0
    239    movi    a2, 1f
    240    movi    a3, 0
    241    movi    a4, 8
    242    movi    a5, 16
    243    sdx     f10, a2, a4
    244    sdx     f11, a2, a5
    245    sdxp    f9, a2, a5
    246    movi    a3, 1f + 16
    247    assert  eq, a2, a3
    248    l32i    a4, a2, -16 + F64_HIGH_OFF
    249    movi    a3, 0x41200000
    250    assert  eq, a4, a3
    251    l32i    a4, a2, -8 + F64_HIGH_OFF
    252    movi    a3, 0x41300000
    253    assert  eq, a4, a3
    254    l32i    a4, a2, F64_HIGH_OFF
    255    movi    a3, 0x41400000
    256    assert  eq, a4, a3
    257.data
    258    .align  8
    2591:
    260.double 0, 0, 0
    261.text
    262test_end
    263
    264#endif
    265
    266test_suite_end