cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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test_shift.S (3933B)


      1#include "macros.inc"
      2
      3test_suite shift
      4
      5.macro test_shift prefix, dst, src, v, imm
      6    \prefix\()_set \dst, \src, \v, \imm
      7    \prefix\()_ver \dst, \v, \imm
      8.endm
      9
     10.macro test_shift_sd prefix, v, imm
     11    test_shift \prefix, a3, a2, \v, \imm
     12    test_shift \prefix, a2, a2, \v, \imm
     13.endm
     14
     15.macro tests_imm_shift prefix, v
     16    test_shift_sd \prefix, \v, 1
     17    test_shift_sd \prefix, \v, 2
     18    test_shift_sd \prefix, \v, 7
     19    test_shift_sd \prefix, \v, 8
     20    test_shift_sd \prefix, \v, 15
     21    test_shift_sd \prefix, \v, 16
     22    test_shift_sd \prefix, \v, 31
     23.endm
     24
     25.macro tests_shift prefix, v
     26    test_shift_sd \prefix, \v, 0
     27    tests_imm_shift \prefix, \v
     28    test_shift_sd \prefix, \v, 32
     29.endm
     30
     31
     32.macro slli_set dst, src, v, imm
     33    movi    \src, \v
     34    slli    \dst, \src, \imm
     35.endm
     36
     37.macro slli_ver dst, v, imm
     38    mov     a2, \dst
     39    movi    a3, ((\v) << (\imm)) & 0xffffffff
     40    assert  eq, a2, a3
     41.endm
     42
     43test slli
     44    tests_imm_shift slli, 0xa3c51249
     45test_end
     46
     47
     48.macro srai_set dst, src, v, imm
     49    movi    \src, \v
     50    srai    \dst, \src, \imm
     51.endm
     52
     53.macro srai_ver dst, v, imm
     54    mov     a2, \dst
     55    .if (\imm)
     56    movi    a3, (((\v) >> (\imm)) & 0xffffffff) | \
     57                ~((((\v) & 0x80000000) >> ((\imm) - 1)) - 1)
     58    .else
     59    movi    a3, \v
     60    .endif
     61    assert  eq, a2, a3
     62.endm
     63
     64test srai
     65    tests_imm_shift srai, 0x49a3c512
     66    tests_imm_shift srai, 0xa3c51249
     67test_end
     68
     69
     70.macro srli_set dst, src, v, imm
     71    movi    \src, \v
     72    srli    \dst, \src, \imm
     73.endm
     74
     75.macro srli_ver dst, v, imm
     76    mov     a2, \dst
     77    movi    a3, (((\v) >> (\imm)) & 0xffffffff)
     78    assert  eq, a2, a3
     79.endm
     80
     81test srli
     82    tests_imm_shift srli, 0x49a3c512
     83    tests_imm_shift srli, 0xa3c51249
     84test_end
     85
     86
     87.macro sll_set dst, src, v, imm
     88    movi    a2, \imm
     89    ssl     a2
     90    movi    \src, \v
     91    sll     \dst, \src
     92.endm
     93
     94.macro sll_sar_set dst, src, v, imm
     95    movi    a2, 32 - \imm
     96    wsr     a2, sar
     97    movi    \src, \v
     98    sll     \dst, \src
     99.endm
    100
    101.macro sll_ver dst, v, imm
    102    slli_ver \dst, \v, (\imm) & 0x1f
    103.endm
    104
    105.macro sll_sar_ver dst, v, imm
    106    slli_ver \dst, \v, \imm
    107.endm
    108
    109test sll
    110    tests_shift sll, 0xa3c51249
    111    tests_shift sll_sar, 0xa3c51249
    112test_end
    113
    114
    115.macro srl_set dst, src, v, imm
    116    movi    a2, \imm
    117    ssr     a2
    118    movi    \src, \v
    119    srl     \dst, \src
    120.endm
    121
    122.macro srl_sar_set dst, src, v, imm
    123    movi    a2, \imm
    124    wsr     a2, sar
    125    movi    \src, \v
    126    srl     \dst, \src
    127.endm
    128
    129.macro srl_ver dst, v, imm
    130    srli_ver \dst, \v, (\imm) & 0x1f
    131.endm
    132
    133.macro srl_sar_ver dst, v, imm
    134    srli_ver \dst, \v, \imm
    135.endm
    136
    137test srl
    138    tests_shift srl, 0xa3c51249
    139    tests_shift srl_sar, 0xa3c51249
    140    tests_shift srl, 0x49a3c512
    141    tests_shift srl_sar, 0x49a3c512
    142test_end
    143
    144
    145.macro sra_set dst, src, v, imm
    146    movi    a2, \imm
    147    ssr     a2
    148    movi    \src, \v
    149    sra     \dst, \src
    150.endm
    151
    152.macro sra_sar_set dst, src, v, imm
    153    movi    a2, \imm
    154    wsr     a2, sar
    155    movi    \src, \v
    156    sra     \dst, \src
    157.endm
    158
    159.macro sra_ver dst, v, imm
    160    srai_ver \dst, \v, (\imm) & 0x1f
    161.endm
    162
    163.macro sra_sar_ver dst, v, imm
    164    srai_ver \dst, \v, \imm
    165.endm
    166
    167test sra
    168    tests_shift sra, 0xa3c51249
    169    tests_shift sra_sar, 0xa3c51249
    170    tests_shift sra, 0x49a3c512
    171    tests_shift sra_sar, 0x49a3c512
    172test_end
    173
    174
    175.macro src_set dst, src, v, imm
    176    movi    a2, \imm
    177    ssr     a2
    178    movi    \src, (\v) & 0xffffffff
    179    movi    a4, (\v) >> 32
    180    src     \dst, a4, \src
    181.endm
    182
    183.macro src_sar_set dst, src, v, imm
    184    movi    a2, \imm
    185    wsr     a2, sar
    186    movi    \src, (\v) & 0xffffffff
    187    movi    a4, (\v) >> 32
    188    src     \dst, a4, \src
    189.endm
    190
    191.macro src_ver dst, v, imm
    192    src_sar_ver \dst, \v, (\imm) & 0x1f
    193.endm
    194
    195.macro src_sar_ver dst, v, imm
    196    mov     a2, \dst
    197    movi    a3, ((\v) >> (\imm)) & 0xffffffff
    198    assert  eq, a2, a3
    199.endm
    200
    201test src
    202    tests_shift src, 0xa3c51249215c3a94
    203    tests_shift src_sar, 0xa3c51249215c3a94
    204test_end
    205
    206test_suite_end