test_sr.S (3996B)
1#include "macros.inc" 2 3test_suite sr 4 5#if XCHAL_HAVE_BE 6#define LOW__SR 0x04 7#define HI_RSR 0x30 8#define HI_WSR 0x31 9#define HI_XSR 0x16 10#else 11#define LOW__SR 0x40 12#define HI_RSR 0x03 13#define HI_WSR 0x13 14#define HI_XSR 0x61 15#endif 16 17.macro sr_op sym, op_sym, op_byte, sr 18 .if \sym 19 \op_sym a4, \sr 20 .else 21 .byte LOW__SR, \sr, \op_byte 22 .endif 23.endm 24 25.macro test_sr_op sym, mask, op, op_byte, sr 26 movi a4, 0 27 .if (\mask) 28 set_vector kernel, 0 29 sr_op \sym, \op, \op_byte, \sr 30 .else 31 set_vector kernel, 2f 321: 33 sr_op \sym, \op, \op_byte, \sr 34 test_fail 352: 36 reset_ps 37 rsr a2, exccause 38 assert eqi, a2, 0 39 rsr a2, epc1 40 movi a3, 1b 41 assert eq, a2, a3 42 .endif 43.endm 44 45.macro test_sr_mask sr, sym, mask 46test \sr 47 test_sr_op \sym, \mask & 1, rsr, HI_RSR, \sr 48 test_sr_op \sym, \mask & 2, wsr, HI_WSR, \sr 49 test_sr_op \sym, \mask & 4, xsr, HI_XSR, \sr 50test_end 51.endm 52 53.macro test_sr sr, conf 54 test_sr_mask \sr, \conf, 7 55.endm 56 57#if XCHAL_HAVE_MAC16 58test_sr acchi, 1 59test_sr acclo, 1 60#else 61test_sr_mask /*acchi*/17, 0, 0 62test_sr_mask /*acclo*/16, 0, 0 63#endif 64 65#if XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000 66test_sr atomctl, 1 67#else 68test_sr_mask /*atomctl*/99, 0, 0 69#endif 70 71#if XCHAL_HAVE_BOOLEANS 72test_sr br, 1 73#else 74test_sr_mask /*br*/4, 0, 0 75#endif 76 77test_sr_mask /*cacheattr*/98, 0, 0 78 79#if XCHAL_HAVE_CCOUNT 80test_sr ccompare0, 1 81test_sr ccount, 1 82#else 83test_sr_mask /*ccompare0*/240, 0, 0 84test_sr_mask /*ccount*/234, 0, 0 85#endif 86 87#if XCHAL_HAVE_CP 88test_sr cpenable, 1 89#else 90test_sr_mask /*cpenable*/224, 0, 0 91#endif 92 93#if XCHAL_HAVE_DEBUG 94#if XCHAL_NUM_DBREAK 95test_sr dbreaka0, 1 96test_sr dbreakc0, 1 97#endif 98test_sr_mask debugcause, 1, 1 99#else 100test_sr_mask /*dbreaka0*/144, 0, 0 101test_sr_mask /*dbreakc0*/160, 0, 0 102test_sr_mask /*debugcause*/233, 0, 0 103#endif 104 105test_sr depc, 1 106 107#if XCHAL_HAVE_PTP_MMU 108test_sr dtlbcfg, 1 109#else 110test_sr_mask /*dtlbcfg*/92, 0, 0 111#endif 112 113test_sr epc1, 1 114 115#if XCHAL_NUM_INTLEVELS > 1 116test_sr epc2, 1 117test_sr eps2, 1 118#else 119test_sr_mask /*epc2*/178, 0, 0 120test_sr_mask /*eps2*/194, 0, 0 121#endif 122 123test_sr exccause, 1 124test_sr excsave1, 1 125 126#if XCHAL_NUM_INTLEVELS > 1 127test_sr excsave2, 1 128#else 129test_sr_mask /*excsave2*/210, 0, 0 130#endif 131 132test_sr excvaddr, 1 133 134#if XCHAL_HAVE_DEBUG 135#if XCHAL_NUM_IBREAK 136test_sr ibreaka0, 1 137test_sr ibreakenable, 1 138#endif 139test_sr icount, 1 140test_sr icountlevel, 1 141#else 142test_sr_mask /*ibreaka0*/128, 0, 0 143test_sr_mask /*ibreakenable*/96, 0, 0 144test_sr_mask /*icount*/236, 0, 0 145test_sr_mask /*icountlevel*/237, 0, 0 146#endif 147 148test_sr_mask /*intclear*/227, 0, 2 149test_sr_mask /*interrupt*/226, 0, 3 150test_sr intenable, 1 151 152#if XCHAL_HAVE_PTP_MMU 153test_sr itlbcfg, 1 154#else 155test_sr_mask /*itlbcfg*/91, 0, 0 156#endif 157 158#if XCHAL_HAVE_LOOPS 159test_sr lbeg, 1 160test_sr lcount, 1 161test_sr lend, 1 162#else 163test_sr_mask /*lbeg*/0, 0, 0 164test_sr_mask /*lcount*/2, 0, 0 165test_sr_mask /*lend*/1, 0, 0 166#endif 167 168#if XCHAL_HAVE_ABSOLUTE_LITERALS 169test_sr litbase, 1 170#else 171test_sr_mask /*litbase*/5, 0, 0 172#endif 173 174#if XCHAL_HAVE_MAC16 175test_sr m0, 1 176#else 177test_sr_mask /*m0*/32, 0, 0 178#endif 179 180#if XCHAL_HW_VERSION >= 250000 181test_sr_mask /*memctl*/97, 0, 7 182#else 183test_sr_mask /*memctl*/97, 0, 0 184#endif 185 186#if XCHAL_NUM_MISC_REGS 187test_sr misc0, 1 188#else 189test_sr_mask /*misc0*/244, 0, 0 190#endif 191 192#if XCHAL_HAVE_PREFETCH 193test_sr prefctl, 1 194#else 195test_sr_mask /*prefctl*/40, 0, 0 196#endif 197 198#if XCHAL_HAVE_PRID 199test_sr_mask /*prid*/235, 0, 1 200#else 201test_sr_mask /*prid*/235, 0, 0 202#endif 203 204test_sr ps, 1 205 206#if XCHAL_HAVE_PTP_MMU 207test_sr ptevaddr, 1 208test_sr rasid, 1 209#else 210test_sr_mask /*ptevaddr*/83, 0, 0 211test_sr_mask /*rasid*/90, 0, 0 212#endif 213 214test_sr sar, 1 215 216#if XCHAL_HAVE_S32C1I 217test_sr scompare1, 1 218#else 219test_sr_mask /*scompare1*/12, 0, 0 220#endif 221 222#if XCHAL_HAVE_VECBASE 223test_sr vecbase, 1 224#else 225test_sr_mask /*vecbase*/231, 0, 0 226#endif 227 228#if XCHAL_HAVE_WINDOWED 229test_sr windowbase, 1 230test_sr windowstart, 1 231#else 232test_sr_mask /*windowbase*/72, 0, 0 233test_sr_mask /*windowstart*/73, 0, 0 234#endif 235 236test_suite_end