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* softmmu: Add probe_write()Yongbok Kim2015-06-111-0/+2
| | | | | | | | | | | | Probe for whether the specified guest write access is permitted. If it is not permitted then an exception will be taken in the same way as if this were a real write access (and we will not return). Otherwise the function will return, and there will be a valid entry in the TLB for this access. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* exec: move functions to translate-all.hPaolo Bonzini2015-06-051-5/+1
| | | | | | | | Remove them from the sundry exec-all.h header, since they are only used by the TCG runtime in exec.c and user-exec.c. Reviewed-by: Fam Zheng <famz@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Add MemTxAttrs to the IOTLBPeter Maydell2015-04-261-0/+3
| | | | | | | | | | | Add a MemTxAttrs field to the IOTLB, and allow target-specific code to set it via a new tlb_set_page_with_attrs() function; pass the attributes through to the device when making IO accesses. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
* memory: Replace io_mem_read/write with memory_region_dispatch_read/writePeter Maydell2015-04-261-4/+0
| | | | | | | | | | | | | | Rather than retaining io_mem_read/write as simple wrappers around the memory_region_dispatch_read/write functions, make the latter public and change all the callers to use them, since we need to touch all the callsites anyway to add MemTxAttrs and MemTxResult support. Delete io_mem_read and io_mem_write entirely. (All the callers currently pass MEMTXATTRS_UNSPECIFIED and convert the return value back to bool or ignore it.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
* exec: RCUify AddressSpaceDispatchPaolo Bonzini2015-02-161-0/+1
| | | | | | | | | | | Note that even after this patch, most callers of address_space_* functions must still be under the big QEMU lock, otherwise the memory region returned by address_space_translate can disappear as soon as address_space_translate returns. This will be fixed in the next part of this series. Reviewed-by: Fam Zheng <famz@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* exec: make iotlb RCU-friendlyPaolo Bonzini2015-02-161-1/+2
| | | | | | | | | | | | | After the previous patch, TLBs will be flushed on every change to the memory mapping. This patch augments that with synchronization of the MemoryRegionSections referred to in the iotlb array. With this change, it is guaranteed that iotlb_to_region will access the correct memory map, even once the TLB will be accessed outside the BQL. Reviewed-by: Fam Zheng <famz@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* exec: introduce cpu_reload_memory_mapPaolo Bonzini2015-02-161-0/+1
| | | | | | | | | | | | | This for now is a simple TLB flush. This can change later for two reasons: 1) an AddressSpaceDispatch will be cached in the CPUState object 2) it will not be possible to do tlb_flush once the TCG-generated code runs outside the BQL. Reviewed-by: Fam Zheng <famz@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* cpu-exec: add a new CF_USE_ICOUNT cflagPaolo Bonzini2014-12-231-2/+3
| | | | | Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* cpu-exec: invalidate nocache translation if they are interruptedPavel Dovgalyuk2014-12-151-0/+1
| | | | | | | | | In this case, QEMU might longjmp out of cpu-exec.c and miss the final cleanup in cpu_exec_nocache. Do this manually through a new compile flag. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* memory: expose alignment used for allocating RAM as MemoryRegion APIIgor Mammedov2014-11-231-1/+1
| | | | | | | | | | introduce memory_region_get_alignment() that returns underlying memory block alignment or 0 if it's not relevant/implemented for backend. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* cpu-exec: Make debug_excp_handler a QOM CPU methodPeter Maydell2014-09-121-4/+0
| | | | | | | Make the debug_excp_handler target specific hook into a QOM CPU method. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* tcg-ppc: Use uintptr_t in ppc_tb_set_jmp_targetRichard Henderson2014-06-231-1/+1
| | | | | Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* softmmu: move all load/store functions to cpu_ldst.hPaolo Bonzini2014-06-051-25/+0
| | | | | | | | Unify pieces of cpu-all.h, exec-all.h, softmmu_exec.h and tcg/tcg.h into a single new header file with all helpers. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* softmmu: move definition of CPU_MMU_INDEX to inclusion site, drop ACCESS_TYPEPaolo Bonzini2014-06-051-2/+2
| | | | | Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* softmmu: start introducing SOFTMMU_CODE_ACCESS in softmmu_header.hPaolo Bonzini2014-06-051-0/+2
| | | | | | | | | This preprocessor symbol is already used in softmmu_template.h. We will use it to distinguish the two "fake" ACCESS_TYPEs NB_MMU_MODES and NB_MMU_MODES + 1. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg-mips: Enable direct chaining of TBsRichard Henderson2014-05-241-2/+2
| | | | | | | | Now that the code_gen_buffer is constrained to not cross 256mb regions, we are assured that we can use J to reach another TB. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-s390: Implement direct chaining of TBsRichard Henderson2014-05-151-0/+9
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* exec-all.h: Use stl_le_p instead of stl_p patching x86Richard Henderson2014-05-131-1/+1
| | | | | | | | We got the wrong version of stl_p, the one that bswaps as appropriate for the target. Since x86 is always little-endian, the "_le_" routine will resolve to what we want. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Define tcg_insn_unit for code pointersRichard Henderson2014-05-121-1/+1
| | | | | | | | | To be defined by the tcg backend based on the elemental unit of the ISA. During the transition, allow TCG_TARGET_INSN_UNIT_SIZE to be undefined, which allows us to default tcg_insn_unit to the current uint8_t. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* exec-all.h: Use stl_p to avoid undefined behaviour patching x86 jumpsPeter Maydell2014-05-121-1/+1
| | | | | | | | | | | | | | | | | | | The code which patches x86 jump instructions assumes it can do an unaligned write of a uint32_t. This is actually safe on x86, but it's still undefined behaviour. We have infrastructure for doing efficient unaligned accesses which doesn't engage in undefined behaviour, so use it. This is technically fractionally less efficient, at least with gcc 4.6; instead of one instruction: 7b2: 89 3e mov %edi,(%rsi) we get an extra spurious store to the stack slot: 7b2: 89 7c 24 64 mov %edi,0x64(%rsp) 7b6: 89 3e mov %edi,(%rsi) Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoderPeter Maydell2014-03-171-1/+1
| | | | | | | | | | The ARM A64 decoder's worst case number of TCG ops per instruction is 266 (for insn 0x4c800000, a post-indexed ST4 multiple-structures store). Raise the MAX_OP_PER_INSTR define accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1394822294-14837-17-git-send-email-peter.maydell@linaro.org
* cputlb: Change tlb_set_page() argument to CPUStateAndreas Färber2014-03-131-1/+1
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* cputlb: Change tlb_flush() argument to CPUStateAndreas Färber2014-03-131-2/+2
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* cputlb: Change tlb_flush_page() argument to CPUStateAndreas Färber2014-03-131-2/+2
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu-exec: Change cpu_resume_from_signal() argument to CPUStateAndreas Färber2014-03-131-1/+1
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* translate-all: Change tb_gen_code() argument to CPUStateAndreas Färber2014-03-131-1/+1
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* translate-all: Change cpu_io_recompile() argument to CPUStateAndreas Färber2014-03-131-1/+1
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* translate-all: Change cpu_restore_state() argument to CPUStateAndreas Färber2014-03-131-1/+1
| | | | | | This lets us drop some local variables in tlb_fill() functions. Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu-exec: Change cpu_loop_exit() argument to CPUStateAndreas Färber2014-03-131-1/+1
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* exec: Change tlb_fill() argument to CPUStateAndreas Färber2014-03-131-1/+1
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Move can_do_io field from CPU_COMMON to CPUStateAndreas Färber2014-03-131-8/+13
| | | | | | Rename can_do_io() to cpu_can_do_io() and change argument to CPUState. Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Add per-cpu address spaceEdgar E. Iglesias2014-02-111-0/+1
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* exec: Make iotlb_to_region input an ASEdgar E. Iglesias2014-02-111-1/+1
| | | | | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* exec: Make tb_invalidate_phys_addr input an ASEdgar E. Iglesias2014-02-111-1/+1
| | | | | | | No functional change. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* kvm: initialize qemu_host_page_sizeAlexey Kardashevskiy2014-01-171-0/+1
| | | | | | | | | | | | | There is a HOST_PAGE_ALIGN macro which makes sense for KVM accelerator but it uses qemu_host_page_size/qemu_host_page_mask which initialized for TCG only. This moves qemu_host_page_size/qemu_host_page_mask initialization from TCG's page_init() and adds a call for it from kvm_init(). Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
* exec: Fix prototype of phys_mem_set_alloc and related functionsStefan Weil2013-10-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | phys_mem_alloc and its assigned values qemu_anon_ram_alloc and legacy_s390_alloc must have identical argument lists. legacy_s390_alloc uses the size parameter to call mmap, so size_t is good enough for all of them. This patch fixes compiler errors on i686 Linux hosts: CC alpha-softmmu/exec.o exec.c:752:51: error: initialization from incompatible pointer type [-Werror] exec.c: In function 'qemu_ram_alloc_from_ptr': exec.c:1139:32: error: comparison of distinct pointer types lacks a cast [-Werror] exec.c: In function 'qemu_ram_remap': exec.c:1283:21: error: comparison of distinct pointer types lacks a cast [-Werror] Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-id: 1380481005-32399-1-git-send-email-sw@weilnetz.de Signed-off-by: Anthony Liguori <aliguori@amazon.com>
* exec: Delete is_tcg_gen_code and GETRA_EXTRichard Henderson2013-10-101-12/+0
| | | | | | All implementations now boil down to GETRA. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-aarch64: Update to helper_ret_*_mmu routinesRichard Henderson2013-10-101-18/+0
| | | | | | | | A minimal update to use the new helpers with the return address argument. Tested-by: Claudio Fontana <claudio.fontana@linaro.org> Reviewed-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-arm: Rearrange slow-path qemu_ld/stRichard Henderson2013-10-011-15/+1
| | | | | | | | Use the new helper_ret_*_mmu routines. Use a conditional call to arrange for a tail-call from the store path, and to load the return address for the helper for the load path. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-ppc: use new return-argument ld/st helpersPaolo Bonzini2013-09-251-3/+1
| | | | | | | | | | | These use a 32-bit load-of-immediate to save a mflr+addi+mtlr sequence. Tested with a Windows 98 guest (pretty much the most recent thing I could run on my PPC machine) and kvm-unit-tests's sieve.flat. The speed up for sieve.flat is as high as 10% for qemu-system-i386, 25% (no kidding) for qemu-system-x86_64 on my PowerBook G4. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* exec: Simplify the guest physical memory allocation hookMarkus Armbruster2013-09-121-0/+2
| | | | | | | | | | | | | | | Make it a generic hook rather than a KVM hook. Less code and ifdeffery. Since the only user of the hook is old S390 KVM, there's hope we can get rid of it some day. Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Message-id: 1375276272-15988-5-git-send-email-armbru@redhat.com Signed-off-by: Anthony Liguori <anthony@codemonkey.ws>
* exec: Split softmmu_defs.hRichard Henderson2013-09-021-1/+4
| | | | | | | | | | | The _cmmu helpers can be moved to exec-all.h. The helpers that are used from TCG will shortly need access to tcg_target_long so move their declarations into tcg.h. This requires minor include adjustments to all TCG backends. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* exec: Reorganize the GETRA/GETPC macrosRichard Henderson2013-09-021-45/+39
| | | | | | | | | | | | | | | | | | Always define GETRA; use __builtin_extract_return_addr, rather than having a special case for s390. Split GETPC_ADJ out of GETPC; use 2 universally, rather than having a special case for arm. Rename GETPC_LDST to GETRA_LDST to indicate that it does not contain the GETPC_ADJ value. Likewise with GETPC_EXT to GETRA_EXT. Perform the GETPC_ADJ adjustment inside helper_ret_ld/st. This will allow backends to pass along the "true" return address rather than the massaged GETPC value. In the meantime, double application of GETPC_ADJ does not hurt, since the call insn in all ISAs is at least 4 bytes long. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-i386: Remove abort from GETPC_LDSTRichard Henderson2013-08-291-5/+5
| | | | | | | | | | | | | Indeed, remove it entirely and remove the is_tcg_gen_code check from GETPC_EXT. Fixes https://bugs.launchpad.net/qemu/+bug/1218098 wherein a call to a "normal" helper function performed a sequence of tail calls all the way into the memory helper functions, leading to a stack frame in which the memory helper function appeared to be called directly from tcg. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg-i386: Use new return-argument ld/st helpersRichard Henderson2013-08-261-11/+2
| | | | | | | | | Discontinue the jump-around-jump-to-jump scheme, trading it for a single immediate move instruction. The two extra jumps always consume 7 bytes, whereas the immediate move is either 5 or 7 bytes depending on where the code_gen_buffer gets located. Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg/aarch64: Implement tlb lookup fast pathJani Kokkonen2013-07-151-0/+14
| | | | | | | | Supports CONFIG_QEMU_LDST_OPTIMIZATION Signed-off-by: Jani Kokkonen <jani.kokkonen@huawei.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
* tcg/aarch64: implement new TCG target for aarch64Claudio Fontana2013-06-121-1/+4
| | | | | | | | | | add preliminary support for TCG target aarch64. Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 51A5C596.3090108@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* memory: propagate errors on I/O dispatchPaolo Bonzini2013-05-291-3/+3
| | | | | Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg-arm: Convert to CONFIG_QEMU_LDST_OPTIMIZATIONRichard Henderson2013-04-271-0/+17
| | | | | | | | Move the slow path out of line, as the TODO's mention. This allows the fast path to be unconditional, which can speed up the fast path as well, depending on the core. Signed-off-by: Richard Henderson <rth@twiddle.net>
* cpu: Move current_tb field to CPUStateAndreas Färber2013-02-161-1/+3
| | | | | | | | | | Explictly NULL it on CPU reset since it was located before breakpoints. Change vapic_report_tpr_access() argument to CPUState. This also resolves the use of void* for cpu.h independence. Change vAPIC patch_instruction() argument to X86CPU. Signed-off-by: Andreas Färber <afaerber@suse.de>
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